2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
55 memset(this, 0, sizeof(*this));
56 this->opcode = BRW_OPCODE_NOP;
57 this->conditional_mod = BRW_CONDITIONAL_NONE;
59 this->dst = reg_undef;
60 this->src[0] = reg_undef;
61 this->src[1] = reg_undef;
62 this->src[2] = reg_undef;
70 fs_inst::fs_inst(enum opcode opcode)
73 this->opcode = opcode;
76 fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
79 this->opcode = opcode;
83 assert(dst.reg_offset >= 0);
86 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
89 this->opcode = opcode;
94 assert(dst.reg_offset >= 0);
95 if (src[0].file == GRF)
96 assert(src[0].reg_offset >= 0);
99 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
102 this->opcode = opcode;
108 assert(dst.reg_offset >= 0);
109 if (src[0].file == GRF)
110 assert(src[0].reg_offset >= 0);
111 if (src[1].file == GRF)
112 assert(src[1].reg_offset >= 0);
115 fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
116 fs_reg src0, fs_reg src1, fs_reg src2)
119 this->opcode = opcode;
126 assert(dst.reg_offset >= 0);
127 if (src[0].file == GRF)
128 assert(src[0].reg_offset >= 0);
129 if (src[1].file == GRF)
130 assert(src[1].reg_offset >= 0);
131 if (src[2].file == GRF)
132 assert(src[2].reg_offset >= 0);
137 fs_visitor::op(fs_reg dst, fs_reg src0) \
139 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
144 fs_visitor::op(fs_reg dst, fs_reg src0, fs_reg src1) \
146 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
165 /** Gen4 predicated IF. */
167 fs_visitor::IF(uint32_t predicate)
169 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
170 inst->predicate = predicate;
174 /** Gen6+ IF with embedded comparison. */
176 fs_visitor::IF(fs_reg src0, fs_reg src1, uint32_t condition)
178 assert(intel->gen >= 6);
179 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
180 reg_null_d, src0, src1);
181 inst->conditional_mod = condition;
186 * CMP: Sets the low bit of the destination channels with the result
187 * of the comparison, while the upper bits are undefined, and updates
188 * the flag register with the packed 16 bits of the result.
191 fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition)
195 /* Take the instruction:
197 * CMP null<d> src0<f> src1<f>
199 * Original gen4 does type conversion to the destination type before
200 * comparison, producing garbage results for floating point comparisons.
201 * gen5 does the comparison on the execution type (resolved source types),
202 * so dst type doesn't matter. gen6 does comparison and then uses the
203 * result as if it was the dst type with no conversion, which happens to
204 * mostly work out for float-interpreted-as-int since our comparisons are
207 if (intel->gen == 4) {
208 dst.type = src0.type;
209 if (dst.file == FIXED_HW_REG)
210 dst.fixed_hw_reg.type = dst.type;
213 resolve_ud_negate(&src0);
214 resolve_ud_negate(&src1);
216 inst = new(mem_ctx) fs_inst(BRW_OPCODE_CMP, dst, src0, src1);
217 inst->conditional_mod = condition;
223 fs_inst::equals(fs_inst *inst)
225 return (opcode == inst->opcode &&
226 dst.equals(inst->dst) &&
227 src[0].equals(inst->src[0]) &&
228 src[1].equals(inst->src[1]) &&
229 src[2].equals(inst->src[2]) &&
230 saturate == inst->saturate &&
231 predicate == inst->predicate &&
232 conditional_mod == inst->conditional_mod &&
233 mlen == inst->mlen &&
234 base_mrf == inst->base_mrf &&
235 sampler == inst->sampler &&
236 target == inst->target &&
238 header_present == inst->header_present &&
239 shadow_compare == inst->shadow_compare &&
240 offset == inst->offset);
244 fs_inst::regs_written()
249 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
250 * but we don't currently use them...nor do we have an opcode for them.
257 fs_inst::overwrites_reg(const fs_reg ®)
259 return (reg.file == dst.file &&
260 reg.reg == dst.reg &&
261 reg.reg_offset >= dst.reg_offset &&
262 reg.reg_offset < dst.reg_offset + regs_written());
268 return (opcode == SHADER_OPCODE_TEX ||
269 opcode == FS_OPCODE_TXB ||
270 opcode == SHADER_OPCODE_TXD ||
271 opcode == SHADER_OPCODE_TXF ||
272 opcode == SHADER_OPCODE_TXL ||
273 opcode == SHADER_OPCODE_TXS);
279 return (opcode == SHADER_OPCODE_RCP ||
280 opcode == SHADER_OPCODE_RSQ ||
281 opcode == SHADER_OPCODE_SQRT ||
282 opcode == SHADER_OPCODE_EXP2 ||
283 opcode == SHADER_OPCODE_LOG2 ||
284 opcode == SHADER_OPCODE_SIN ||
285 opcode == SHADER_OPCODE_COS ||
286 opcode == SHADER_OPCODE_INT_QUOTIENT ||
287 opcode == SHADER_OPCODE_INT_REMAINDER ||
288 opcode == SHADER_OPCODE_POW);
294 memset(this, 0, sizeof(*this));
298 /** Generic unset register constructor. */
302 this->file = BAD_FILE;
305 /** Immediate value constructor. */
306 fs_reg::fs_reg(float f)
310 this->type = BRW_REGISTER_TYPE_F;
314 /** Immediate value constructor. */
315 fs_reg::fs_reg(int32_t i)
319 this->type = BRW_REGISTER_TYPE_D;
323 /** Immediate value constructor. */
324 fs_reg::fs_reg(uint32_t u)
328 this->type = BRW_REGISTER_TYPE_UD;
332 /** Fixed brw_reg Immediate value constructor. */
333 fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
336 this->file = FIXED_HW_REG;
337 this->fixed_hw_reg = fixed_hw_reg;
338 this->type = fixed_hw_reg.type;
342 fs_reg::equals(const fs_reg &r) const
344 return (file == r.file &&
346 reg_offset == r.reg_offset &&
348 negate == r.negate &&
350 memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
351 sizeof(fixed_hw_reg)) == 0 &&
357 fs_visitor::type_size(const struct glsl_type *type)
359 unsigned int size, i;
361 switch (type->base_type) {
364 case GLSL_TYPE_FLOAT:
366 return type->components();
367 case GLSL_TYPE_ARRAY:
368 return type_size(type->fields.array) * type->length;
369 case GLSL_TYPE_STRUCT:
371 for (i = 0; i < type->length; i++) {
372 size += type_size(type->fields.structure[i].type);
375 case GLSL_TYPE_SAMPLER:
376 /* Samplers take up no register space, since they're baked in at
381 assert(!"not reached");
387 fs_visitor::fail(const char *format, ...)
397 va_start(va, format);
398 msg = ralloc_vasprintf(mem_ctx, format, va);
400 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg);
402 this->fail_msg = msg;
404 if (INTEL_DEBUG & DEBUG_WM) {
405 fprintf(stderr, "%s", msg);
410 fs_visitor::emit(enum opcode opcode)
412 return emit(fs_inst(opcode));
416 fs_visitor::emit(enum opcode opcode, fs_reg dst)
418 return emit(fs_inst(opcode, dst));
422 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0)
424 return emit(fs_inst(opcode, dst, src0));
428 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
430 return emit(fs_inst(opcode, dst, src0, src1));
434 fs_visitor::emit(enum opcode opcode, fs_reg dst,
435 fs_reg src0, fs_reg src1, fs_reg src2)
437 return emit(fs_inst(opcode, dst, src0, src1, src2));
441 fs_visitor::push_force_uncompressed()
443 force_uncompressed_stack++;
447 fs_visitor::pop_force_uncompressed()
449 force_uncompressed_stack--;
450 assert(force_uncompressed_stack >= 0);
454 fs_visitor::push_force_sechalf()
456 force_sechalf_stack++;
460 fs_visitor::pop_force_sechalf()
462 force_sechalf_stack--;
463 assert(force_sechalf_stack >= 0);
467 * Returns how many MRFs an FS opcode will write over.
469 * Note that this is not the 0 or 1 implied writes in an actual gen
470 * instruction -- the FS opcodes often generate MOVs in addition.
473 fs_visitor::implied_mrf_writes(fs_inst *inst)
478 switch (inst->opcode) {
479 case SHADER_OPCODE_RCP:
480 case SHADER_OPCODE_RSQ:
481 case SHADER_OPCODE_SQRT:
482 case SHADER_OPCODE_EXP2:
483 case SHADER_OPCODE_LOG2:
484 case SHADER_OPCODE_SIN:
485 case SHADER_OPCODE_COS:
486 return 1 * dispatch_width / 8;
487 case SHADER_OPCODE_POW:
488 case SHADER_OPCODE_INT_QUOTIENT:
489 case SHADER_OPCODE_INT_REMAINDER:
490 return 2 * dispatch_width / 8;
491 case SHADER_OPCODE_TEX:
493 case SHADER_OPCODE_TXD:
494 case SHADER_OPCODE_TXF:
495 case SHADER_OPCODE_TXL:
496 case SHADER_OPCODE_TXS:
498 case FS_OPCODE_FB_WRITE:
500 case FS_OPCODE_PULL_CONSTANT_LOAD:
501 case FS_OPCODE_UNSPILL:
503 case FS_OPCODE_SPILL:
506 assert(!"not reached");
512 fs_visitor::virtual_grf_alloc(int size)
514 if (virtual_grf_array_size <= virtual_grf_count) {
515 if (virtual_grf_array_size == 0)
516 virtual_grf_array_size = 16;
518 virtual_grf_array_size *= 2;
519 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
520 virtual_grf_array_size);
522 virtual_grf_sizes[virtual_grf_count] = size;
523 return virtual_grf_count++;
526 /** Fixed HW reg constructor. */
527 fs_reg::fs_reg(enum register_file file, int reg)
532 this->type = BRW_REGISTER_TYPE_F;
535 /** Fixed HW reg constructor. */
536 fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
544 /** Automatic reg constructor. */
545 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
550 this->reg = v->virtual_grf_alloc(v->type_size(type));
551 this->reg_offset = 0;
552 this->type = brw_type_for_base_type(type);
556 fs_visitor::variable_storage(ir_variable *var)
558 return (fs_reg *)hash_table_find(this->variable_ht, var);
562 import_uniforms_callback(const void *key,
566 struct hash_table *dst_ht = (struct hash_table *)closure;
567 const fs_reg *reg = (const fs_reg *)data;
569 if (reg->file != UNIFORM)
572 hash_table_insert(dst_ht, data, key);
575 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
576 * This brings in those uniform definitions
579 fs_visitor::import_uniforms(fs_visitor *v)
581 hash_table_call_foreach(v->variable_ht,
582 import_uniforms_callback,
584 this->params_remap = v->params_remap;
587 /* Our support for uniforms is piggy-backed on the struct
588 * gl_fragment_program, because that's where the values actually
589 * get stored, rather than in some global gl_shader_program uniform
593 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
595 unsigned int offset = 0;
597 if (type->is_matrix()) {
598 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
599 type->vector_elements,
602 for (unsigned int i = 0; i < type->matrix_columns; i++) {
603 offset += setup_uniform_values(loc + offset, column);
609 switch (type->base_type) {
610 case GLSL_TYPE_FLOAT:
614 for (unsigned int i = 0; i < type->vector_elements; i++) {
615 unsigned int param = c->prog_data.nr_params++;
617 this->param_index[param] = loc;
618 this->param_offset[param] = i;
622 case GLSL_TYPE_STRUCT:
623 for (unsigned int i = 0; i < type->length; i++) {
624 offset += setup_uniform_values(loc + offset,
625 type->fields.structure[i].type);
629 case GLSL_TYPE_ARRAY:
630 for (unsigned int i = 0; i < type->length; i++) {
631 offset += setup_uniform_values(loc + offset, type->fields.array);
635 case GLSL_TYPE_SAMPLER:
636 /* The sampler takes up a slot, but we don't use any values from it. */
640 assert(!"not reached");
646 /* Our support for builtin uniforms is even scarier than non-builtin.
647 * It sits on top of the PROG_STATE_VAR parameters that are
648 * automatically updated from GL context state.
651 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
653 const ir_state_slot *const slots = ir->state_slots;
654 assert(ir->state_slots != NULL);
656 for (unsigned int i = 0; i < ir->num_state_slots; i++) {
657 /* This state reference has already been setup by ir_to_mesa, but we'll
658 * get the same index back here.
660 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
661 (gl_state_index *)slots[i].tokens);
663 /* Add each of the unique swizzles of the element as a parameter.
664 * This'll end up matching the expected layout of the
665 * array/matrix/structure we're trying to fill in.
668 for (unsigned int j = 0; j < 4; j++) {
669 int swiz = GET_SWZ(slots[i].swizzle, j);
670 if (swiz == last_swiz)
674 this->param_index[c->prog_data.nr_params] = index;
675 this->param_offset[c->prog_data.nr_params] = swiz;
676 c->prog_data.nr_params++;
682 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
684 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
686 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
689 if (ir->pixel_center_integer) {
690 emit(MOV(wpos, this->pixel_x));
692 emit(ADD(wpos, this->pixel_x, fs_reg(0.5f)));
697 if (!flip && ir->pixel_center_integer) {
698 emit(MOV(wpos, this->pixel_y));
700 fs_reg pixel_y = this->pixel_y;
701 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
704 pixel_y.negate = true;
705 offset += c->key.drawable_height - 1.0;
708 emit(ADD(wpos, pixel_y, fs_reg(offset)));
713 if (intel->gen >= 6) {
714 emit(MOV(wpos, fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
716 emit(FS_OPCODE_LINTERP, wpos,
717 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
718 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
719 interp_reg(FRAG_ATTRIB_WPOS, 2));
723 /* gl_FragCoord.w: Already set up in emit_interpolation */
724 emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
730 fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp,
731 glsl_interp_qualifier interpolation_mode,
734 brw_wm_barycentric_interp_mode barycoord_mode;
736 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
737 barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
739 barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
741 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
742 barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
744 barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
746 return emit(FS_OPCODE_LINTERP, attr,
747 this->delta_x[barycoord_mode],
748 this->delta_y[barycoord_mode], interp);
752 fs_visitor::emit_general_interpolation(ir_variable *ir)
754 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
755 reg->type = brw_type_for_base_type(ir->type->get_scalar_type());
758 unsigned int array_elements;
759 const glsl_type *type;
761 if (ir->type->is_array()) {
762 array_elements = ir->type->length;
763 if (array_elements == 0) {
764 fail("dereferenced array '%s' has length 0\n", ir->name);
766 type = ir->type->fields.array;
772 glsl_interp_qualifier interpolation_mode =
773 ir->determine_interpolation_mode(c->key.flat_shade);
775 int location = ir->location;
776 for (unsigned int i = 0; i < array_elements; i++) {
777 for (unsigned int j = 0; j < type->matrix_columns; j++) {
778 if (urb_setup[location] == -1) {
779 /* If there's no incoming setup data for this slot, don't
780 * emit interpolation for it.
782 attr.reg_offset += type->vector_elements;
787 if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
788 /* Constant interpolation (flat shading) case. The SF has
789 * handed us defined values in only the constant offset
790 * field of the setup reg.
792 for (unsigned int k = 0; k < type->vector_elements; k++) {
793 struct brw_reg interp = interp_reg(location, k);
794 interp = suboffset(interp, 3);
795 interp.type = reg->type;
796 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
800 /* Smooth/noperspective interpolation case. */
801 for (unsigned int k = 0; k < type->vector_elements; k++) {
802 /* FINISHME: At some point we probably want to push
803 * this farther by giving similar treatment to the
804 * other potentially constant components of the
805 * attribute, as well as making brw_vs_constval.c
806 * handle varyings other than gl_TexCoord.
808 if (location >= FRAG_ATTRIB_TEX0 &&
809 location <= FRAG_ATTRIB_TEX7 &&
810 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) {
811 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
813 struct brw_reg interp = interp_reg(location, k);
814 emit_linterp(attr, fs_reg(interp), interpolation_mode,
816 if (brw->needs_unlit_centroid_workaround && ir->centroid) {
817 /* Get the pixel/sample mask into f0 so that we know
818 * which pixels are lit. Then, for each channel that is
819 * unlit, replace the centroid data with non-centroid
822 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
823 fs_inst *inst = emit_linterp(attr, fs_reg(interp),
824 interpolation_mode, false);
825 inst->predicate = BRW_PREDICATE_NORMAL;
826 inst->predicate_inverse = true;
828 if (intel->gen < 6) {
829 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
844 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
846 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
848 /* The frontfacing comes in as a bit in the thread payload. */
849 if (intel->gen >= 6) {
850 emit(BRW_OPCODE_ASR, *reg,
851 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
853 emit(BRW_OPCODE_NOT, *reg, *reg);
854 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
856 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
857 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
860 emit(CMP(*reg, fs_reg(r1_6ud), fs_reg(1u << 31), BRW_CONDITIONAL_L));
861 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
868 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
871 case SHADER_OPCODE_RCP:
872 case SHADER_OPCODE_RSQ:
873 case SHADER_OPCODE_SQRT:
874 case SHADER_OPCODE_EXP2:
875 case SHADER_OPCODE_LOG2:
876 case SHADER_OPCODE_SIN:
877 case SHADER_OPCODE_COS:
880 assert(!"not reached: bad math opcode");
884 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
885 * might be able to do better by doing execsize = 1 math and then
886 * expanding that result out, but we would need to be careful with
889 * Gen 6 hardware ignores source modifiers (negate and abs) on math
890 * instructions, so we also move to a temp to set those up.
892 if (intel->gen == 6 && (src.file == UNIFORM ||
895 fs_reg expanded = fs_reg(this, glsl_type::float_type);
896 emit(BRW_OPCODE_MOV, expanded, src);
900 fs_inst *inst = emit(opcode, dst, src);
902 if (intel->gen < 6) {
904 inst->mlen = dispatch_width / 8;
911 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
917 case SHADER_OPCODE_POW:
918 case SHADER_OPCODE_INT_QUOTIENT:
919 case SHADER_OPCODE_INT_REMAINDER:
922 assert(!"not reached: unsupported binary math opcode.");
926 if (intel->gen >= 7) {
927 inst = emit(opcode, dst, src0, src1);
928 } else if (intel->gen == 6) {
929 /* Can't do hstride == 0 args to gen6 math, so expand it out.
931 * The hardware ignores source modifiers (negate and abs) on math
932 * instructions, so we also move to a temp to set those up.
934 if (src0.file == UNIFORM || src0.abs || src0.negate) {
935 fs_reg expanded = fs_reg(this, glsl_type::float_type);
936 expanded.type = src0.type;
937 emit(BRW_OPCODE_MOV, expanded, src0);
941 if (src1.file == UNIFORM || src1.abs || src1.negate) {
942 fs_reg expanded = fs_reg(this, glsl_type::float_type);
943 expanded.type = src1.type;
944 emit(BRW_OPCODE_MOV, expanded, src1);
948 inst = emit(opcode, dst, src0, src1);
950 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
953 * "Operand0[7]. For the INT DIV functions, this operand is the
956 * "Operand1[7]. For the INT DIV functions, this operand is the
959 bool is_int_div = opcode != SHADER_OPCODE_POW;
960 fs_reg &op0 = is_int_div ? src1 : src0;
961 fs_reg &op1 = is_int_div ? src0 : src1;
963 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
964 inst = emit(opcode, dst, op0, reg_null_f);
966 inst->base_mrf = base_mrf;
967 inst->mlen = 2 * dispatch_width / 8;
973 * To be called after the last _mesa_add_state_reference() call, to
974 * set up prog_data.param[] for assign_curb_setup() and
975 * setup_pull_constants().
978 fs_visitor::setup_paramvalues_refs()
980 if (dispatch_width != 8)
983 /* Set up the pointers to ParamValues now that that array is finalized. */
984 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
985 c->prog_data.param[i] =
986 (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] +
987 this->param_offset[i];
992 fs_visitor::assign_curb_setup()
994 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
995 if (dispatch_width == 8) {
996 c->prog_data.first_curbe_grf = c->nr_payload_regs;
998 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
1001 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1002 foreach_list(node, &this->instructions) {
1003 fs_inst *inst = (fs_inst *)node;
1005 for (unsigned int i = 0; i < 3; i++) {
1006 if (inst->src[i].file == UNIFORM) {
1007 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1008 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
1012 inst->src[i].file = FIXED_HW_REG;
1013 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
1020 fs_visitor::calculate_urb_setup()
1022 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1027 /* Figure out where each of the incoming setup attributes lands. */
1028 if (intel->gen >= 6) {
1029 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1030 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
1031 urb_setup[i] = urb_next++;
1035 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1036 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
1037 /* Point size is packed into the header, not as a general attribute */
1038 if (i == VERT_RESULT_PSIZ)
1041 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
1042 int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
1044 /* The back color slot is skipped when the front color is
1045 * also written to. In addition, some slots can be
1046 * written in the vertex shader and not read in the
1047 * fragment shader. So the register number must always be
1048 * incremented, mapped or not.
1051 urb_setup[fp_index] = urb_next;
1057 * It's a FS only attribute, and we did interpolation for this attribute
1058 * in SF thread. So, count it here, too.
1060 * See compile_sf_prog() for more info.
1062 if (fp->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
1063 urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
1066 /* Each attribute is 4 setup channels, each of which is half a reg. */
1067 c->prog_data.urb_read_length = urb_next * 2;
1071 fs_visitor::assign_urb_setup()
1073 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
1075 /* Offset all the urb_setup[] index by the actual position of the
1076 * setup regs, now that the location of the constants has been chosen.
1078 foreach_list(node, &this->instructions) {
1079 fs_inst *inst = (fs_inst *)node;
1081 if (inst->opcode == FS_OPCODE_LINTERP) {
1082 assert(inst->src[2].file == FIXED_HW_REG);
1083 inst->src[2].fixed_hw_reg.nr += urb_start;
1086 if (inst->opcode == FS_OPCODE_CINTERP) {
1087 assert(inst->src[0].file == FIXED_HW_REG);
1088 inst->src[0].fixed_hw_reg.nr += urb_start;
1092 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1096 * Split large virtual GRFs into separate components if we can.
1098 * This is mostly duplicated with what brw_fs_vector_splitting does,
1099 * but that's really conservative because it's afraid of doing
1100 * splitting that doesn't result in real progress after the rest of
1101 * the optimization phases, which would cause infinite looping in
1102 * optimization. We can do it once here, safely. This also has the
1103 * opportunity to split interpolated values, or maybe even uniforms,
1104 * which we don't have at the IR level.
1106 * We want to split, because virtual GRFs are what we register
1107 * allocate and spill (due to contiguousness requirements for some
1108 * instructions), and they're what we naturally generate in the
1109 * codegen process, but most virtual GRFs don't actually need to be
1110 * contiguous sets of GRFs. If we split, we'll end up with reduced
1111 * live intervals and better dead code elimination and coalescing.
1114 fs_visitor::split_virtual_grfs()
1116 int num_vars = this->virtual_grf_count;
1117 bool split_grf[num_vars];
1118 int new_virtual_grf[num_vars];
1120 /* Try to split anything > 0 sized. */
1121 for (int i = 0; i < num_vars; i++) {
1122 if (this->virtual_grf_sizes[i] != 1)
1123 split_grf[i] = true;
1125 split_grf[i] = false;
1129 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF) {
1130 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1131 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1132 * Gen6, that was the only supported interpolation mode, and since Gen6,
1133 * delta_x and delta_y are in fixed hardware registers.
1135 split_grf[this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg] =
1139 foreach_list(node, &this->instructions) {
1140 fs_inst *inst = (fs_inst *)node;
1142 /* If there's a SEND message that requires contiguous destination
1143 * registers, no splitting is allowed.
1145 if (inst->regs_written() > 1) {
1146 split_grf[inst->dst.reg] = false;
1150 /* Allocate new space for split regs. Note that the virtual
1151 * numbers will be contiguous.
1153 for (int i = 0; i < num_vars; i++) {
1155 new_virtual_grf[i] = virtual_grf_alloc(1);
1156 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
1157 int reg = virtual_grf_alloc(1);
1158 assert(reg == new_virtual_grf[i] + j - 1);
1161 this->virtual_grf_sizes[i] = 1;
1165 foreach_list(node, &this->instructions) {
1166 fs_inst *inst = (fs_inst *)node;
1168 if (inst->dst.file == GRF &&
1169 split_grf[inst->dst.reg] &&
1170 inst->dst.reg_offset != 0) {
1171 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
1172 inst->dst.reg_offset - 1);
1173 inst->dst.reg_offset = 0;
1175 for (int i = 0; i < 3; i++) {
1176 if (inst->src[i].file == GRF &&
1177 split_grf[inst->src[i].reg] &&
1178 inst->src[i].reg_offset != 0) {
1179 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
1180 inst->src[i].reg_offset - 1);
1181 inst->src[i].reg_offset = 0;
1185 this->live_intervals_valid = false;
1189 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1191 * During code generation, we create tons of temporary variables, many of
1192 * which get immediately killed and are never used again. Yet, in later
1193 * optimization and analysis passes, such as compute_live_intervals, we need
1194 * to loop over all the virtual GRFs. Compacting them can save a lot of
1198 fs_visitor::compact_virtual_grfs()
1200 /* Mark which virtual GRFs are used, and count how many. */
1201 int remap_table[this->virtual_grf_count];
1202 memset(remap_table, -1, sizeof(remap_table));
1204 foreach_list(node, &this->instructions) {
1205 const fs_inst *inst = (const fs_inst *) node;
1207 if (inst->dst.file == GRF)
1208 remap_table[inst->dst.reg] = 0;
1210 for (int i = 0; i < 3; i++) {
1211 if (inst->src[i].file == GRF)
1212 remap_table[inst->src[i].reg] = 0;
1216 /* In addition to registers used in instructions, fs_visitor keeps
1217 * direct references to certain special values which must be patched:
1219 fs_reg *special[] = {
1220 &frag_depth, &pixel_x, &pixel_y, &pixel_w, &wpos_w, &dual_src_output,
1221 &outputs[0], &outputs[1], &outputs[2], &outputs[3],
1222 &outputs[4], &outputs[5], &outputs[6], &outputs[7],
1223 &delta_x[0], &delta_x[1], &delta_x[2],
1224 &delta_x[3], &delta_x[4], &delta_x[5],
1225 &delta_y[0], &delta_y[1], &delta_y[2],
1226 &delta_y[3], &delta_y[4], &delta_y[5],
1228 STATIC_ASSERT(BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT == 6);
1229 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS == 8);
1231 /* Treat all special values as used, to be conservative */
1232 for (unsigned i = 0; i < ARRAY_SIZE(special); i++) {
1233 if (special[i]->file == GRF)
1234 remap_table[special[i]->reg] = 0;
1237 /* Compact the GRF arrays. */
1239 for (int i = 0; i < this->virtual_grf_count; i++) {
1240 if (remap_table[i] != -1) {
1241 remap_table[i] = new_index;
1242 virtual_grf_sizes[new_index] = virtual_grf_sizes[i];
1243 if (live_intervals_valid) {
1244 virtual_grf_use[new_index] = virtual_grf_use[i];
1245 virtual_grf_def[new_index] = virtual_grf_def[i];
1251 this->virtual_grf_count = new_index;
1253 /* Patch all the instructions to use the newly renumbered registers */
1254 foreach_list(node, &this->instructions) {
1255 fs_inst *inst = (fs_inst *) node;
1257 if (inst->dst.file == GRF)
1258 inst->dst.reg = remap_table[inst->dst.reg];
1260 for (int i = 0; i < 3; i++) {
1261 if (inst->src[i].file == GRF)
1262 inst->src[i].reg = remap_table[inst->src[i].reg];
1266 /* Patch all the references to special values */
1267 for (unsigned i = 0; i < ARRAY_SIZE(special); i++) {
1268 if (special[i]->file == GRF && remap_table[special[i]->reg] != -1)
1269 special[i]->reg = remap_table[special[i]->reg];
1274 fs_visitor::remove_dead_constants()
1276 if (dispatch_width == 8) {
1277 this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
1279 for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
1280 this->params_remap[i] = -1;
1282 /* Find which params are still in use. */
1283 foreach_list(node, &this->instructions) {
1284 fs_inst *inst = (fs_inst *)node;
1286 for (int i = 0; i < 3; i++) {
1287 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1289 if (inst->src[i].file != UNIFORM)
1292 assert(constant_nr < (int)c->prog_data.nr_params);
1294 /* For now, set this to non-negative. We'll give it the
1295 * actual new number in a moment, in order to keep the
1296 * register numbers nicely ordered.
1298 this->params_remap[constant_nr] = 0;
1302 /* Figure out what the new numbers for the params will be. At some
1303 * point when we're doing uniform array access, we're going to want
1304 * to keep the distinction between .reg and .reg_offset, but for
1305 * now we don't care.
1307 unsigned int new_nr_params = 0;
1308 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1309 if (this->params_remap[i] != -1) {
1310 this->params_remap[i] = new_nr_params++;
1314 /* Update the list of params to be uploaded to match our new numbering. */
1315 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1316 int remapped = this->params_remap[i];
1321 /* We've already done setup_paramvalues_refs() so no need to worry
1322 * about param_index and param_offset.
1324 c->prog_data.param[remapped] = c->prog_data.param[i];
1327 c->prog_data.nr_params = new_nr_params;
1329 /* This should have been generated in the 8-wide pass already. */
1330 assert(this->params_remap);
1333 /* Now do the renumbering of the shader to remove unused params. */
1334 foreach_list(node, &this->instructions) {
1335 fs_inst *inst = (fs_inst *)node;
1337 for (int i = 0; i < 3; i++) {
1338 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1340 if (inst->src[i].file != UNIFORM)
1343 assert(this->params_remap[constant_nr] != -1);
1344 inst->src[i].reg = this->params_remap[constant_nr];
1345 inst->src[i].reg_offset = 0;
1353 * Choose accesses from the UNIFORM file to demote to using the pull
1356 * We allow a fragment shader to have more than the specified minimum
1357 * maximum number of fragment shader uniform components (64). If
1358 * there are too many of these, they'd fill up all of register space.
1359 * So, this will push some of them out to the pull constant buffer and
1360 * update the program to load them.
1363 fs_visitor::setup_pull_constants()
1365 /* Only allow 16 registers (128 uniform components) as push constants. */
1366 unsigned int max_uniform_components = 16 * 8;
1367 if (c->prog_data.nr_params <= max_uniform_components)
1370 if (dispatch_width == 16) {
1371 fail("Pull constants not supported in 16-wide\n");
1375 /* Just demote the end of the list. We could probably do better
1376 * here, demoting things that are rarely used in the program first.
1378 int pull_uniform_base = max_uniform_components;
1379 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base;
1381 foreach_list(node, &this->instructions) {
1382 fs_inst *inst = (fs_inst *)node;
1384 for (int i = 0; i < 3; i++) {
1385 if (inst->src[i].file != UNIFORM)
1388 int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset;
1389 if (uniform_nr < pull_uniform_base)
1392 fs_reg dst = fs_reg(this, glsl_type::float_type);
1393 fs_reg index = fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER);
1394 fs_reg offset = fs_reg((unsigned)(((uniform_nr -
1395 pull_uniform_base) * 4) & ~15));
1396 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD,
1397 dst, index, offset);
1398 pull->ir = inst->ir;
1399 pull->annotation = inst->annotation;
1400 pull->base_mrf = 14;
1403 inst->insert_before(pull);
1405 inst->src[i].file = GRF;
1406 inst->src[i].reg = dst.reg;
1407 inst->src[i].reg_offset = 0;
1408 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3;
1412 for (int i = 0; i < pull_uniform_count; i++) {
1413 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i];
1415 c->prog_data.nr_params -= pull_uniform_count;
1416 c->prog_data.nr_pull_params = pull_uniform_count;
1420 fs_visitor::opt_algebraic()
1422 bool progress = false;
1424 foreach_list(node, &this->instructions) {
1425 fs_inst *inst = (fs_inst *)node;
1427 switch (inst->opcode) {
1428 case BRW_OPCODE_MUL:
1429 if (inst->src[1].file != IMM)
1433 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1434 inst->src[1].imm.f == 1.0) {
1435 inst->opcode = BRW_OPCODE_MOV;
1436 inst->src[1] = reg_undef;
1442 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1443 inst->src[1].imm.f == 0.0) {
1444 inst->opcode = BRW_OPCODE_MOV;
1445 inst->src[0] = fs_reg(0.0f);
1446 inst->src[1] = reg_undef;
1452 case BRW_OPCODE_ADD:
1453 if (inst->src[1].file != IMM)
1457 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1458 inst->src[1].imm.f == 0.0) {
1459 inst->opcode = BRW_OPCODE_MOV;
1460 inst->src[1] = reg_undef;
1474 * Must be called after calculate_live_intervales() to remove unused
1475 * writes to registers -- register allocation will fail otherwise
1476 * because something deffed but not used won't be considered to
1477 * interfere with other regs.
1480 fs_visitor::dead_code_eliminate()
1482 bool progress = false;
1485 calculate_live_intervals();
1487 foreach_list_safe(node, &this->instructions) {
1488 fs_inst *inst = (fs_inst *)node;
1490 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
1499 live_intervals_valid = false;
1505 * Implements a second type of register coalescing: This one checks if
1506 * the two regs involved in a raw move don't interfere, in which case
1507 * they can both by stored in the same place and the MOV removed.
1510 fs_visitor::register_coalesce_2()
1512 bool progress = false;
1514 calculate_live_intervals();
1516 foreach_list_safe(node, &this->instructions) {
1517 fs_inst *inst = (fs_inst *)node;
1519 if (inst->opcode != BRW_OPCODE_MOV ||
1522 inst->src[0].file != GRF ||
1523 inst->src[0].negate ||
1525 inst->src[0].smear != -1 ||
1526 inst->dst.file != GRF ||
1527 inst->dst.type != inst->src[0].type ||
1528 virtual_grf_sizes[inst->src[0].reg] != 1 ||
1529 virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) {
1533 int reg_from = inst->src[0].reg;
1534 assert(inst->src[0].reg_offset == 0);
1535 int reg_to = inst->dst.reg;
1536 int reg_to_offset = inst->dst.reg_offset;
1538 foreach_list_safe(node, &this->instructions) {
1539 fs_inst *scan_inst = (fs_inst *)node;
1541 if (scan_inst->dst.file == GRF &&
1542 scan_inst->dst.reg == reg_from) {
1543 scan_inst->dst.reg = reg_to;
1544 scan_inst->dst.reg_offset = reg_to_offset;
1546 for (int i = 0; i < 3; i++) {
1547 if (scan_inst->src[i].file == GRF &&
1548 scan_inst->src[i].reg == reg_from) {
1549 scan_inst->src[i].reg = reg_to;
1550 scan_inst->src[i].reg_offset = reg_to_offset;
1556 live_intervals_valid = false;
1565 fs_visitor::register_coalesce()
1567 bool progress = false;
1571 foreach_list_safe(node, &this->instructions) {
1572 fs_inst *inst = (fs_inst *)node;
1574 /* Make sure that we dominate the instructions we're going to
1575 * scan for interfering with our coalescing, or we won't have
1576 * scanned enough to see if anything interferes with our
1577 * coalescing. We don't dominate the following instructions if
1578 * we're in a loop or an if block.
1580 switch (inst->opcode) {
1584 case BRW_OPCODE_WHILE:
1590 case BRW_OPCODE_ENDIF:
1596 if (loop_depth || if_depth)
1599 if (inst->opcode != BRW_OPCODE_MOV ||
1602 inst->dst.file != GRF || (inst->src[0].file != GRF &&
1603 inst->src[0].file != UNIFORM)||
1604 inst->dst.type != inst->src[0].type)
1607 bool has_source_modifiers = inst->src[0].abs || inst->src[0].negate;
1609 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1610 * them: check for no writes to either one until the exit of the
1613 bool interfered = false;
1615 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1616 !scan_inst->is_tail_sentinel();
1617 scan_inst = (fs_inst *)scan_inst->next) {
1618 if (scan_inst->dst.file == GRF) {
1619 if (scan_inst->overwrites_reg(inst->dst) ||
1620 scan_inst->overwrites_reg(inst->src[0])) {
1626 /* The gen6 MATH instruction can't handle source modifiers or
1627 * unusual register regions, so avoid coalescing those for
1628 * now. We should do something more specific.
1630 if (intel->gen >= 6 &&
1631 scan_inst->is_math() &&
1632 (has_source_modifiers || inst->src[0].file == UNIFORM)) {
1637 /* The accumulator result appears to get used for the
1638 * conditional modifier generation. When negating a UD
1639 * value, there is a 33rd bit generated for the sign in the
1640 * accumulator value, so now you can't check, for example,
1641 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1643 if (scan_inst->conditional_mod &&
1644 inst->src[0].negate &&
1645 inst->src[0].type == BRW_REGISTER_TYPE_UD) {
1654 /* Rewrite the later usage to point at the source of the move to
1657 for (fs_inst *scan_inst = inst;
1658 !scan_inst->is_tail_sentinel();
1659 scan_inst = (fs_inst *)scan_inst->next) {
1660 for (int i = 0; i < 3; i++) {
1661 if (scan_inst->src[i].file == GRF &&
1662 scan_inst->src[i].reg == inst->dst.reg &&
1663 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
1664 fs_reg new_src = inst->src[0];
1665 if (scan_inst->src[i].abs) {
1669 new_src.negate ^= scan_inst->src[i].negate;
1670 scan_inst->src[i] = new_src;
1680 live_intervals_valid = false;
1687 fs_visitor::compute_to_mrf()
1689 bool progress = false;
1692 calculate_live_intervals();
1694 foreach_list_safe(node, &this->instructions) {
1695 fs_inst *inst = (fs_inst *)node;
1700 if (inst->opcode != BRW_OPCODE_MOV ||
1702 inst->dst.file != MRF || inst->src[0].file != GRF ||
1703 inst->dst.type != inst->src[0].type ||
1704 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
1707 /* Work out which hardware MRF registers are written by this
1710 int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4;
1712 if (inst->dst.reg & BRW_MRF_COMPR4) {
1713 mrf_high = mrf_low + 4;
1714 } else if (dispatch_width == 16 &&
1715 (!inst->force_uncompressed && !inst->force_sechalf)) {
1716 mrf_high = mrf_low + 1;
1721 /* Can't compute-to-MRF this GRF if someone else was going to
1724 if (this->virtual_grf_use[inst->src[0].reg] > ip)
1727 /* Found a move of a GRF to a MRF. Let's see if we can go
1728 * rewrite the thing that made this GRF to write into the MRF.
1731 for (scan_inst = (fs_inst *)inst->prev;
1732 scan_inst->prev != NULL;
1733 scan_inst = (fs_inst *)scan_inst->prev) {
1734 if (scan_inst->dst.file == GRF &&
1735 scan_inst->dst.reg == inst->src[0].reg) {
1736 /* Found the last thing to write our reg we want to turn
1737 * into a compute-to-MRF.
1740 /* SENDs can only write to GRFs, so no compute-to-MRF. */
1741 if (scan_inst->mlen) {
1745 /* If it's predicated, it (probably) didn't populate all
1746 * the channels. We might be able to rewrite everything
1747 * that writes that reg, but it would require smarter
1748 * tracking to delay the rewriting until complete success.
1750 if (scan_inst->predicate)
1753 /* If it's half of register setup and not the same half as
1754 * our MOV we're trying to remove, bail for now.
1756 if (scan_inst->force_uncompressed != inst->force_uncompressed ||
1757 scan_inst->force_sechalf != inst->force_sechalf) {
1761 /* SEND instructions can't have MRF as a destination. */
1762 if (scan_inst->mlen)
1765 if (intel->gen >= 6) {
1766 /* gen6 math instructions must have the destination be
1767 * GRF, so no compute-to-MRF for them.
1769 if (scan_inst->is_math()) {
1774 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
1775 /* Found the creator of our MRF's source value. */
1776 scan_inst->dst.file = MRF;
1777 scan_inst->dst.reg = inst->dst.reg;
1778 scan_inst->saturate |= inst->saturate;
1785 /* We don't handle flow control here. Most computation of
1786 * values that end up in MRFs are shortly before the MRF
1789 if (scan_inst->opcode == BRW_OPCODE_DO ||
1790 scan_inst->opcode == BRW_OPCODE_WHILE ||
1791 scan_inst->opcode == BRW_OPCODE_ELSE ||
1792 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1796 /* You can't read from an MRF, so if someone else reads our
1797 * MRF's source GRF that we wanted to rewrite, that stops us.
1799 bool interfered = false;
1800 for (int i = 0; i < 3; i++) {
1801 if (scan_inst->src[i].file == GRF &&
1802 scan_inst->src[i].reg == inst->src[0].reg &&
1803 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
1810 if (scan_inst->dst.file == MRF) {
1811 /* If somebody else writes our MRF here, we can't
1812 * compute-to-MRF before that.
1814 int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4;
1817 if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
1818 scan_mrf_high = scan_mrf_low + 4;
1819 } else if (dispatch_width == 16 &&
1820 (!scan_inst->force_uncompressed &&
1821 !scan_inst->force_sechalf)) {
1822 scan_mrf_high = scan_mrf_low + 1;
1824 scan_mrf_high = scan_mrf_low;
1827 if (mrf_low == scan_mrf_low ||
1828 mrf_low == scan_mrf_high ||
1829 mrf_high == scan_mrf_low ||
1830 mrf_high == scan_mrf_high) {
1835 if (scan_inst->mlen > 0) {
1836 /* Found a SEND instruction, which means that there are
1837 * live values in MRFs from base_mrf to base_mrf +
1838 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1841 if (mrf_low >= scan_inst->base_mrf &&
1842 mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
1845 if (mrf_high >= scan_inst->base_mrf &&
1846 mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
1854 live_intervals_valid = false;
1860 * Walks through basic blocks, looking for repeated MRF writes and
1861 * removing the later ones.
1864 fs_visitor::remove_duplicate_mrf_writes()
1866 fs_inst *last_mrf_move[16];
1867 bool progress = false;
1869 /* Need to update the MRF tracking for compressed instructions. */
1870 if (dispatch_width == 16)
1873 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1875 foreach_list_safe(node, &this->instructions) {
1876 fs_inst *inst = (fs_inst *)node;
1878 switch (inst->opcode) {
1880 case BRW_OPCODE_WHILE:
1882 case BRW_OPCODE_ELSE:
1883 case BRW_OPCODE_ENDIF:
1884 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1890 if (inst->opcode == BRW_OPCODE_MOV &&
1891 inst->dst.file == MRF) {
1892 fs_inst *prev_inst = last_mrf_move[inst->dst.reg];
1893 if (prev_inst && inst->equals(prev_inst)) {
1900 /* Clear out the last-write records for MRFs that were overwritten. */
1901 if (inst->dst.file == MRF) {
1902 last_mrf_move[inst->dst.reg] = NULL;
1905 if (inst->mlen > 0) {
1906 /* Found a SEND instruction, which will include two or fewer
1907 * implied MRF writes. We could do better here.
1909 for (int i = 0; i < implied_mrf_writes(inst); i++) {
1910 last_mrf_move[inst->base_mrf + i] = NULL;
1914 /* Clear out any MRF move records whose sources got overwritten. */
1915 if (inst->dst.file == GRF) {
1916 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
1917 if (last_mrf_move[i] &&
1918 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
1919 last_mrf_move[i] = NULL;
1924 if (inst->opcode == BRW_OPCODE_MOV &&
1925 inst->dst.file == MRF &&
1926 inst->src[0].file == GRF &&
1928 last_mrf_move[inst->dst.reg] = inst;
1933 live_intervals_valid = false;
1939 * Possibly returns an instruction that set up @param reg.
1941 * Sometimes we want to take the result of some expression/variable
1942 * dereference tree and rewrite the instruction generating the result
1943 * of the tree. When processing the tree, we know that the
1944 * instructions generated are all writing temporaries that are dead
1945 * outside of this tree. So, if we have some instructions that write
1946 * a temporary, we're free to point that temp write somewhere else.
1948 * Note that this doesn't guarantee that the instruction generated
1949 * only reg -- it might be the size=4 destination of a texture instruction.
1952 fs_visitor::get_instruction_generating_reg(fs_inst *start,
1958 end->force_uncompressed ||
1959 end->force_sechalf ||
1960 !reg.equals(end->dst)) {
1968 fs_visitor::setup_payload_gen6()
1970 struct intel_context *intel = &brw->intel;
1972 (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
1973 unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
1975 assert(intel->gen >= 6);
1977 /* R0-1: masks, pixel X/Y coordinates. */
1978 c->nr_payload_regs = 2;
1979 /* R2: only for 32-pixel dispatch.*/
1981 /* R3-26: barycentric interpolation coordinates. These appear in the
1982 * same order that they appear in the brw_wm_barycentric_interp_mode
1983 * enum. Each set of coordinates occupies 2 registers if dispatch width
1984 * == 8 and 4 registers if dispatch width == 16. Coordinates only
1985 * appear if they were enabled using the "Barycentric Interpolation
1986 * Mode" bits in WM_STATE.
1988 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
1989 if (barycentric_interp_modes & (1 << i)) {
1990 c->barycentric_coord_reg[i] = c->nr_payload_regs;
1991 c->nr_payload_regs += 2;
1992 if (dispatch_width == 16) {
1993 c->nr_payload_regs += 2;
1998 /* R27: interpolated depth if uses source depth */
2000 c->source_depth_reg = c->nr_payload_regs;
2001 c->nr_payload_regs++;
2002 if (dispatch_width == 16) {
2003 /* R28: interpolated depth if not 8-wide. */
2004 c->nr_payload_regs++;
2007 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
2009 c->source_w_reg = c->nr_payload_regs;
2010 c->nr_payload_regs++;
2011 if (dispatch_width == 16) {
2012 /* R30: interpolated W if not 8-wide. */
2013 c->nr_payload_regs++;
2016 /* R31: MSAA position offsets. */
2017 /* R32-: bary for 32-pixel. */
2018 /* R58-59: interp W for 32-pixel. */
2020 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2021 c->source_depth_to_render_target = true;
2028 uint32_t prog_offset_16 = 0;
2029 uint32_t orig_nr_params = c->prog_data.nr_params;
2031 if (intel->gen >= 6)
2032 setup_payload_gen6();
2034 setup_payload_gen4();
2036 if (dispatch_width == 16) {
2037 /* We have to do a compaction pass now, or the one at the end of
2038 * execution will squash down where our prog_offset start needs
2041 brw_compact_instructions(p);
2043 /* align to 64 byte boundary. */
2044 while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
2048 /* Save off the start of this 16-wide program in case we succeed. */
2049 prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction);
2051 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2057 calculate_urb_setup();
2059 emit_interpolation_setup_gen4();
2061 emit_interpolation_setup_gen6();
2063 /* Generate FS IR for main(). (the visitor only descends into
2064 * functions called "main").
2067 foreach_list(node, &*shader->ir) {
2068 ir_instruction *ir = (ir_instruction *)node;
2070 this->result = reg_undef;
2074 emit_fragment_program_code();
2081 split_virtual_grfs();
2083 setup_paramvalues_refs();
2084 setup_pull_constants();
2090 compact_virtual_grfs();
2092 progress = remove_duplicate_mrf_writes() || progress;
2094 progress = opt_algebraic() || progress;
2095 progress = opt_cse() || progress;
2096 progress = opt_copy_propagate() || progress;
2097 progress = dead_code_eliminate() || progress;
2098 progress = register_coalesce() || progress;
2099 progress = register_coalesce_2() || progress;
2100 progress = compute_to_mrf() || progress;
2103 remove_dead_constants();
2105 schedule_instructions();
2107 assign_curb_setup();
2111 /* Debug of register spilling: Go spill everything. */
2112 for (int i = 0; i < virtual_grf_count; i++) {
2118 assign_regs_trivial();
2120 while (!assign_regs()) {
2126 assert(force_uncompressed_stack == 0);
2127 assert(force_sechalf_stack == 0);
2134 if (dispatch_width == 8) {
2135 c->prog_data.reg_blocks = brw_register_blocks(grf_used);
2137 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
2138 c->prog_data.prog_offset_16 = prog_offset_16;
2140 /* Make sure we didn't try to sneak in an extra uniform */
2141 assert(orig_nr_params == c->prog_data.nr_params);
2142 (void) orig_nr_params;
2149 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
2150 struct gl_fragment_program *fp,
2151 struct gl_shader_program *prog)
2153 struct intel_context *intel = &brw->intel;
2154 bool start_busy = false;
2155 float start_time = 0;
2157 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
2158 start_busy = (intel->batch.last_bo &&
2159 drm_intel_bo_busy(intel->batch.last_bo));
2160 start_time = get_time();
2163 struct brw_shader *shader = NULL;
2165 shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2167 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
2169 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2170 _mesa_print_ir(shader->ir, NULL);
2173 printf("ARB_fragment_program %d ir for native fragment shader\n",
2175 _mesa_print_program(&fp->Base);
2179 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2181 fs_visitor v(brw, c, prog, fp, 8);
2183 prog->LinkStatus = false;
2184 ralloc_strcat(&prog->InfoLog, v.fail_msg);
2186 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n",
2192 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
2193 fs_visitor v2(brw, c, prog, fp, 16);
2194 v2.import_uniforms(&v);
2196 perf_debug("16-wide shader failed to compile, falling back to "
2197 "8-wide at a 10-20%% performance cost: %s", v2.fail_msg);
2201 c->prog_data.dispatch_width = 8;
2203 if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
2204 if (shader->compiled_once)
2205 brw_wm_debug_recompile(brw, prog, &c->key);
2206 shader->compiled_once = true;
2208 if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
2209 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
2210 (get_time() - start_time) * 1000);
2218 brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
2220 struct brw_context *brw = brw_context(ctx);
2221 struct intel_context *intel = &brw->intel;
2222 struct brw_wm_prog_key key;
2224 if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
2227 struct gl_fragment_program *fp = (struct gl_fragment_program *)
2228 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program;
2229 struct brw_fragment_program *bfp = brw_fragment_program(fp);
2230 bool program_uses_dfdy = fp->UsesDFdy;
2232 memset(&key, 0, sizeof(key));
2234 if (intel->gen < 6) {
2236 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
2238 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
2239 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
2241 /* Just assume depth testing. */
2242 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
2243 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
2246 if (prog->Name != 0)
2247 key.proj_attrib_mask = 0xffffffff;
2250 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
2252 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2253 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
2256 if (prog->Name == 0)
2257 key.proj_attrib_mask |= 1 << i;
2259 if (intel->gen < 6) {
2260 int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
2263 key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
2267 key.clamp_fragment_color = true;
2269 for (int i = 0; i < MAX_SAMPLERS; i++) {
2270 if (fp->Base.ShadowSamplers & (1 << i)) {
2271 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
2272 key.tex.swizzles[i] =
2273 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
2275 /* Color sampler: assume no swizzling. */
2276 key.tex.swizzles[i] = SWIZZLE_XYZW;
2280 if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
2281 key.drawable_height = ctx->DrawBuffer->Height;
2284 if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
2285 key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
2288 key.nr_color_regions = 1;
2290 key.program_string_id = bfp->id;
2292 uint32_t old_prog_offset = brw->wm.prog_offset;
2293 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
2295 bool success = do_wm_prog(brw, prog, bfp, &key);
2297 brw->wm.prog_offset = old_prog_offset;
2298 brw->wm.prog_data = old_prog_data;