2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/fbobject.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/register_allocate.h"
42 #include "program/sampler.h"
43 #include "program/hash_table.h"
44 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir_print_visitor.h"
56 memset(this, 0, sizeof(*this));
57 this->opcode = BRW_OPCODE_NOP;
58 this->conditional_mod = BRW_CONDITIONAL_NONE;
60 this->dst = reg_undef;
61 this->src[0] = reg_undef;
62 this->src[1] = reg_undef;
63 this->src[2] = reg_undef;
71 fs_inst::fs_inst(enum opcode opcode)
74 this->opcode = opcode;
77 fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
80 this->opcode = opcode;
84 assert(dst.reg_offset >= 0);
87 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
90 this->opcode = opcode;
95 assert(dst.reg_offset >= 0);
96 if (src[0].file == GRF)
97 assert(src[0].reg_offset >= 0);
100 fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
103 this->opcode = opcode;
109 assert(dst.reg_offset >= 0);
110 if (src[0].file == GRF)
111 assert(src[0].reg_offset >= 0);
112 if (src[1].file == GRF)
113 assert(src[1].reg_offset >= 0);
116 fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
117 fs_reg src0, fs_reg src1, fs_reg src2)
120 this->opcode = opcode;
127 assert(dst.reg_offset >= 0);
128 if (src[0].file == GRF)
129 assert(src[0].reg_offset >= 0);
130 if (src[1].file == GRF)
131 assert(src[1].reg_offset >= 0);
132 if (src[2].file == GRF)
133 assert(src[2].reg_offset >= 0);
137 fs_inst::equals(fs_inst *inst)
139 return (opcode == inst->opcode &&
140 dst.equals(inst->dst) &&
141 src[0].equals(inst->src[0]) &&
142 src[1].equals(inst->src[1]) &&
143 src[2].equals(inst->src[2]) &&
144 saturate == inst->saturate &&
145 predicated == inst->predicated &&
146 conditional_mod == inst->conditional_mod &&
147 mlen == inst->mlen &&
148 base_mrf == inst->base_mrf &&
149 sampler == inst->sampler &&
150 target == inst->target &&
152 header_present == inst->header_present &&
153 shadow_compare == inst->shadow_compare &&
154 offset == inst->offset);
158 fs_inst::regs_written()
163 /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
164 * but we don't currently use them...nor do we have an opcode for them.
173 return (opcode == SHADER_OPCODE_TEX ||
174 opcode == FS_OPCODE_TXB ||
175 opcode == SHADER_OPCODE_TXD ||
176 opcode == SHADER_OPCODE_TXF ||
177 opcode == SHADER_OPCODE_TXL ||
178 opcode == SHADER_OPCODE_TXS);
184 return (opcode == SHADER_OPCODE_RCP ||
185 opcode == SHADER_OPCODE_RSQ ||
186 opcode == SHADER_OPCODE_SQRT ||
187 opcode == SHADER_OPCODE_EXP2 ||
188 opcode == SHADER_OPCODE_LOG2 ||
189 opcode == SHADER_OPCODE_SIN ||
190 opcode == SHADER_OPCODE_COS ||
191 opcode == SHADER_OPCODE_INT_QUOTIENT ||
192 opcode == SHADER_OPCODE_INT_REMAINDER ||
193 opcode == SHADER_OPCODE_POW);
199 memset(this, 0, sizeof(*this));
203 /** Generic unset register constructor. */
207 this->file = BAD_FILE;
210 /** Immediate value constructor. */
211 fs_reg::fs_reg(float f)
215 this->type = BRW_REGISTER_TYPE_F;
219 /** Immediate value constructor. */
220 fs_reg::fs_reg(int32_t i)
224 this->type = BRW_REGISTER_TYPE_D;
228 /** Immediate value constructor. */
229 fs_reg::fs_reg(uint32_t u)
233 this->type = BRW_REGISTER_TYPE_UD;
237 /** Fixed brw_reg Immediate value constructor. */
238 fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
241 this->file = FIXED_HW_REG;
242 this->fixed_hw_reg = fixed_hw_reg;
243 this->type = fixed_hw_reg.type;
247 fs_reg::equals(const fs_reg &r) const
249 return (file == r.file &&
251 reg_offset == r.reg_offset &&
253 negate == r.negate &&
255 memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
256 sizeof(fixed_hw_reg)) == 0 &&
262 fs_visitor::type_size(const struct glsl_type *type)
264 unsigned int size, i;
266 switch (type->base_type) {
269 case GLSL_TYPE_FLOAT:
271 return type->components();
272 case GLSL_TYPE_ARRAY:
273 return type_size(type->fields.array) * type->length;
274 case GLSL_TYPE_STRUCT:
276 for (i = 0; i < type->length; i++) {
277 size += type_size(type->fields.structure[i].type);
280 case GLSL_TYPE_SAMPLER:
281 /* Samplers take up no register space, since they're baked in at
286 assert(!"not reached");
292 fs_visitor::fail(const char *format, ...)
302 va_start(va, format);
303 msg = ralloc_vasprintf(mem_ctx, format, va);
305 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg);
307 this->fail_msg = msg;
309 if (INTEL_DEBUG & DEBUG_WM) {
310 fprintf(stderr, "%s", msg);
315 fs_visitor::emit(enum opcode opcode)
317 return emit(fs_inst(opcode));
321 fs_visitor::emit(enum opcode opcode, fs_reg dst)
323 return emit(fs_inst(opcode, dst));
327 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0)
329 return emit(fs_inst(opcode, dst, src0));
333 fs_visitor::emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
335 return emit(fs_inst(opcode, dst, src0, src1));
339 fs_visitor::emit(enum opcode opcode, fs_reg dst,
340 fs_reg src0, fs_reg src1, fs_reg src2)
342 return emit(fs_inst(opcode, dst, src0, src1, src2));
346 fs_visitor::push_force_uncompressed()
348 force_uncompressed_stack++;
352 fs_visitor::pop_force_uncompressed()
354 force_uncompressed_stack--;
355 assert(force_uncompressed_stack >= 0);
359 fs_visitor::push_force_sechalf()
361 force_sechalf_stack++;
365 fs_visitor::pop_force_sechalf()
367 force_sechalf_stack--;
368 assert(force_sechalf_stack >= 0);
372 * Returns how many MRFs an FS opcode will write over.
374 * Note that this is not the 0 or 1 implied writes in an actual gen
375 * instruction -- the FS opcodes often generate MOVs in addition.
378 fs_visitor::implied_mrf_writes(fs_inst *inst)
383 switch (inst->opcode) {
384 case SHADER_OPCODE_RCP:
385 case SHADER_OPCODE_RSQ:
386 case SHADER_OPCODE_SQRT:
387 case SHADER_OPCODE_EXP2:
388 case SHADER_OPCODE_LOG2:
389 case SHADER_OPCODE_SIN:
390 case SHADER_OPCODE_COS:
391 return 1 * c->dispatch_width / 8;
392 case SHADER_OPCODE_POW:
393 case SHADER_OPCODE_INT_QUOTIENT:
394 case SHADER_OPCODE_INT_REMAINDER:
395 return 2 * c->dispatch_width / 8;
396 case SHADER_OPCODE_TEX:
398 case SHADER_OPCODE_TXD:
399 case SHADER_OPCODE_TXF:
400 case SHADER_OPCODE_TXL:
401 case SHADER_OPCODE_TXS:
403 case FS_OPCODE_FB_WRITE:
405 case FS_OPCODE_PULL_CONSTANT_LOAD:
406 case FS_OPCODE_UNSPILL:
408 case FS_OPCODE_SPILL:
411 assert(!"not reached");
417 fs_visitor::virtual_grf_alloc(int size)
419 if (virtual_grf_array_size <= virtual_grf_next) {
420 if (virtual_grf_array_size == 0)
421 virtual_grf_array_size = 16;
423 virtual_grf_array_size *= 2;
424 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
425 virtual_grf_array_size);
427 virtual_grf_sizes[virtual_grf_next] = size;
428 return virtual_grf_next++;
431 /** Fixed HW reg constructor. */
432 fs_reg::fs_reg(enum register_file file, int reg)
437 this->type = BRW_REGISTER_TYPE_F;
440 /** Fixed HW reg constructor. */
441 fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
449 /** Automatic reg constructor. */
450 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
455 this->reg = v->virtual_grf_alloc(v->type_size(type));
456 this->reg_offset = 0;
457 this->type = brw_type_for_base_type(type);
461 fs_visitor::variable_storage(ir_variable *var)
463 return (fs_reg *)hash_table_find(this->variable_ht, var);
467 import_uniforms_callback(const void *key,
471 struct hash_table *dst_ht = (struct hash_table *)closure;
472 const fs_reg *reg = (const fs_reg *)data;
474 if (reg->file != UNIFORM)
477 hash_table_insert(dst_ht, data, key);
480 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
481 * This brings in those uniform definitions
484 fs_visitor::import_uniforms(fs_visitor *v)
486 hash_table_call_foreach(v->variable_ht,
487 import_uniforms_callback,
489 this->params_remap = v->params_remap;
492 /* Our support for uniforms is piggy-backed on the struct
493 * gl_fragment_program, because that's where the values actually
494 * get stored, rather than in some global gl_shader_program uniform
498 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
500 unsigned int offset = 0;
502 if (type->is_matrix()) {
503 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
504 type->vector_elements,
507 for (unsigned int i = 0; i < type->matrix_columns; i++) {
508 offset += setup_uniform_values(loc + offset, column);
514 switch (type->base_type) {
515 case GLSL_TYPE_FLOAT:
519 for (unsigned int i = 0; i < type->vector_elements; i++) {
520 unsigned int param = c->prog_data.nr_params++;
522 assert(param < ARRAY_SIZE(c->prog_data.param));
524 if (ctx->Const.NativeIntegers) {
525 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
527 switch (type->base_type) {
528 case GLSL_TYPE_FLOAT:
529 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
532 c->prog_data.param_convert[param] = PARAM_CONVERT_F2U;
535 c->prog_data.param_convert[param] = PARAM_CONVERT_F2I;
538 c->prog_data.param_convert[param] = PARAM_CONVERT_F2B;
541 assert(!"not reached");
542 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
546 this->param_index[param] = loc;
547 this->param_offset[param] = i;
551 case GLSL_TYPE_STRUCT:
552 for (unsigned int i = 0; i < type->length; i++) {
553 offset += setup_uniform_values(loc + offset,
554 type->fields.structure[i].type);
558 case GLSL_TYPE_ARRAY:
559 for (unsigned int i = 0; i < type->length; i++) {
560 offset += setup_uniform_values(loc + offset, type->fields.array);
564 case GLSL_TYPE_SAMPLER:
565 /* The sampler takes up a slot, but we don't use any values from it. */
569 assert(!"not reached");
575 /* Our support for builtin uniforms is even scarier than non-builtin.
576 * It sits on top of the PROG_STATE_VAR parameters that are
577 * automatically updated from GL context state.
580 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
582 const ir_state_slot *const slots = ir->state_slots;
583 assert(ir->state_slots != NULL);
585 for (unsigned int i = 0; i < ir->num_state_slots; i++) {
586 /* This state reference has already been setup by ir_to_mesa, but we'll
587 * get the same index back here.
589 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
590 (gl_state_index *)slots[i].tokens);
592 /* Add each of the unique swizzles of the element as a parameter.
593 * This'll end up matching the expected layout of the
594 * array/matrix/structure we're trying to fill in.
597 for (unsigned int j = 0; j < 4; j++) {
598 int swiz = GET_SWZ(slots[i].swizzle, j);
599 if (swiz == last_swiz)
603 c->prog_data.param_convert[c->prog_data.nr_params] =
605 this->param_index[c->prog_data.nr_params] = index;
606 this->param_offset[c->prog_data.nr_params] = swiz;
607 c->prog_data.nr_params++;
613 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
615 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
617 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
620 if (ir->pixel_center_integer) {
621 emit(BRW_OPCODE_MOV, wpos, this->pixel_x);
623 emit(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f));
628 if (!flip && ir->pixel_center_integer) {
629 emit(BRW_OPCODE_MOV, wpos, this->pixel_y);
631 fs_reg pixel_y = this->pixel_y;
632 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
635 pixel_y.negate = true;
636 offset += c->key.drawable_height - 1.0;
639 emit(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset));
644 if (intel->gen >= 6) {
645 emit(BRW_OPCODE_MOV, wpos,
646 fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
648 emit(FS_OPCODE_LINTERP, wpos,
649 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
650 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
651 interp_reg(FRAG_ATTRIB_WPOS, 2));
655 /* gl_FragCoord.w: Already set up in emit_interpolation */
656 emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
662 fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp,
663 glsl_interp_qualifier interpolation_mode,
666 brw_wm_barycentric_interp_mode barycoord_mode;
668 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
669 barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
671 barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
673 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
674 barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
676 barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
678 return emit(FS_OPCODE_LINTERP, attr,
679 this->delta_x[barycoord_mode],
680 this->delta_y[barycoord_mode], interp);
684 fs_visitor::emit_general_interpolation(ir_variable *ir)
686 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
687 reg->type = brw_type_for_base_type(ir->type->get_scalar_type());
690 unsigned int array_elements;
691 const glsl_type *type;
693 if (ir->type->is_array()) {
694 array_elements = ir->type->length;
695 if (array_elements == 0) {
696 fail("dereferenced array '%s' has length 0\n", ir->name);
698 type = ir->type->fields.array;
704 glsl_interp_qualifier interpolation_mode =
705 ir->determine_interpolation_mode(c->key.flat_shade);
707 int location = ir->location;
708 for (unsigned int i = 0; i < array_elements; i++) {
709 for (unsigned int j = 0; j < type->matrix_columns; j++) {
710 if (urb_setup[location] == -1) {
711 /* If there's no incoming setup data for this slot, don't
712 * emit interpolation for it.
714 attr.reg_offset += type->vector_elements;
719 if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
720 /* Constant interpolation (flat shading) case. The SF has
721 * handed us defined values in only the constant offset
722 * field of the setup reg.
724 for (unsigned int k = 0; k < type->vector_elements; k++) {
725 struct brw_reg interp = interp_reg(location, k);
726 interp = suboffset(interp, 3);
727 interp.type = reg->type;
728 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
732 /* Smooth/noperspective interpolation case. */
733 for (unsigned int k = 0; k < type->vector_elements; k++) {
734 /* FINISHME: At some point we probably want to push
735 * this farther by giving similar treatment to the
736 * other potentially constant components of the
737 * attribute, as well as making brw_vs_constval.c
738 * handle varyings other than gl_TexCoord.
740 if (location >= FRAG_ATTRIB_TEX0 &&
741 location <= FRAG_ATTRIB_TEX7 &&
742 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) {
743 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
745 struct brw_reg interp = interp_reg(location, k);
746 emit_linterp(attr, fs_reg(interp), interpolation_mode,
748 if (brw->needs_unlit_centroid_workaround && ir->centroid) {
749 /* Get the pixel/sample mask into f0 so that we know
750 * which pixels are lit. Then, for each channel that is
751 * unlit, replace the centroid data with non-centroid
754 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
755 fs_inst *inst = emit_linterp(attr, fs_reg(interp),
756 interpolation_mode, false);
757 inst->predicated = true;
758 inst->predicate_inverse = true;
760 if (intel->gen < 6) {
761 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
776 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
778 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
780 /* The frontfacing comes in as a bit in the thread payload. */
781 if (intel->gen >= 6) {
782 emit(BRW_OPCODE_ASR, *reg,
783 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
785 emit(BRW_OPCODE_NOT, *reg, *reg);
786 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
788 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
789 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
792 fs_inst *inst = emit(BRW_OPCODE_CMP, *reg,
795 inst->conditional_mod = BRW_CONDITIONAL_L;
796 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
803 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
806 case SHADER_OPCODE_RCP:
807 case SHADER_OPCODE_RSQ:
808 case SHADER_OPCODE_SQRT:
809 case SHADER_OPCODE_EXP2:
810 case SHADER_OPCODE_LOG2:
811 case SHADER_OPCODE_SIN:
812 case SHADER_OPCODE_COS:
815 assert(!"not reached: bad math opcode");
819 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
820 * might be able to do better by doing execsize = 1 math and then
821 * expanding that result out, but we would need to be careful with
824 * Gen 6 hardware ignores source modifiers (negate and abs) on math
825 * instructions, so we also move to a temp to set those up.
827 if (intel->gen == 6 && (src.file == UNIFORM ||
830 fs_reg expanded = fs_reg(this, glsl_type::float_type);
831 emit(BRW_OPCODE_MOV, expanded, src);
835 fs_inst *inst = emit(opcode, dst, src);
837 if (intel->gen < 6) {
839 inst->mlen = c->dispatch_width / 8;
846 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
852 case SHADER_OPCODE_POW:
853 case SHADER_OPCODE_INT_QUOTIENT:
854 case SHADER_OPCODE_INT_REMAINDER:
857 assert(!"not reached: unsupported binary math opcode.");
861 if (intel->gen >= 7) {
862 inst = emit(opcode, dst, src0, src1);
863 } else if (intel->gen == 6) {
864 /* Can't do hstride == 0 args to gen6 math, so expand it out.
866 * The hardware ignores source modifiers (negate and abs) on math
867 * instructions, so we also move to a temp to set those up.
869 if (src0.file == UNIFORM || src0.abs || src0.negate) {
870 fs_reg expanded = fs_reg(this, glsl_type::float_type);
871 expanded.type = src0.type;
872 emit(BRW_OPCODE_MOV, expanded, src0);
876 if (src1.file == UNIFORM || src1.abs || src1.negate) {
877 fs_reg expanded = fs_reg(this, glsl_type::float_type);
878 expanded.type = src1.type;
879 emit(BRW_OPCODE_MOV, expanded, src1);
883 inst = emit(opcode, dst, src0, src1);
885 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
888 * "Operand0[7]. For the INT DIV functions, this operand is the
891 * "Operand1[7]. For the INT DIV functions, this operand is the
894 bool is_int_div = opcode != SHADER_OPCODE_POW;
895 fs_reg &op0 = is_int_div ? src1 : src0;
896 fs_reg &op1 = is_int_div ? src0 : src1;
898 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
899 inst = emit(opcode, dst, op0, reg_null_f);
901 inst->base_mrf = base_mrf;
902 inst->mlen = 2 * c->dispatch_width / 8;
908 * To be called after the last _mesa_add_state_reference() call, to
909 * set up prog_data.param[] for assign_curb_setup() and
910 * setup_pull_constants().
913 fs_visitor::setup_paramvalues_refs()
915 if (c->dispatch_width != 8)
918 /* Set up the pointers to ParamValues now that that array is finalized. */
919 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
920 c->prog_data.param[i] =
921 (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] +
922 this->param_offset[i];
927 fs_visitor::assign_curb_setup()
929 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
930 if (c->dispatch_width == 8) {
931 c->prog_data.first_curbe_grf = c->nr_payload_regs;
933 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
936 /* Map the offsets in the UNIFORM file to fixed HW regs. */
937 foreach_list(node, &this->instructions) {
938 fs_inst *inst = (fs_inst *)node;
940 for (unsigned int i = 0; i < 3; i++) {
941 if (inst->src[i].file == UNIFORM) {
942 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
943 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
947 inst->src[i].file = FIXED_HW_REG;
948 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
955 fs_visitor::calculate_urb_setup()
957 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
962 /* Figure out where each of the incoming setup attributes lands. */
963 if (intel->gen >= 6) {
964 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
965 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
966 urb_setup[i] = urb_next++;
970 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
971 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
972 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
973 int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
976 urb_setup[fp_index] = urb_next++;
981 * It's a FS only attribute, and we did interpolation for this attribute
982 * in SF thread. So, count it here, too.
984 * See compile_sf_prog() for more info.
986 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
987 urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
990 /* Each attribute is 4 setup channels, each of which is half a reg. */
991 c->prog_data.urb_read_length = urb_next * 2;
995 fs_visitor::assign_urb_setup()
997 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
999 /* Offset all the urb_setup[] index by the actual position of the
1000 * setup regs, now that the location of the constants has been chosen.
1002 foreach_list(node, &this->instructions) {
1003 fs_inst *inst = (fs_inst *)node;
1005 if (inst->opcode == FS_OPCODE_LINTERP) {
1006 assert(inst->src[2].file == FIXED_HW_REG);
1007 inst->src[2].fixed_hw_reg.nr += urb_start;
1010 if (inst->opcode == FS_OPCODE_CINTERP) {
1011 assert(inst->src[0].file == FIXED_HW_REG);
1012 inst->src[0].fixed_hw_reg.nr += urb_start;
1016 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1020 * Split large virtual GRFs into separate components if we can.
1022 * This is mostly duplicated with what brw_fs_vector_splitting does,
1023 * but that's really conservative because it's afraid of doing
1024 * splitting that doesn't result in real progress after the rest of
1025 * the optimization phases, which would cause infinite looping in
1026 * optimization. We can do it once here, safely. This also has the
1027 * opportunity to split interpolated values, or maybe even uniforms,
1028 * which we don't have at the IR level.
1030 * We want to split, because virtual GRFs are what we register
1031 * allocate and spill (due to contiguousness requirements for some
1032 * instructions), and they're what we naturally generate in the
1033 * codegen process, but most virtual GRFs don't actually need to be
1034 * contiguous sets of GRFs. If we split, we'll end up with reduced
1035 * live intervals and better dead code elimination and coalescing.
1038 fs_visitor::split_virtual_grfs()
1040 int num_vars = this->virtual_grf_next;
1041 bool split_grf[num_vars];
1042 int new_virtual_grf[num_vars];
1044 /* Try to split anything > 0 sized. */
1045 for (int i = 0; i < num_vars; i++) {
1046 if (this->virtual_grf_sizes[i] != 1)
1047 split_grf[i] = true;
1049 split_grf[i] = false;
1053 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF) {
1054 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
1055 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
1056 * Gen6, that was the only supported interpolation mode, and since Gen6,
1057 * delta_x and delta_y are in fixed hardware registers.
1059 split_grf[this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg] =
1063 foreach_list(node, &this->instructions) {
1064 fs_inst *inst = (fs_inst *)node;
1066 /* Texturing produces 4 contiguous registers, so no splitting. */
1067 if (inst->is_tex()) {
1068 split_grf[inst->dst.reg] = false;
1072 /* Allocate new space for split regs. Note that the virtual
1073 * numbers will be contiguous.
1075 for (int i = 0; i < num_vars; i++) {
1077 new_virtual_grf[i] = virtual_grf_alloc(1);
1078 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
1079 int reg = virtual_grf_alloc(1);
1080 assert(reg == new_virtual_grf[i] + j - 1);
1083 this->virtual_grf_sizes[i] = 1;
1087 foreach_list(node, &this->instructions) {
1088 fs_inst *inst = (fs_inst *)node;
1090 if (inst->dst.file == GRF &&
1091 split_grf[inst->dst.reg] &&
1092 inst->dst.reg_offset != 0) {
1093 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
1094 inst->dst.reg_offset - 1);
1095 inst->dst.reg_offset = 0;
1097 for (int i = 0; i < 3; i++) {
1098 if (inst->src[i].file == GRF &&
1099 split_grf[inst->src[i].reg] &&
1100 inst->src[i].reg_offset != 0) {
1101 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
1102 inst->src[i].reg_offset - 1);
1103 inst->src[i].reg_offset = 0;
1107 this->live_intervals_valid = false;
1111 fs_visitor::remove_dead_constants()
1113 if (c->dispatch_width == 8) {
1114 this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
1116 for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
1117 this->params_remap[i] = -1;
1119 /* Find which params are still in use. */
1120 foreach_list(node, &this->instructions) {
1121 fs_inst *inst = (fs_inst *)node;
1123 for (int i = 0; i < 3; i++) {
1124 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1126 if (inst->src[i].file != UNIFORM)
1129 assert(constant_nr < (int)c->prog_data.nr_params);
1131 /* For now, set this to non-negative. We'll give it the
1132 * actual new number in a moment, in order to keep the
1133 * register numbers nicely ordered.
1135 this->params_remap[constant_nr] = 0;
1139 /* Figure out what the new numbers for the params will be. At some
1140 * point when we're doing uniform array access, we're going to want
1141 * to keep the distinction between .reg and .reg_offset, but for
1142 * now we don't care.
1144 unsigned int new_nr_params = 0;
1145 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1146 if (this->params_remap[i] != -1) {
1147 this->params_remap[i] = new_nr_params++;
1151 /* Update the list of params to be uploaded to match our new numbering. */
1152 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
1153 int remapped = this->params_remap[i];
1158 /* We've already done setup_paramvalues_refs() so no need to worry
1159 * about param_index and param_offset.
1161 c->prog_data.param[remapped] = c->prog_data.param[i];
1162 c->prog_data.param_convert[remapped] = c->prog_data.param_convert[i];
1165 c->prog_data.nr_params = new_nr_params;
1167 /* This should have been generated in the 8-wide pass already. */
1168 assert(this->params_remap);
1171 /* Now do the renumbering of the shader to remove unused params. */
1172 foreach_list(node, &this->instructions) {
1173 fs_inst *inst = (fs_inst *)node;
1175 for (int i = 0; i < 3; i++) {
1176 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
1178 if (inst->src[i].file != UNIFORM)
1181 assert(this->params_remap[constant_nr] != -1);
1182 inst->src[i].reg = this->params_remap[constant_nr];
1183 inst->src[i].reg_offset = 0;
1191 * Choose accesses from the UNIFORM file to demote to using the pull
1194 * We allow a fragment shader to have more than the specified minimum
1195 * maximum number of fragment shader uniform components (64). If
1196 * there are too many of these, they'd fill up all of register space.
1197 * So, this will push some of them out to the pull constant buffer and
1198 * update the program to load them.
1201 fs_visitor::setup_pull_constants()
1203 /* Only allow 16 registers (128 uniform components) as push constants. */
1204 unsigned int max_uniform_components = 16 * 8;
1205 if (c->prog_data.nr_params <= max_uniform_components)
1208 if (c->dispatch_width == 16) {
1209 fail("Pull constants not supported in 16-wide\n");
1213 /* Just demote the end of the list. We could probably do better
1214 * here, demoting things that are rarely used in the program first.
1216 int pull_uniform_base = max_uniform_components;
1217 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base;
1219 foreach_list(node, &this->instructions) {
1220 fs_inst *inst = (fs_inst *)node;
1222 for (int i = 0; i < 3; i++) {
1223 if (inst->src[i].file != UNIFORM)
1226 int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset;
1227 if (uniform_nr < pull_uniform_base)
1230 fs_reg dst = fs_reg(this, glsl_type::float_type);
1231 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD,
1233 pull->offset = ((uniform_nr - pull_uniform_base) * 4) & ~15;
1234 pull->ir = inst->ir;
1235 pull->annotation = inst->annotation;
1236 pull->base_mrf = 14;
1239 inst->insert_before(pull);
1241 inst->src[i].file = GRF;
1242 inst->src[i].reg = dst.reg;
1243 inst->src[i].reg_offset = 0;
1244 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3;
1248 for (int i = 0; i < pull_uniform_count; i++) {
1249 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i];
1250 c->prog_data.pull_param_convert[i] =
1251 c->prog_data.param_convert[pull_uniform_base + i];
1253 c->prog_data.nr_params -= pull_uniform_count;
1254 c->prog_data.nr_pull_params = pull_uniform_count;
1258 * Attempts to move immediate constants into the immediate
1259 * constant slot of following instructions.
1261 * Immediate constants are a bit tricky -- they have to be in the last
1262 * operand slot, you can't do abs/negate on them,
1266 fs_visitor::propagate_constants()
1268 bool progress = false;
1270 calculate_live_intervals();
1272 foreach_list(node, &this->instructions) {
1273 fs_inst *inst = (fs_inst *)node;
1275 if (inst->opcode != BRW_OPCODE_MOV ||
1277 inst->dst.file != GRF || inst->src[0].file != IMM ||
1278 inst->dst.type != inst->src[0].type ||
1279 (c->dispatch_width == 16 &&
1280 (inst->force_uncompressed || inst->force_sechalf)))
1283 /* Don't bother with cases where we should have had the
1284 * operation on the constant folded in GLSL already.
1289 /* Found a move of a constant to a GRF. Find anything else using the GRF
1290 * before it's written, and replace it with the constant if we can.
1292 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1293 !scan_inst->is_tail_sentinel();
1294 scan_inst = (fs_inst *)scan_inst->next) {
1295 if (scan_inst->opcode == BRW_OPCODE_DO ||
1296 scan_inst->opcode == BRW_OPCODE_WHILE ||
1297 scan_inst->opcode == BRW_OPCODE_ELSE ||
1298 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1302 for (int i = 2; i >= 0; i--) {
1303 if (scan_inst->src[i].file != GRF ||
1304 scan_inst->src[i].reg != inst->dst.reg ||
1305 scan_inst->src[i].reg_offset != inst->dst.reg_offset)
1308 /* Don't bother with cases where we should have had the
1309 * operation on the constant folded in GLSL already.
1311 if (scan_inst->src[i].negate || scan_inst->src[i].abs)
1314 switch (scan_inst->opcode) {
1315 case BRW_OPCODE_MOV:
1316 scan_inst->src[i] = inst->src[0];
1320 case BRW_OPCODE_MUL:
1321 case BRW_OPCODE_ADD:
1323 scan_inst->src[i] = inst->src[0];
1325 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1326 /* Fit this constant in by commuting the operands.
1327 * Exception: we can't do this for 32-bit integer MUL
1328 * because it's asymmetric.
1330 if (scan_inst->opcode == BRW_OPCODE_MUL &&
1331 (scan_inst->src[1].type == BRW_REGISTER_TYPE_D ||
1332 scan_inst->src[1].type == BRW_REGISTER_TYPE_UD))
1334 scan_inst->src[0] = scan_inst->src[1];
1335 scan_inst->src[1] = inst->src[0];
1340 case BRW_OPCODE_CMP:
1343 scan_inst->src[i] = inst->src[0];
1345 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1348 new_cmod = brw_swap_cmod(scan_inst->conditional_mod);
1349 if (new_cmod != ~0u) {
1350 /* Fit this constant in by swapping the operands and
1353 scan_inst->src[0] = scan_inst->src[1];
1354 scan_inst->src[1] = inst->src[0];
1355 scan_inst->conditional_mod = new_cmod;
1361 case BRW_OPCODE_SEL:
1363 scan_inst->src[i] = inst->src[0];
1365 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1366 scan_inst->src[0] = scan_inst->src[1];
1367 scan_inst->src[1] = inst->src[0];
1369 /* If this was predicated, flipping operands means
1370 * we also need to flip the predicate.
1372 if (scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) {
1373 scan_inst->predicate_inverse =
1374 !scan_inst->predicate_inverse;
1380 case SHADER_OPCODE_RCP:
1381 /* The hardware doesn't do math on immediate values
1382 * (because why are you doing that, seriously?), but
1383 * the correct answer is to just constant fold it
1387 if (inst->src[0].imm.f != 0.0f) {
1388 scan_inst->opcode = BRW_OPCODE_MOV;
1389 scan_inst->src[0] = inst->src[0];
1390 scan_inst->src[0].imm.f = 1.0f / scan_inst->src[0].imm.f;
1400 if (scan_inst->dst.file == GRF &&
1401 scan_inst->dst.reg == inst->dst.reg &&
1402 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1403 scan_inst->is_tex())) {
1410 this->live_intervals_valid = false;
1417 * Attempts to move immediate constants into the immediate
1418 * constant slot of following instructions.
1420 * Immediate constants are a bit tricky -- they have to be in the last
1421 * operand slot, you can't do abs/negate on them,
1425 fs_visitor::opt_algebraic()
1427 bool progress = false;
1429 calculate_live_intervals();
1431 foreach_list(node, &this->instructions) {
1432 fs_inst *inst = (fs_inst *)node;
1434 switch (inst->opcode) {
1435 case BRW_OPCODE_MUL:
1436 if (inst->src[1].file != IMM)
1440 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1441 inst->src[1].imm.f == 1.0) {
1442 inst->opcode = BRW_OPCODE_MOV;
1443 inst->src[1] = reg_undef;
1458 * Must be called after calculate_live_intervales() to remove unused
1459 * writes to registers -- register allocation will fail otherwise
1460 * because something deffed but not used won't be considered to
1461 * interfere with other regs.
1464 fs_visitor::dead_code_eliminate()
1466 bool progress = false;
1469 calculate_live_intervals();
1471 foreach_list_safe(node, &this->instructions) {
1472 fs_inst *inst = (fs_inst *)node;
1474 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
1483 live_intervals_valid = false;
1489 * Implements a second type of register coalescing: This one checks if
1490 * the two regs involved in a raw move don't interfere, in which case
1491 * they can both by stored in the same place and the MOV removed.
1494 fs_visitor::register_coalesce_2()
1496 bool progress = false;
1498 calculate_live_intervals();
1500 foreach_list_safe(node, &this->instructions) {
1501 fs_inst *inst = (fs_inst *)node;
1503 if (inst->opcode != BRW_OPCODE_MOV ||
1506 inst->src[0].file != GRF ||
1507 inst->src[0].negate ||
1509 inst->src[0].smear != -1 ||
1510 inst->dst.file != GRF ||
1511 inst->dst.type != inst->src[0].type ||
1512 virtual_grf_sizes[inst->src[0].reg] != 1 ||
1513 virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) {
1517 int reg_from = inst->src[0].reg;
1518 assert(inst->src[0].reg_offset == 0);
1519 int reg_to = inst->dst.reg;
1520 int reg_to_offset = inst->dst.reg_offset;
1522 foreach_list_safe(node, &this->instructions) {
1523 fs_inst *scan_inst = (fs_inst *)node;
1525 if (scan_inst->dst.file == GRF &&
1526 scan_inst->dst.reg == reg_from) {
1527 scan_inst->dst.reg = reg_to;
1528 scan_inst->dst.reg_offset = reg_to_offset;
1530 for (int i = 0; i < 3; i++) {
1531 if (scan_inst->src[i].file == GRF &&
1532 scan_inst->src[i].reg == reg_from) {
1533 scan_inst->src[i].reg = reg_to;
1534 scan_inst->src[i].reg_offset = reg_to_offset;
1540 live_intervals_valid = false;
1549 fs_visitor::register_coalesce()
1551 bool progress = false;
1555 foreach_list_safe(node, &this->instructions) {
1556 fs_inst *inst = (fs_inst *)node;
1558 /* Make sure that we dominate the instructions we're going to
1559 * scan for interfering with our coalescing, or we won't have
1560 * scanned enough to see if anything interferes with our
1561 * coalescing. We don't dominate the following instructions if
1562 * we're in a loop or an if block.
1564 switch (inst->opcode) {
1568 case BRW_OPCODE_WHILE:
1574 case BRW_OPCODE_ENDIF:
1580 if (loop_depth || if_depth)
1583 if (inst->opcode != BRW_OPCODE_MOV ||
1586 inst->dst.file != GRF || (inst->src[0].file != GRF &&
1587 inst->src[0].file != UNIFORM)||
1588 inst->dst.type != inst->src[0].type)
1591 bool has_source_modifiers = inst->src[0].abs || inst->src[0].negate;
1593 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1594 * them: check for no writes to either one until the exit of the
1597 bool interfered = false;
1599 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1600 !scan_inst->is_tail_sentinel();
1601 scan_inst = (fs_inst *)scan_inst->next) {
1602 if (scan_inst->dst.file == GRF) {
1603 if (scan_inst->dst.reg == inst->dst.reg &&
1604 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1605 scan_inst->is_tex())) {
1609 if (inst->src[0].file == GRF &&
1610 scan_inst->dst.reg == inst->src[0].reg &&
1611 (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
1612 scan_inst->is_tex())) {
1618 /* The gen6 MATH instruction can't handle source modifiers or
1619 * unusual register regions, so avoid coalescing those for
1620 * now. We should do something more specific.
1622 if (intel->gen >= 6 &&
1623 scan_inst->is_math() &&
1624 (has_source_modifiers || inst->src[0].file == UNIFORM)) {
1629 /* The accumulator result appears to get used for the
1630 * conditional modifier generation. When negating a UD
1631 * value, there is a 33rd bit generated for the sign in the
1632 * accumulator value, so now you can't check, for example,
1633 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1635 if (scan_inst->conditional_mod &&
1636 inst->src[0].negate &&
1637 inst->src[0].type == BRW_REGISTER_TYPE_UD) {
1646 /* Rewrite the later usage to point at the source of the move to
1649 for (fs_inst *scan_inst = inst;
1650 !scan_inst->is_tail_sentinel();
1651 scan_inst = (fs_inst *)scan_inst->next) {
1652 for (int i = 0; i < 3; i++) {
1653 if (scan_inst->src[i].file == GRF &&
1654 scan_inst->src[i].reg == inst->dst.reg &&
1655 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
1656 fs_reg new_src = inst->src[0];
1657 if (scan_inst->src[i].abs) {
1661 new_src.negate ^= scan_inst->src[i].negate;
1662 scan_inst->src[i] = new_src;
1672 live_intervals_valid = false;
1679 fs_visitor::compute_to_mrf()
1681 bool progress = false;
1684 calculate_live_intervals();
1686 foreach_list_safe(node, &this->instructions) {
1687 fs_inst *inst = (fs_inst *)node;
1692 if (inst->opcode != BRW_OPCODE_MOV ||
1694 inst->dst.file != MRF || inst->src[0].file != GRF ||
1695 inst->dst.type != inst->src[0].type ||
1696 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
1699 /* Work out which hardware MRF registers are written by this
1702 int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4;
1704 if (inst->dst.reg & BRW_MRF_COMPR4) {
1705 mrf_high = mrf_low + 4;
1706 } else if (c->dispatch_width == 16 &&
1707 (!inst->force_uncompressed && !inst->force_sechalf)) {
1708 mrf_high = mrf_low + 1;
1713 /* Can't compute-to-MRF this GRF if someone else was going to
1716 if (this->virtual_grf_use[inst->src[0].reg] > ip)
1719 /* Found a move of a GRF to a MRF. Let's see if we can go
1720 * rewrite the thing that made this GRF to write into the MRF.
1723 for (scan_inst = (fs_inst *)inst->prev;
1724 scan_inst->prev != NULL;
1725 scan_inst = (fs_inst *)scan_inst->prev) {
1726 if (scan_inst->dst.file == GRF &&
1727 scan_inst->dst.reg == inst->src[0].reg) {
1728 /* Found the last thing to write our reg we want to turn
1729 * into a compute-to-MRF.
1732 if (scan_inst->is_tex()) {
1733 /* texturing writes several continuous regs, so we can't
1734 * compute-to-mrf that.
1739 /* If it's predicated, it (probably) didn't populate all
1740 * the channels. We might be able to rewrite everything
1741 * that writes that reg, but it would require smarter
1742 * tracking to delay the rewriting until complete success.
1744 if (scan_inst->predicated)
1747 /* If it's half of register setup and not the same half as
1748 * our MOV we're trying to remove, bail for now.
1750 if (scan_inst->force_uncompressed != inst->force_uncompressed ||
1751 scan_inst->force_sechalf != inst->force_sechalf) {
1755 /* SEND instructions can't have MRF as a destination. */
1756 if (scan_inst->mlen)
1759 if (intel->gen >= 6) {
1760 /* gen6 math instructions must have the destination be
1761 * GRF, so no compute-to-MRF for them.
1763 if (scan_inst->is_math()) {
1768 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
1769 /* Found the creator of our MRF's source value. */
1770 scan_inst->dst.file = MRF;
1771 scan_inst->dst.reg = inst->dst.reg;
1772 scan_inst->saturate |= inst->saturate;
1779 /* We don't handle flow control here. Most computation of
1780 * values that end up in MRFs are shortly before the MRF
1783 if (scan_inst->opcode == BRW_OPCODE_DO ||
1784 scan_inst->opcode == BRW_OPCODE_WHILE ||
1785 scan_inst->opcode == BRW_OPCODE_ELSE ||
1786 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1790 /* You can't read from an MRF, so if someone else reads our
1791 * MRF's source GRF that we wanted to rewrite, that stops us.
1793 bool interfered = false;
1794 for (int i = 0; i < 3; i++) {
1795 if (scan_inst->src[i].file == GRF &&
1796 scan_inst->src[i].reg == inst->src[0].reg &&
1797 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
1804 if (scan_inst->dst.file == MRF) {
1805 /* If somebody else writes our MRF here, we can't
1806 * compute-to-MRF before that.
1808 int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4;
1811 if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
1812 scan_mrf_high = scan_mrf_low + 4;
1813 } else if (c->dispatch_width == 16 &&
1814 (!scan_inst->force_uncompressed &&
1815 !scan_inst->force_sechalf)) {
1816 scan_mrf_high = scan_mrf_low + 1;
1818 scan_mrf_high = scan_mrf_low;
1821 if (mrf_low == scan_mrf_low ||
1822 mrf_low == scan_mrf_high ||
1823 mrf_high == scan_mrf_low ||
1824 mrf_high == scan_mrf_high) {
1829 if (scan_inst->mlen > 0) {
1830 /* Found a SEND instruction, which means that there are
1831 * live values in MRFs from base_mrf to base_mrf +
1832 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1835 if (mrf_low >= scan_inst->base_mrf &&
1836 mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
1839 if (mrf_high >= scan_inst->base_mrf &&
1840 mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
1851 * Walks through basic blocks, looking for repeated MRF writes and
1852 * removing the later ones.
1855 fs_visitor::remove_duplicate_mrf_writes()
1857 fs_inst *last_mrf_move[16];
1858 bool progress = false;
1860 /* Need to update the MRF tracking for compressed instructions. */
1861 if (c->dispatch_width == 16)
1864 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1866 foreach_list_safe(node, &this->instructions) {
1867 fs_inst *inst = (fs_inst *)node;
1869 switch (inst->opcode) {
1871 case BRW_OPCODE_WHILE:
1873 case BRW_OPCODE_ELSE:
1874 case BRW_OPCODE_ENDIF:
1875 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1881 if (inst->opcode == BRW_OPCODE_MOV &&
1882 inst->dst.file == MRF) {
1883 fs_inst *prev_inst = last_mrf_move[inst->dst.reg];
1884 if (prev_inst && inst->equals(prev_inst)) {
1891 /* Clear out the last-write records for MRFs that were overwritten. */
1892 if (inst->dst.file == MRF) {
1893 last_mrf_move[inst->dst.reg] = NULL;
1896 if (inst->mlen > 0) {
1897 /* Found a SEND instruction, which will include two or fewer
1898 * implied MRF writes. We could do better here.
1900 for (int i = 0; i < implied_mrf_writes(inst); i++) {
1901 last_mrf_move[inst->base_mrf + i] = NULL;
1905 /* Clear out any MRF move records whose sources got overwritten. */
1906 if (inst->dst.file == GRF) {
1907 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
1908 if (last_mrf_move[i] &&
1909 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
1910 last_mrf_move[i] = NULL;
1915 if (inst->opcode == BRW_OPCODE_MOV &&
1916 inst->dst.file == MRF &&
1917 inst->src[0].file == GRF &&
1918 !inst->predicated) {
1919 last_mrf_move[inst->dst.reg] = inst;
1927 * Possibly returns an instruction that set up @param reg.
1929 * Sometimes we want to take the result of some expression/variable
1930 * dereference tree and rewrite the instruction generating the result
1931 * of the tree. When processing the tree, we know that the
1932 * instructions generated are all writing temporaries that are dead
1933 * outside of this tree. So, if we have some instructions that write
1934 * a temporary, we're free to point that temp write somewhere else.
1936 * Note that this doesn't guarantee that the instruction generated
1937 * only reg -- it might be the size=4 destination of a texture instruction.
1940 fs_visitor::get_instruction_generating_reg(fs_inst *start,
1946 end->force_uncompressed ||
1947 end->force_sechalf ||
1948 !reg.equals(end->dst)) {
1958 uint32_t prog_offset_16 = 0;
1959 uint32_t orig_nr_params = c->prog_data.nr_params;
1961 brw_wm_payload_setup(brw, c);
1963 if (c->dispatch_width == 16) {
1964 /* align to 64 byte boundary. */
1965 while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
1969 /* Save off the start of this 16-wide program in case we succeed. */
1970 prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction);
1972 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1978 calculate_urb_setup();
1980 emit_interpolation_setup_gen4();
1982 emit_interpolation_setup_gen6();
1984 /* Generate FS IR for main(). (the visitor only descends into
1985 * functions called "main").
1987 foreach_list(node, &*shader->ir) {
1988 ir_instruction *ir = (ir_instruction *)node;
1990 this->result = reg_undef;
1998 split_virtual_grfs();
2000 setup_paramvalues_refs();
2001 setup_pull_constants();
2007 progress = remove_duplicate_mrf_writes() || progress;
2009 progress = propagate_constants() || progress;
2010 progress = opt_algebraic() || progress;
2011 progress = opt_cse() || progress;
2012 progress = opt_copy_propagate() || progress;
2013 progress = register_coalesce() || progress;
2014 progress = register_coalesce_2() || progress;
2015 progress = compute_to_mrf() || progress;
2016 progress = dead_code_eliminate() || progress;
2019 remove_dead_constants();
2021 schedule_instructions();
2023 assign_curb_setup();
2027 /* Debug of register spilling: Go spill everything. */
2028 int virtual_grf_count = virtual_grf_next;
2029 for (int i = 0; i < virtual_grf_count; i++) {
2035 assign_regs_trivial();
2037 while (!assign_regs()) {
2043 assert(force_uncompressed_stack == 0);
2044 assert(force_sechalf_stack == 0);
2051 if (c->dispatch_width == 8) {
2052 c->prog_data.reg_blocks = brw_register_blocks(grf_used);
2054 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
2055 c->prog_data.prog_offset_16 = prog_offset_16;
2057 /* Make sure we didn't try to sneak in an extra uniform */
2058 assert(orig_nr_params == c->prog_data.nr_params);
2059 (void) orig_nr_params;
2066 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
2067 struct gl_shader_program *prog)
2069 struct intel_context *intel = &brw->intel;
2074 struct brw_shader *shader =
2075 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2079 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
2080 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
2081 _mesa_print_ir(shader->ir, NULL);
2085 /* Now the main event: Visit the shader IR and generate our FS IR for it.
2087 c->dispatch_width = 8;
2089 fs_visitor v(c, prog, shader);
2091 prog->LinkStatus = false;
2092 ralloc_strcat(&prog->InfoLog, v.fail_msg);
2094 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n",
2100 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
2101 c->dispatch_width = 16;
2102 fs_visitor v2(c, prog, shader);
2103 v2.import_uniforms(&v);
2107 c->prog_data.dispatch_width = 8;
2113 brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
2115 struct brw_context *brw = brw_context(ctx);
2116 struct brw_wm_prog_key key;
2118 /* As a temporary measure we assume that all programs use dFdy() (and hence
2119 * need to be compiled differently depending on whether we're rendering to
2120 * an FBO). FIXME: set this bool correctly based on the contents of the
2123 bool program_uses_dfdy = true;
2125 if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
2128 struct gl_fragment_program *fp = (struct gl_fragment_program *)
2129 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program;
2130 struct brw_fragment_program *bfp = brw_fragment_program(fp);
2132 memset(&key, 0, sizeof(key));
2135 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
2137 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
2138 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
2140 /* Just assume depth testing. */
2141 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
2142 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
2144 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
2145 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2146 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
2149 key.proj_attrib_mask |= 1 << i;
2151 int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
2154 key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
2157 key.clamp_fragment_color = true;
2159 for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
2160 if (fp->Base.ShadowSamplers & (1 << i))
2161 key.tex.compare_funcs[i] = GL_LESS;
2163 /* FINISHME: depth compares might use (0,0,0,W) for example */
2164 key.tex.swizzles[i] = SWIZZLE_XYZW;
2167 if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
2168 key.drawable_height = ctx->DrawBuffer->Height;
2171 if ((fp->Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
2172 key.render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
2175 key.nr_color_regions = 1;
2177 key.program_string_id = bfp->id;
2179 uint32_t old_prog_offset = brw->wm.prog_offset;
2180 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
2182 bool success = do_wm_prog(brw, prog, bfp, &key);
2184 brw->wm.prog_offset = old_prog_offset;
2185 brw->wm.prog_data = old_prog_data;