2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "program/prog_parameter.h"
39 #include "program/prog_print.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_print_visitor.h"
52 #define MAX_INSTRUCTION (1 << 30)
55 fs_visitor::type_size(const struct glsl_type *type)
59 switch (type->base_type) {
64 return type->components();
66 return type_size(type->fields.array) * type->length;
67 case GLSL_TYPE_STRUCT:
69 for (i = 0; i < type->length; i++) {
70 size += type_size(type->fields.structure[i].type);
73 case GLSL_TYPE_SAMPLER:
74 /* Samplers take up no register space, since they're baked in at
79 assert(!"not reached");
85 fs_visitor::fail(const char *format, ...)
96 msg = ralloc_vasprintf(mem_ctx, format, va);
98 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg);
100 this->fail_msg = msg;
102 if (INTEL_DEBUG & DEBUG_WM) {
103 fprintf(stderr, "%s", msg);
108 fs_visitor::push_force_uncompressed()
110 force_uncompressed_stack++;
114 fs_visitor::pop_force_uncompressed()
116 force_uncompressed_stack--;
117 assert(force_uncompressed_stack >= 0);
121 fs_visitor::push_force_sechalf()
123 force_sechalf_stack++;
127 fs_visitor::pop_force_sechalf()
129 force_sechalf_stack--;
130 assert(force_sechalf_stack >= 0);
134 * Returns how many MRFs an FS opcode will write over.
136 * Note that this is not the 0 or 1 implied writes in an actual gen
137 * instruction -- the FS opcodes often generate MOVs in addition.
140 fs_visitor::implied_mrf_writes(fs_inst *inst)
145 switch (inst->opcode) {
146 case SHADER_OPCODE_RCP:
147 case SHADER_OPCODE_RSQ:
148 case SHADER_OPCODE_SQRT:
149 case SHADER_OPCODE_EXP2:
150 case SHADER_OPCODE_LOG2:
151 case SHADER_OPCODE_SIN:
152 case SHADER_OPCODE_COS:
153 return 1 * c->dispatch_width / 8;
154 case SHADER_OPCODE_POW:
155 case SHADER_OPCODE_INT_QUOTIENT:
156 case SHADER_OPCODE_INT_REMAINDER:
157 return 2 * c->dispatch_width / 8;
158 case SHADER_OPCODE_TEX:
160 case SHADER_OPCODE_TXD:
161 case SHADER_OPCODE_TXF:
162 case SHADER_OPCODE_TXL:
163 case SHADER_OPCODE_TXS:
165 case FS_OPCODE_FB_WRITE:
167 case FS_OPCODE_PULL_CONSTANT_LOAD:
168 case FS_OPCODE_UNSPILL:
170 case FS_OPCODE_SPILL:
173 assert(!"not reached");
179 fs_visitor::virtual_grf_alloc(int size)
181 if (virtual_grf_array_size <= virtual_grf_next) {
182 if (virtual_grf_array_size == 0)
183 virtual_grf_array_size = 16;
185 virtual_grf_array_size *= 2;
186 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
187 virtual_grf_array_size);
189 virtual_grf_sizes[virtual_grf_next] = size;
190 return virtual_grf_next++;
193 /** Fixed HW reg constructor. */
194 fs_reg::fs_reg(enum register_file file, int reg)
199 this->type = BRW_REGISTER_TYPE_F;
202 /** Fixed HW reg constructor. */
203 fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
211 /** Automatic reg constructor. */
212 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
217 this->reg = v->virtual_grf_alloc(v->type_size(type));
218 this->reg_offset = 0;
219 this->type = brw_type_for_base_type(type);
223 fs_visitor::variable_storage(ir_variable *var)
225 return (fs_reg *)hash_table_find(this->variable_ht, var);
229 import_uniforms_callback(const void *key,
233 struct hash_table *dst_ht = (struct hash_table *)closure;
234 const fs_reg *reg = (const fs_reg *)data;
236 if (reg->file != UNIFORM)
239 hash_table_insert(dst_ht, data, key);
242 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
243 * This brings in those uniform definitions
246 fs_visitor::import_uniforms(fs_visitor *v)
248 hash_table_call_foreach(v->variable_ht,
249 import_uniforms_callback,
251 this->params_remap = v->params_remap;
254 /* Our support for uniforms is piggy-backed on the struct
255 * gl_fragment_program, because that's where the values actually
256 * get stored, rather than in some global gl_shader_program uniform
260 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
262 unsigned int offset = 0;
264 if (type->is_matrix()) {
265 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
266 type->vector_elements,
269 for (unsigned int i = 0; i < type->matrix_columns; i++) {
270 offset += setup_uniform_values(loc + offset, column);
276 switch (type->base_type) {
277 case GLSL_TYPE_FLOAT:
281 for (unsigned int i = 0; i < type->vector_elements; i++) {
282 unsigned int param = c->prog_data.nr_params++;
284 assert(param < ARRAY_SIZE(c->prog_data.param));
286 if (ctx->Const.NativeIntegers) {
287 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
289 switch (type->base_type) {
290 case GLSL_TYPE_FLOAT:
291 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
294 c->prog_data.param_convert[param] = PARAM_CONVERT_F2U;
297 c->prog_data.param_convert[param] = PARAM_CONVERT_F2I;
300 c->prog_data.param_convert[param] = PARAM_CONVERT_F2B;
303 assert(!"not reached");
304 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
308 this->param_index[param] = loc;
309 this->param_offset[param] = i;
313 case GLSL_TYPE_STRUCT:
314 for (unsigned int i = 0; i < type->length; i++) {
315 offset += setup_uniform_values(loc + offset,
316 type->fields.structure[i].type);
320 case GLSL_TYPE_ARRAY:
321 for (unsigned int i = 0; i < type->length; i++) {
322 offset += setup_uniform_values(loc + offset, type->fields.array);
326 case GLSL_TYPE_SAMPLER:
327 /* The sampler takes up a slot, but we don't use any values from it. */
331 assert(!"not reached");
337 /* Our support for builtin uniforms is even scarier than non-builtin.
338 * It sits on top of the PROG_STATE_VAR parameters that are
339 * automatically updated from GL context state.
342 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
344 const ir_state_slot *const slots = ir->state_slots;
345 assert(ir->state_slots != NULL);
347 for (unsigned int i = 0; i < ir->num_state_slots; i++) {
348 /* This state reference has already been setup by ir_to_mesa, but we'll
349 * get the same index back here.
351 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
352 (gl_state_index *)slots[i].tokens);
354 /* Add each of the unique swizzles of the element as a parameter.
355 * This'll end up matching the expected layout of the
356 * array/matrix/structure we're trying to fill in.
359 for (unsigned int j = 0; j < 4; j++) {
360 int swiz = GET_SWZ(slots[i].swizzle, j);
361 if (swiz == last_swiz)
365 c->prog_data.param_convert[c->prog_data.nr_params] =
367 this->param_index[c->prog_data.nr_params] = index;
368 this->param_offset[c->prog_data.nr_params] = swiz;
369 c->prog_data.nr_params++;
375 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
377 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
379 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
382 if (ir->pixel_center_integer) {
383 emit(BRW_OPCODE_MOV, wpos, this->pixel_x);
385 emit(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f));
390 if (!flip && ir->pixel_center_integer) {
391 emit(BRW_OPCODE_MOV, wpos, this->pixel_y);
393 fs_reg pixel_y = this->pixel_y;
394 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
397 pixel_y.negate = true;
398 offset += c->key.drawable_height - 1.0;
401 emit(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset));
406 if (intel->gen >= 6) {
407 emit(BRW_OPCODE_MOV, wpos,
408 fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
410 emit(FS_OPCODE_LINTERP, wpos,
411 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
412 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
413 interp_reg(FRAG_ATTRIB_WPOS, 2));
417 /* gl_FragCoord.w: Already set up in emit_interpolation */
418 emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
424 fs_visitor::emit_general_interpolation(ir_variable *ir)
426 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
427 reg->type = brw_type_for_base_type(ir->type->get_scalar_type());
430 unsigned int array_elements;
431 const glsl_type *type;
433 if (ir->type->is_array()) {
434 array_elements = ir->type->length;
435 if (array_elements == 0) {
436 fail("dereferenced array '%s' has length 0\n", ir->name);
438 type = ir->type->fields.array;
444 glsl_interp_qualifier interpolation_mode =
445 ir->determine_interpolation_mode(c->key.flat_shade);
447 int location = ir->location;
448 for (unsigned int i = 0; i < array_elements; i++) {
449 for (unsigned int j = 0; j < type->matrix_columns; j++) {
450 if (urb_setup[location] == -1) {
451 /* If there's no incoming setup data for this slot, don't
452 * emit interpolation for it.
454 attr.reg_offset += type->vector_elements;
459 if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
460 /* Constant interpolation (flat shading) case. The SF has
461 * handed us defined values in only the constant offset
462 * field of the setup reg.
464 for (unsigned int k = 0; k < type->vector_elements; k++) {
465 struct brw_reg interp = interp_reg(location, k);
466 interp = suboffset(interp, 3);
467 interp.type = reg->type;
468 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
472 /* Smooth/noperspective interpolation case. */
473 for (unsigned int k = 0; k < type->vector_elements; k++) {
474 /* FINISHME: At some point we probably want to push
475 * this farther by giving similar treatment to the
476 * other potentially constant components of the
477 * attribute, as well as making brw_vs_constval.c
478 * handle varyings other than gl_TexCoord.
480 if (location >= FRAG_ATTRIB_TEX0 &&
481 location <= FRAG_ATTRIB_TEX7 &&
482 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) {
483 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
485 struct brw_reg interp = interp_reg(location, k);
486 brw_wm_barycentric_interp_mode barycoord_mode;
487 if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
488 barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
490 barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
491 emit(FS_OPCODE_LINTERP, attr,
492 this->delta_x[barycoord_mode],
493 this->delta_y[barycoord_mode], fs_reg(interp));
498 if (intel->gen < 6) {
499 attr.reg_offset -= type->vector_elements;
500 for (unsigned int k = 0; k < type->vector_elements; k++) {
501 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
514 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
516 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
518 /* The frontfacing comes in as a bit in the thread payload. */
519 if (intel->gen >= 6) {
520 emit(BRW_OPCODE_ASR, *reg,
521 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
523 emit(BRW_OPCODE_NOT, *reg, *reg);
524 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
526 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
527 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
530 fs_inst *inst = emit(BRW_OPCODE_CMP, *reg,
533 inst->conditional_mod = BRW_CONDITIONAL_L;
534 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
541 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
544 case SHADER_OPCODE_RCP:
545 case SHADER_OPCODE_RSQ:
546 case SHADER_OPCODE_SQRT:
547 case SHADER_OPCODE_EXP2:
548 case SHADER_OPCODE_LOG2:
549 case SHADER_OPCODE_SIN:
550 case SHADER_OPCODE_COS:
553 assert(!"not reached: bad math opcode");
557 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
558 * might be able to do better by doing execsize = 1 math and then
559 * expanding that result out, but we would need to be careful with
562 * Gen 6 hardware ignores source modifiers (negate and abs) on math
563 * instructions, so we also move to a temp to set those up.
565 if (intel->gen == 6 && (src.file == UNIFORM ||
568 fs_reg expanded = fs_reg(this, glsl_type::float_type);
569 emit(BRW_OPCODE_MOV, expanded, src);
573 fs_inst *inst = emit(opcode, dst, src);
575 if (intel->gen < 6) {
577 inst->mlen = c->dispatch_width / 8;
584 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
590 case SHADER_OPCODE_POW:
591 case SHADER_OPCODE_INT_QUOTIENT:
592 case SHADER_OPCODE_INT_REMAINDER:
595 assert(!"not reached: unsupported binary math opcode.");
599 if (intel->gen >= 7) {
600 inst = emit(opcode, dst, src0, src1);
601 } else if (intel->gen == 6) {
602 /* Can't do hstride == 0 args to gen6 math, so expand it out.
604 * The hardware ignores source modifiers (negate and abs) on math
605 * instructions, so we also move to a temp to set those up.
607 if (src0.file == UNIFORM || src0.abs || src0.negate) {
608 fs_reg expanded = fs_reg(this, glsl_type::float_type);
609 expanded.type = src0.type;
610 emit(BRW_OPCODE_MOV, expanded, src0);
614 if (src1.file == UNIFORM || src1.abs || src1.negate) {
615 fs_reg expanded = fs_reg(this, glsl_type::float_type);
616 expanded.type = src1.type;
617 emit(BRW_OPCODE_MOV, expanded, src1);
621 inst = emit(opcode, dst, src0, src1);
623 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
626 * "Operand0[7]. For the INT DIV functions, this operand is the
629 * "Operand1[7]. For the INT DIV functions, this operand is the
632 bool is_int_div = opcode != SHADER_OPCODE_POW;
633 fs_reg &op0 = is_int_div ? src1 : src0;
634 fs_reg &op1 = is_int_div ? src0 : src1;
636 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1, op1.type), op1);
637 inst = emit(opcode, dst, op0, reg_null_f);
639 inst->base_mrf = base_mrf;
640 inst->mlen = 2 * c->dispatch_width / 8;
646 * To be called after the last _mesa_add_state_reference() call, to
647 * set up prog_data.param[] for assign_curb_setup() and
648 * setup_pull_constants().
651 fs_visitor::setup_paramvalues_refs()
653 if (c->dispatch_width != 8)
656 /* Set up the pointers to ParamValues now that that array is finalized. */
657 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
658 c->prog_data.param[i] =
659 (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] +
660 this->param_offset[i];
665 fs_visitor::assign_curb_setup()
667 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
668 if (c->dispatch_width == 8) {
669 c->prog_data.first_curbe_grf = c->nr_payload_regs;
671 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
674 /* Map the offsets in the UNIFORM file to fixed HW regs. */
675 foreach_list(node, &this->instructions) {
676 fs_inst *inst = (fs_inst *)node;
678 for (unsigned int i = 0; i < 3; i++) {
679 if (inst->src[i].file == UNIFORM) {
680 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
681 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
685 inst->src[i].file = FIXED_HW_REG;
686 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
693 fs_visitor::calculate_urb_setup()
695 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
700 /* Figure out where each of the incoming setup attributes lands. */
701 if (intel->gen >= 6) {
702 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
703 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
704 urb_setup[i] = urb_next++;
708 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
709 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
710 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
711 int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
714 urb_setup[fp_index] = urb_next++;
719 /* Each attribute is 4 setup channels, each of which is half a reg. */
720 c->prog_data.urb_read_length = urb_next * 2;
724 fs_visitor::assign_urb_setup()
726 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
728 /* Offset all the urb_setup[] index by the actual position of the
729 * setup regs, now that the location of the constants has been chosen.
731 foreach_list(node, &this->instructions) {
732 fs_inst *inst = (fs_inst *)node;
734 if (inst->opcode == FS_OPCODE_LINTERP) {
735 assert(inst->src[2].file == FIXED_HW_REG);
736 inst->src[2].fixed_hw_reg.nr += urb_start;
739 if (inst->opcode == FS_OPCODE_CINTERP) {
740 assert(inst->src[0].file == FIXED_HW_REG);
741 inst->src[0].fixed_hw_reg.nr += urb_start;
745 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
749 * Split large virtual GRFs into separate components if we can.
751 * This is mostly duplicated with what brw_fs_vector_splitting does,
752 * but that's really conservative because it's afraid of doing
753 * splitting that doesn't result in real progress after the rest of
754 * the optimization phases, which would cause infinite looping in
755 * optimization. We can do it once here, safely. This also has the
756 * opportunity to split interpolated values, or maybe even uniforms,
757 * which we don't have at the IR level.
759 * We want to split, because virtual GRFs are what we register
760 * allocate and spill (due to contiguousness requirements for some
761 * instructions), and they're what we naturally generate in the
762 * codegen process, but most virtual GRFs don't actually need to be
763 * contiguous sets of GRFs. If we split, we'll end up with reduced
764 * live intervals and better dead code elimination and coalescing.
767 fs_visitor::split_virtual_grfs()
769 int num_vars = this->virtual_grf_next;
770 bool split_grf[num_vars];
771 int new_virtual_grf[num_vars];
773 /* Try to split anything > 0 sized. */
774 for (int i = 0; i < num_vars; i++) {
775 if (this->virtual_grf_sizes[i] != 1)
778 split_grf[i] = false;
782 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF) {
783 /* PLN opcodes rely on the delta_xy being contiguous. We only have to
784 * check this for BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because prior to
785 * Gen6, that was the only supported interpolation mode, and since Gen6,
786 * delta_x and delta_y are in fixed hardware registers.
788 split_grf[this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg] =
792 foreach_list(node, &this->instructions) {
793 fs_inst *inst = (fs_inst *)node;
795 /* Texturing produces 4 contiguous registers, so no splitting. */
796 if (inst->is_tex()) {
797 split_grf[inst->dst.reg] = false;
801 /* Allocate new space for split regs. Note that the virtual
802 * numbers will be contiguous.
804 for (int i = 0; i < num_vars; i++) {
806 new_virtual_grf[i] = virtual_grf_alloc(1);
807 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
808 int reg = virtual_grf_alloc(1);
809 assert(reg == new_virtual_grf[i] + j - 1);
812 this->virtual_grf_sizes[i] = 1;
816 foreach_list(node, &this->instructions) {
817 fs_inst *inst = (fs_inst *)node;
819 if (inst->dst.file == GRF &&
820 split_grf[inst->dst.reg] &&
821 inst->dst.reg_offset != 0) {
822 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
823 inst->dst.reg_offset - 1);
824 inst->dst.reg_offset = 0;
826 for (int i = 0; i < 3; i++) {
827 if (inst->src[i].file == GRF &&
828 split_grf[inst->src[i].reg] &&
829 inst->src[i].reg_offset != 0) {
830 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
831 inst->src[i].reg_offset - 1);
832 inst->src[i].reg_offset = 0;
836 this->live_intervals_valid = false;
840 fs_visitor::remove_dead_constants()
842 if (c->dispatch_width == 8) {
843 this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
845 for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
846 this->params_remap[i] = -1;
848 /* Find which params are still in use. */
849 foreach_list(node, &this->instructions) {
850 fs_inst *inst = (fs_inst *)node;
852 for (int i = 0; i < 3; i++) {
853 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
855 if (inst->src[i].file != UNIFORM)
858 assert(constant_nr < (int)c->prog_data.nr_params);
860 /* For now, set this to non-negative. We'll give it the
861 * actual new number in a moment, in order to keep the
862 * register numbers nicely ordered.
864 this->params_remap[constant_nr] = 0;
868 /* Figure out what the new numbers for the params will be. At some
869 * point when we're doing uniform array access, we're going to want
870 * to keep the distinction between .reg and .reg_offset, but for
873 unsigned int new_nr_params = 0;
874 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
875 if (this->params_remap[i] != -1) {
876 this->params_remap[i] = new_nr_params++;
880 /* Update the list of params to be uploaded to match our new numbering. */
881 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
882 int remapped = this->params_remap[i];
887 /* We've already done setup_paramvalues_refs() so no need to worry
888 * about param_index and param_offset.
890 c->prog_data.param[remapped] = c->prog_data.param[i];
891 c->prog_data.param_convert[remapped] = c->prog_data.param_convert[i];
894 c->prog_data.nr_params = new_nr_params;
896 /* This should have been generated in the 8-wide pass already. */
897 assert(this->params_remap);
900 /* Now do the renumbering of the shader to remove unused params. */
901 foreach_list(node, &this->instructions) {
902 fs_inst *inst = (fs_inst *)node;
904 for (int i = 0; i < 3; i++) {
905 int constant_nr = inst->src[i].reg + inst->src[i].reg_offset;
907 if (inst->src[i].file != UNIFORM)
910 assert(this->params_remap[constant_nr] != -1);
911 inst->src[i].reg = this->params_remap[constant_nr];
912 inst->src[i].reg_offset = 0;
920 * Choose accesses from the UNIFORM file to demote to using the pull
923 * We allow a fragment shader to have more than the specified minimum
924 * maximum number of fragment shader uniform components (64). If
925 * there are too many of these, they'd fill up all of register space.
926 * So, this will push some of them out to the pull constant buffer and
927 * update the program to load them.
930 fs_visitor::setup_pull_constants()
932 /* Only allow 16 registers (128 uniform components) as push constants. */
933 unsigned int max_uniform_components = 16 * 8;
934 if (c->prog_data.nr_params <= max_uniform_components)
937 if (c->dispatch_width == 16) {
938 fail("Pull constants not supported in 16-wide\n");
942 /* Just demote the end of the list. We could probably do better
943 * here, demoting things that are rarely used in the program first.
945 int pull_uniform_base = max_uniform_components;
946 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base;
948 foreach_list(node, &this->instructions) {
949 fs_inst *inst = (fs_inst *)node;
951 for (int i = 0; i < 3; i++) {
952 if (inst->src[i].file != UNIFORM)
955 int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset;
956 if (uniform_nr < pull_uniform_base)
959 fs_reg dst = fs_reg(this, glsl_type::float_type);
960 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD,
962 pull->offset = ((uniform_nr - pull_uniform_base) * 4) & ~15;
964 pull->annotation = inst->annotation;
968 inst->insert_before(pull);
970 inst->src[i].file = GRF;
971 inst->src[i].reg = dst.reg;
972 inst->src[i].reg_offset = 0;
973 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3;
977 for (int i = 0; i < pull_uniform_count; i++) {
978 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i];
979 c->prog_data.pull_param_convert[i] =
980 c->prog_data.param_convert[pull_uniform_base + i];
982 c->prog_data.nr_params -= pull_uniform_count;
983 c->prog_data.nr_pull_params = pull_uniform_count;
987 fs_visitor::calculate_live_intervals()
989 int num_vars = this->virtual_grf_next;
990 int *def = ralloc_array(mem_ctx, int, num_vars);
991 int *use = ralloc_array(mem_ctx, int, num_vars);
995 if (this->live_intervals_valid)
998 for (int i = 0; i < num_vars; i++) {
999 def[i] = MAX_INSTRUCTION;
1004 foreach_list(node, &this->instructions) {
1005 fs_inst *inst = (fs_inst *)node;
1007 if (inst->opcode == BRW_OPCODE_DO) {
1008 if (loop_depth++ == 0)
1010 } else if (inst->opcode == BRW_OPCODE_WHILE) {
1013 if (loop_depth == 0) {
1014 /* Patches up the use of vars marked for being live across
1017 for (int i = 0; i < num_vars; i++) {
1018 if (use[i] == loop_start) {
1024 for (unsigned int i = 0; i < 3; i++) {
1025 if (inst->src[i].file == GRF) {
1026 int reg = inst->src[i].reg;
1031 def[reg] = MIN2(loop_start, def[reg]);
1032 use[reg] = loop_start;
1034 /* Nobody else is going to go smash our start to
1035 * later in the loop now, because def[reg] now
1036 * points before the bb header.
1041 if (inst->dst.file == GRF) {
1042 int reg = inst->dst.reg;
1045 def[reg] = MIN2(def[reg], ip);
1047 def[reg] = MIN2(def[reg], loop_start);
1055 ralloc_free(this->virtual_grf_def);
1056 ralloc_free(this->virtual_grf_use);
1057 this->virtual_grf_def = def;
1058 this->virtual_grf_use = use;
1060 this->live_intervals_valid = true;
1064 * Attempts to move immediate constants into the immediate
1065 * constant slot of following instructions.
1067 * Immediate constants are a bit tricky -- they have to be in the last
1068 * operand slot, you can't do abs/negate on them,
1072 fs_visitor::propagate_constants()
1074 bool progress = false;
1076 calculate_live_intervals();
1078 foreach_list(node, &this->instructions) {
1079 fs_inst *inst = (fs_inst *)node;
1081 if (inst->opcode != BRW_OPCODE_MOV ||
1083 inst->dst.file != GRF || inst->src[0].file != IMM ||
1084 inst->dst.type != inst->src[0].type ||
1085 (c->dispatch_width == 16 &&
1086 (inst->force_uncompressed || inst->force_sechalf)))
1089 /* Don't bother with cases where we should have had the
1090 * operation on the constant folded in GLSL already.
1095 /* Found a move of a constant to a GRF. Find anything else using the GRF
1096 * before it's written, and replace it with the constant if we can.
1098 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1099 !scan_inst->is_tail_sentinel();
1100 scan_inst = (fs_inst *)scan_inst->next) {
1101 if (scan_inst->opcode == BRW_OPCODE_DO ||
1102 scan_inst->opcode == BRW_OPCODE_WHILE ||
1103 scan_inst->opcode == BRW_OPCODE_ELSE ||
1104 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1108 for (int i = 2; i >= 0; i--) {
1109 if (scan_inst->src[i].file != GRF ||
1110 scan_inst->src[i].reg != inst->dst.reg ||
1111 scan_inst->src[i].reg_offset != inst->dst.reg_offset)
1114 /* Don't bother with cases where we should have had the
1115 * operation on the constant folded in GLSL already.
1117 if (scan_inst->src[i].negate || scan_inst->src[i].abs)
1120 switch (scan_inst->opcode) {
1121 case BRW_OPCODE_MOV:
1122 scan_inst->src[i] = inst->src[0];
1126 case BRW_OPCODE_MUL:
1127 case BRW_OPCODE_ADD:
1129 scan_inst->src[i] = inst->src[0];
1131 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1132 /* Fit this constant in by commuting the operands.
1133 * Exception: we can't do this for 32-bit integer MUL
1134 * because it's asymmetric.
1136 if (scan_inst->opcode == BRW_OPCODE_MUL &&
1137 (scan_inst->src[1].type == BRW_REGISTER_TYPE_D ||
1138 scan_inst->src[1].type == BRW_REGISTER_TYPE_UD))
1140 scan_inst->src[0] = scan_inst->src[1];
1141 scan_inst->src[1] = inst->src[0];
1146 case BRW_OPCODE_CMP:
1148 scan_inst->src[i] = inst->src[0];
1150 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1153 new_cmod = brw_swap_cmod(scan_inst->conditional_mod);
1154 if (new_cmod != ~0u) {
1155 /* Fit this constant in by swapping the operands and
1158 scan_inst->src[0] = scan_inst->src[1];
1159 scan_inst->src[1] = inst->src[0];
1160 scan_inst->conditional_mod = new_cmod;
1166 case BRW_OPCODE_SEL:
1168 scan_inst->src[i] = inst->src[0];
1170 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1171 scan_inst->src[0] = scan_inst->src[1];
1172 scan_inst->src[1] = inst->src[0];
1174 /* If this was predicated, flipping operands means
1175 * we also need to flip the predicate.
1177 if (scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) {
1178 scan_inst->predicate_inverse =
1179 !scan_inst->predicate_inverse;
1185 case SHADER_OPCODE_RCP:
1186 /* The hardware doesn't do math on immediate values
1187 * (because why are you doing that, seriously?), but
1188 * the correct answer is to just constant fold it
1192 if (inst->src[0].imm.f != 0.0f) {
1193 scan_inst->opcode = BRW_OPCODE_MOV;
1194 scan_inst->src[0] = inst->src[0];
1195 scan_inst->src[0].imm.f = 1.0f / scan_inst->src[0].imm.f;
1205 if (scan_inst->dst.file == GRF &&
1206 scan_inst->dst.reg == inst->dst.reg &&
1207 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1208 scan_inst->is_tex())) {
1215 this->live_intervals_valid = false;
1222 * Attempts to move immediate constants into the immediate
1223 * constant slot of following instructions.
1225 * Immediate constants are a bit tricky -- they have to be in the last
1226 * operand slot, you can't do abs/negate on them,
1230 fs_visitor::opt_algebraic()
1232 bool progress = false;
1234 calculate_live_intervals();
1236 foreach_list(node, &this->instructions) {
1237 fs_inst *inst = (fs_inst *)node;
1239 switch (inst->opcode) {
1240 case BRW_OPCODE_MUL:
1241 if (inst->src[1].file != IMM)
1245 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1246 inst->src[1].imm.f == 1.0) {
1247 inst->opcode = BRW_OPCODE_MOV;
1248 inst->src[1] = reg_undef;
1263 * Must be called after calculate_live_intervales() to remove unused
1264 * writes to registers -- register allocation will fail otherwise
1265 * because something deffed but not used won't be considered to
1266 * interfere with other regs.
1269 fs_visitor::dead_code_eliminate()
1271 bool progress = false;
1274 calculate_live_intervals();
1276 foreach_list_safe(node, &this->instructions) {
1277 fs_inst *inst = (fs_inst *)node;
1279 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
1288 live_intervals_valid = false;
1294 fs_visitor::register_coalesce()
1296 bool progress = false;
1300 foreach_list_safe(node, &this->instructions) {
1301 fs_inst *inst = (fs_inst *)node;
1303 /* Make sure that we dominate the instructions we're going to
1304 * scan for interfering with our coalescing, or we won't have
1305 * scanned enough to see if anything interferes with our
1306 * coalescing. We don't dominate the following instructions if
1307 * we're in a loop or an if block.
1309 switch (inst->opcode) {
1313 case BRW_OPCODE_WHILE:
1319 case BRW_OPCODE_ENDIF:
1325 if (loop_depth || if_depth)
1328 if (inst->opcode != BRW_OPCODE_MOV ||
1331 inst->dst.file != GRF || (inst->src[0].file != GRF &&
1332 inst->src[0].file != UNIFORM)||
1333 inst->dst.type != inst->src[0].type)
1336 bool has_source_modifiers = inst->src[0].abs || inst->src[0].negate;
1338 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1339 * them: check for no writes to either one until the exit of the
1342 bool interfered = false;
1344 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1345 !scan_inst->is_tail_sentinel();
1346 scan_inst = (fs_inst *)scan_inst->next) {
1347 if (scan_inst->dst.file == GRF) {
1348 if (scan_inst->dst.reg == inst->dst.reg &&
1349 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1350 scan_inst->is_tex())) {
1354 if (inst->src[0].file == GRF &&
1355 scan_inst->dst.reg == inst->src[0].reg &&
1356 (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
1357 scan_inst->is_tex())) {
1363 /* The gen6 MATH instruction can't handle source modifiers or
1364 * unusual register regions, so avoid coalescing those for
1365 * now. We should do something more specific.
1367 if (intel->gen >= 6 &&
1368 scan_inst->is_math() &&
1369 (has_source_modifiers || inst->src[0].file == UNIFORM)) {
1374 /* The accumulator result appears to get used for the
1375 * conditional modifier generation. When negating a UD
1376 * value, there is a 33rd bit generated for the sign in the
1377 * accumulator value, so now you can't check, for example,
1378 * equality with a 32-bit value. See piglit fs-op-neg-uint.
1380 if (scan_inst->conditional_mod &&
1381 inst->src[0].negate &&
1382 inst->src[0].type == BRW_REGISTER_TYPE_UD) {
1391 /* Rewrite the later usage to point at the source of the move to
1394 for (fs_inst *scan_inst = inst;
1395 !scan_inst->is_tail_sentinel();
1396 scan_inst = (fs_inst *)scan_inst->next) {
1397 for (int i = 0; i < 3; i++) {
1398 if (scan_inst->src[i].file == GRF &&
1399 scan_inst->src[i].reg == inst->dst.reg &&
1400 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
1401 fs_reg new_src = inst->src[0];
1402 if (scan_inst->src[i].abs) {
1406 new_src.negate ^= scan_inst->src[i].negate;
1407 scan_inst->src[i] = new_src;
1417 live_intervals_valid = false;
1424 fs_visitor::compute_to_mrf()
1426 bool progress = false;
1429 calculate_live_intervals();
1431 foreach_list_safe(node, &this->instructions) {
1432 fs_inst *inst = (fs_inst *)node;
1437 if (inst->opcode != BRW_OPCODE_MOV ||
1439 inst->dst.file != MRF || inst->src[0].file != GRF ||
1440 inst->dst.type != inst->src[0].type ||
1441 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
1444 /* Work out which hardware MRF registers are written by this
1447 int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4;
1449 if (inst->dst.reg & BRW_MRF_COMPR4) {
1450 mrf_high = mrf_low + 4;
1451 } else if (c->dispatch_width == 16 &&
1452 (!inst->force_uncompressed && !inst->force_sechalf)) {
1453 mrf_high = mrf_low + 1;
1458 /* Can't compute-to-MRF this GRF if someone else was going to
1461 if (this->virtual_grf_use[inst->src[0].reg] > ip)
1464 /* Found a move of a GRF to a MRF. Let's see if we can go
1465 * rewrite the thing that made this GRF to write into the MRF.
1468 for (scan_inst = (fs_inst *)inst->prev;
1469 scan_inst->prev != NULL;
1470 scan_inst = (fs_inst *)scan_inst->prev) {
1471 if (scan_inst->dst.file == GRF &&
1472 scan_inst->dst.reg == inst->src[0].reg) {
1473 /* Found the last thing to write our reg we want to turn
1474 * into a compute-to-MRF.
1477 if (scan_inst->is_tex()) {
1478 /* texturing writes several continuous regs, so we can't
1479 * compute-to-mrf that.
1484 /* If it's predicated, it (probably) didn't populate all
1485 * the channels. We might be able to rewrite everything
1486 * that writes that reg, but it would require smarter
1487 * tracking to delay the rewriting until complete success.
1489 if (scan_inst->predicated)
1492 /* If it's half of register setup and not the same half as
1493 * our MOV we're trying to remove, bail for now.
1495 if (scan_inst->force_uncompressed != inst->force_uncompressed ||
1496 scan_inst->force_sechalf != inst->force_sechalf) {
1500 /* SEND instructions can't have MRF as a destination. */
1501 if (scan_inst->mlen)
1504 if (intel->gen >= 6) {
1505 /* gen6 math instructions must have the destination be
1506 * GRF, so no compute-to-MRF for them.
1508 if (scan_inst->is_math()) {
1513 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
1514 /* Found the creator of our MRF's source value. */
1515 scan_inst->dst.file = MRF;
1516 scan_inst->dst.reg = inst->dst.reg;
1517 scan_inst->saturate |= inst->saturate;
1524 /* We don't handle flow control here. Most computation of
1525 * values that end up in MRFs are shortly before the MRF
1528 if (scan_inst->opcode == BRW_OPCODE_DO ||
1529 scan_inst->opcode == BRW_OPCODE_WHILE ||
1530 scan_inst->opcode == BRW_OPCODE_ELSE ||
1531 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1535 /* You can't read from an MRF, so if someone else reads our
1536 * MRF's source GRF that we wanted to rewrite, that stops us.
1538 bool interfered = false;
1539 for (int i = 0; i < 3; i++) {
1540 if (scan_inst->src[i].file == GRF &&
1541 scan_inst->src[i].reg == inst->src[0].reg &&
1542 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
1549 if (scan_inst->dst.file == MRF) {
1550 /* If somebody else writes our MRF here, we can't
1551 * compute-to-MRF before that.
1553 int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4;
1556 if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
1557 scan_mrf_high = scan_mrf_low + 4;
1558 } else if (c->dispatch_width == 16 &&
1559 (!scan_inst->force_uncompressed &&
1560 !scan_inst->force_sechalf)) {
1561 scan_mrf_high = scan_mrf_low + 1;
1563 scan_mrf_high = scan_mrf_low;
1566 if (mrf_low == scan_mrf_low ||
1567 mrf_low == scan_mrf_high ||
1568 mrf_high == scan_mrf_low ||
1569 mrf_high == scan_mrf_high) {
1574 if (scan_inst->mlen > 0) {
1575 /* Found a SEND instruction, which means that there are
1576 * live values in MRFs from base_mrf to base_mrf +
1577 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1580 if (mrf_low >= scan_inst->base_mrf &&
1581 mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
1584 if (mrf_high >= scan_inst->base_mrf &&
1585 mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
1596 * Walks through basic blocks, locking for repeated MRF writes and
1597 * removing the later ones.
1600 fs_visitor::remove_duplicate_mrf_writes()
1602 fs_inst *last_mrf_move[16];
1603 bool progress = false;
1605 /* Need to update the MRF tracking for compressed instructions. */
1606 if (c->dispatch_width == 16)
1609 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1611 foreach_list_safe(node, &this->instructions) {
1612 fs_inst *inst = (fs_inst *)node;
1614 switch (inst->opcode) {
1616 case BRW_OPCODE_WHILE:
1618 case BRW_OPCODE_ELSE:
1619 case BRW_OPCODE_ENDIF:
1620 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1626 if (inst->opcode == BRW_OPCODE_MOV &&
1627 inst->dst.file == MRF) {
1628 fs_inst *prev_inst = last_mrf_move[inst->dst.reg];
1629 if (prev_inst && inst->equals(prev_inst)) {
1636 /* Clear out the last-write records for MRFs that were overwritten. */
1637 if (inst->dst.file == MRF) {
1638 last_mrf_move[inst->dst.reg] = NULL;
1641 if (inst->mlen > 0) {
1642 /* Found a SEND instruction, which will include two or fewer
1643 * implied MRF writes. We could do better here.
1645 for (int i = 0; i < implied_mrf_writes(inst); i++) {
1646 last_mrf_move[inst->base_mrf + i] = NULL;
1650 /* Clear out any MRF move records whose sources got overwritten. */
1651 if (inst->dst.file == GRF) {
1652 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
1653 if (last_mrf_move[i] &&
1654 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
1655 last_mrf_move[i] = NULL;
1660 if (inst->opcode == BRW_OPCODE_MOV &&
1661 inst->dst.file == MRF &&
1662 inst->src[0].file == GRF &&
1663 !inst->predicated) {
1664 last_mrf_move[inst->dst.reg] = inst;
1672 fs_visitor::virtual_grf_interferes(int a, int b)
1674 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
1675 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
1677 /* We can't handle dead register writes here, without iterating
1678 * over the whole instruction stream to find every single dead
1679 * write to that register to compare to the live interval of the
1680 * other register. Just assert that dead_code_eliminate() has been
1683 assert((this->virtual_grf_use[a] != -1 ||
1684 this->virtual_grf_def[a] == MAX_INSTRUCTION) &&
1685 (this->virtual_grf_use[b] != -1 ||
1686 this->virtual_grf_def[b] == MAX_INSTRUCTION));
1688 /* If the register is used to store 16 values of less than float
1689 * size (only the case for pixel_[xy]), then we can't allocate
1690 * another dword-sized thing to that register that would be used in
1691 * the same instruction. This is because when the GPU decodes (for
1694 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
1695 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
1697 * it's actually processed as:
1698 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
1699 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
1701 * so our second half values in g6 got overwritten in the first
1704 if (c->dispatch_width == 16 && (this->pixel_x.reg == a ||
1705 this->pixel_x.reg == b ||
1706 this->pixel_y.reg == a ||
1707 this->pixel_y.reg == b)) {
1708 return start <= end;
1717 uint32_t prog_offset_16 = 0;
1718 uint32_t orig_nr_params = c->prog_data.nr_params;
1720 brw_wm_payload_setup(brw, c);
1722 if (c->dispatch_width == 16) {
1723 /* align to 64 byte boundary. */
1724 while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
1728 /* Save off the start of this 16-wide program in case we succeed. */
1729 prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction);
1731 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1737 calculate_urb_setup();
1739 emit_interpolation_setup_gen4();
1741 emit_interpolation_setup_gen6();
1743 /* Generate FS IR for main(). (the visitor only descends into
1744 * functions called "main").
1746 foreach_list(node, &*shader->ir) {
1747 ir_instruction *ir = (ir_instruction *)node;
1749 this->result = reg_undef;
1757 split_virtual_grfs();
1759 setup_paramvalues_refs();
1760 setup_pull_constants();
1766 progress = remove_duplicate_mrf_writes() || progress;
1768 progress = propagate_constants() || progress;
1769 progress = opt_algebraic() || progress;
1770 progress = register_coalesce() || progress;
1771 progress = compute_to_mrf() || progress;
1772 progress = dead_code_eliminate() || progress;
1775 remove_dead_constants();
1777 schedule_instructions();
1779 assign_curb_setup();
1783 /* Debug of register spilling: Go spill everything. */
1784 int virtual_grf_count = virtual_grf_next;
1785 for (int i = 0; i < virtual_grf_count; i++) {
1791 assign_regs_trivial();
1793 while (!assign_regs()) {
1799 assert(force_uncompressed_stack == 0);
1800 assert(force_sechalf_stack == 0);
1807 if (c->dispatch_width == 8) {
1808 c->prog_data.reg_blocks = brw_register_blocks(grf_used);
1810 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
1811 c->prog_data.prog_offset_16 = prog_offset_16;
1813 /* Make sure we didn't try to sneak in an extra uniform */
1814 assert(orig_nr_params == c->prog_data.nr_params);
1815 (void) orig_nr_params;
1822 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
1823 struct gl_shader_program *prog)
1825 struct intel_context *intel = &brw->intel;
1830 struct brw_shader *shader =
1831 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
1835 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1836 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
1837 _mesa_print_ir(shader->ir, NULL);
1841 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1843 c->dispatch_width = 8;
1845 fs_visitor v(c, prog, shader);
1847 prog->LinkStatus = false;
1848 ralloc_strcat(&prog->InfoLog, v.fail_msg);
1853 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
1854 c->dispatch_width = 16;
1855 fs_visitor v2(c, prog, shader);
1856 v2.import_uniforms(&v);
1860 c->prog_data.dispatch_width = 8;
1866 brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
1868 struct brw_context *brw = brw_context(ctx);
1869 struct brw_wm_prog_key key;
1871 if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
1874 struct gl_fragment_program *fp = (struct gl_fragment_program *)
1875 prog->_LinkedShaders[MESA_SHADER_FRAGMENT]->Program;
1876 struct brw_fragment_program *bfp = brw_fragment_program(fp);
1878 memset(&key, 0, sizeof(key));
1881 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
1883 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
1884 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
1886 /* Just assume depth testing. */
1887 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
1888 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
1890 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
1891 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1892 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
1895 key.proj_attrib_mask |= 1 << i;
1897 int vp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
1900 key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
1903 key.clamp_fragment_color = true;
1905 for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1906 if (fp->Base.ShadowSamplers & (1 << i))
1907 key.compare_funcs[i] = GL_LESS;
1909 /* FINISHME: depth compares might use (0,0,0,W) for example */
1910 key.tex_swizzles[i] = SWIZZLE_XYZW;
1913 if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
1914 key.drawable_height = ctx->DrawBuffer->Height;
1915 key.render_to_fbo = ctx->DrawBuffer->Name != 0;
1918 key.nr_color_regions = 1;
1920 key.program_string_id = bfp->id;
1922 uint32_t old_prog_offset = brw->wm.prog_offset;
1923 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
1925 bool success = do_wm_prog(brw, prog, bfp, &key);
1927 brw->wm.prog_offset = old_prog_offset;
1928 brw->wm.prog_data = old_prog_data;