2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
31 #include "util/register_allocate.h"
36 assign_reg(unsigned *reg_hw_locations, fs_reg *reg)
38 if (reg->file == VGRF) {
39 reg->nr = reg_hw_locations[reg->nr] + reg->reg_offset;
45 fs_visitor::assign_regs_trivial()
47 unsigned hw_reg_mapping[this->alloc.count + 1];
49 int reg_width = dispatch_width / 8;
51 /* Note that compressed instructions require alignment to 2 registers. */
52 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
53 for (i = 1; i <= this->alloc.count; i++) {
54 hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
55 this->alloc.sizes[i - 1]);
57 this->grf_used = hw_reg_mapping[this->alloc.count];
59 foreach_block_and_inst(block, fs_inst, inst, cfg) {
60 assign_reg(hw_reg_mapping, &inst->dst);
61 for (i = 0; i < inst->sources; i++) {
62 assign_reg(hw_reg_mapping, &inst->src[i]);
66 if (this->grf_used >= max_grf) {
67 fail("Ran out of regs on trivial allocator (%d/%d)\n",
68 this->grf_used, max_grf);
70 this->alloc.count = this->grf_used;
76 brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
78 const struct brw_device_info *devinfo = compiler->devinfo;
79 int base_reg_count = BRW_MAX_GRF;
80 int index = (dispatch_width / 8) - 1;
82 if (dispatch_width > 8 && devinfo->gen >= 7) {
83 /* For IVB+, we don't need the PLN hacks or the even-reg alignment in
84 * SIMD16. Therefore, we can use the exact same register sets for
85 * SIMD16 as we do for SIMD8 and we don't need to recalculate them.
87 compiler->fs_reg_sets[index] = compiler->fs_reg_sets[0];
91 /* The registers used to make up almost all values handled in the compiler
92 * are a scalar value occupying a single register (or 2 registers in the
93 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
94 * multiplying allocated register numbers by 2). Things that were
95 * aggregates of scalar values at the GLSL level were split to scalar
96 * values by split_virtual_grfs().
98 * However, texture SEND messages return a series of contiguous registers
99 * to write into. We currently always ask for 4 registers, but we may
100 * convert that to use less some day.
102 * Additionally, on gen5 we need aligned pairs of registers for the PLN
103 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
106 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
107 * and we add in '3' to make indexing the array easier for the common case
108 * (since we'll probably want it for texturing later).
110 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
111 * means that we may need any size up to the sampler message size limit (11
115 int class_sizes[MAX_VGRF_SIZE];
117 if (devinfo->gen >= 7) {
118 for (class_count = 0; class_count < MAX_VGRF_SIZE; class_count++)
119 class_sizes[class_count] = class_count + 1;
121 for (class_count = 0; class_count < 4; class_count++)
122 class_sizes[class_count] = class_count + 1;
123 class_sizes[class_count++] = 8;
126 memset(compiler->fs_reg_sets[index].class_to_ra_reg_range, 0,
127 sizeof(compiler->fs_reg_sets[index].class_to_ra_reg_range));
128 int *class_to_ra_reg_range = compiler->fs_reg_sets[index].class_to_ra_reg_range;
130 /* Compute the total number of registers across all classes. */
131 int ra_reg_count = 0;
132 for (int i = 0; i < class_count; i++) {
133 if (devinfo->gen <= 5 && dispatch_width == 16) {
136 * In order to reduce the hardware complexity, the following
137 * rules and restrictions apply to the compressed instruction:
139 * * Operand Alignment Rule: With the exceptions listed below, a
140 * source/destination operand in general should be aligned to
141 * even 256-bit physical register with a region size equal to
142 * two 256-bit physical register
144 ra_reg_count += (base_reg_count - (class_sizes[i] - 1)) / 2;
146 ra_reg_count += base_reg_count - (class_sizes[i] - 1);
148 /* Mark the last register. We'll fill in the beginnings later. */
149 class_to_ra_reg_range[class_sizes[i]] = ra_reg_count;
152 /* Fill out the rest of the range markers */
153 for (int i = 1; i < 17; ++i) {
154 if (class_to_ra_reg_range[i] == 0)
155 class_to_ra_reg_range[i] = class_to_ra_reg_range[i-1];
158 uint8_t *ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count);
159 struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false);
160 if (devinfo->gen >= 6)
161 ra_set_allocate_round_robin(regs);
162 int *classes = ralloc_array(compiler, int, class_count);
163 int aligned_pairs_class = -1;
165 /* Allocate space for q values. We allocate class_count + 1 because we
166 * want to leave room for the aligned pairs class if we have it. */
167 unsigned int **q_values = ralloc_array(compiler, unsigned int *,
169 for (int i = 0; i < class_count + 1; ++i)
170 q_values[i] = ralloc_array(q_values, unsigned int, class_count + 1);
172 /* Now, add the registers to their classes, and add the conflicts
173 * between them and the base GRF registers (and also each other).
176 int pairs_base_reg = 0;
177 int pairs_reg_count = 0;
178 for (int i = 0; i < class_count; i++) {
180 if (devinfo->gen <= 5 && dispatch_width == 16) {
181 class_reg_count = (base_reg_count - (class_sizes[i] - 1)) / 2;
183 /* See comment below. The only difference here is that we are
184 * dealing with pairs of registers instead of single registers.
185 * Registers of odd sizes simply get rounded up. */
186 for (int j = 0; j < class_count; j++)
187 q_values[i][j] = (class_sizes[i] + 1) / 2 +
188 (class_sizes[j] + 1) / 2 - 1;
190 class_reg_count = base_reg_count - (class_sizes[i] - 1);
192 /* From register_allocate.c:
194 * q(B,C) (indexed by C, B is this register class) in
195 * Runeson/Nyström paper. This is "how many registers of B could
196 * the worst choice register from C conflict with".
198 * If we just let the register allocation algorithm compute these
199 * values, is extremely expensive. However, since all of our
200 * registers are laid out, we can very easily compute them
201 * ourselves. View the register from C as fixed starting at GRF n
202 * somwhere in the middle, and the register from B as sliding back
203 * and forth. Then the first register to conflict from B is the
204 * one starting at n - class_size[B] + 1 and the last register to
205 * conflict will start at n + class_size[B] - 1. Therefore, the
206 * number of conflicts from B is class_size[B] + class_size[C] - 1.
208 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
209 * B | | | | | |n| --> | | | | | | |
210 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
215 for (int j = 0; j < class_count; j++)
216 q_values[i][j] = class_sizes[i] + class_sizes[j] - 1;
218 classes[i] = ra_alloc_reg_class(regs);
220 /* Save this off for the aligned pair class at the end. */
221 if (class_sizes[i] == 2) {
222 pairs_base_reg = reg;
223 pairs_reg_count = class_reg_count;
226 if (devinfo->gen <= 5 && dispatch_width == 16) {
227 for (int j = 0; j < class_reg_count; j++) {
228 ra_class_add_reg(regs, classes[i], reg);
230 ra_reg_to_grf[reg] = j * 2;
232 for (int base_reg = j;
233 base_reg < j + (class_sizes[i] + 1) / 2;
235 ra_add_reg_conflict(regs, base_reg, reg);
241 for (int j = 0; j < class_reg_count; j++) {
242 ra_class_add_reg(regs, classes[i], reg);
244 ra_reg_to_grf[reg] = j;
246 for (int base_reg = j;
247 base_reg < j + class_sizes[i];
249 ra_add_reg_conflict(regs, base_reg, reg);
256 assert(reg == ra_reg_count);
258 /* Applying transitivity to all of the base registers gives us the
259 * appropreate register conflict relationships everywhere.
261 for (int reg = 0; reg < base_reg_count; reg++)
262 ra_make_reg_conflicts_transitive(regs, reg);
264 /* Add a special class for aligned pairs, which we'll put delta_xy
265 * in on Gen <= 6 so that we can do PLN.
267 if (devinfo->has_pln && dispatch_width == 8 && devinfo->gen <= 6) {
268 aligned_pairs_class = ra_alloc_reg_class(regs);
270 for (int i = 0; i < pairs_reg_count; i++) {
271 if ((ra_reg_to_grf[pairs_base_reg + i] & 1) == 0) {
272 ra_class_add_reg(regs, aligned_pairs_class, pairs_base_reg + i);
276 for (int i = 0; i < class_count; i++) {
277 /* These are a little counter-intuitive because the pair registers
278 * are required to be aligned while the register they are
279 * potentially interferring with are not. In the case where the
280 * size is even, the worst-case is that the register is
281 * odd-aligned. In the odd-size case, it doesn't matter.
283 q_values[class_count][i] = class_sizes[i] / 2 + 1;
284 q_values[i][class_count] = class_sizes[i] + 1;
286 q_values[class_count][class_count] = 1;
289 ra_set_finalize(regs, q_values);
291 ralloc_free(q_values);
293 compiler->fs_reg_sets[index].regs = regs;
294 for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++)
295 compiler->fs_reg_sets[index].classes[i] = -1;
296 for (int i = 0; i < class_count; i++)
297 compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i];
298 compiler->fs_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf;
299 compiler->fs_reg_sets[index].aligned_pairs_class = aligned_pairs_class;
303 brw_fs_alloc_reg_sets(struct brw_compiler *compiler)
305 brw_alloc_reg_set(compiler, 8);
306 brw_alloc_reg_set(compiler, 16);
310 count_to_loop_end(const bblock_t *block)
312 if (block->end()->opcode == BRW_OPCODE_WHILE)
313 return block->end_ip;
316 /* Skip the first block, since we don't want to count the do the calling
319 for (block = block->next();
321 block = block->next()) {
322 if (block->start()->opcode == BRW_OPCODE_DO)
324 if (block->end()->opcode == BRW_OPCODE_WHILE) {
327 return block->end_ip;
330 unreachable("not reached");
333 void fs_visitor::calculate_payload_ranges(int payload_node_count,
334 int *payload_last_use_ip)
339 for (int i = 0; i < payload_node_count; i++)
340 payload_last_use_ip[i] = -1;
343 foreach_block_and_inst(block, fs_inst, inst, cfg) {
344 switch (inst->opcode) {
348 /* Since payload regs are deffed only at the start of the shader
349 * execution, any uses of the payload within a loop mean the live
350 * interval extends to the end of the outermost loop. Find the ip of
354 loop_end_ip = count_to_loop_end(block);
356 case BRW_OPCODE_WHILE:
365 use_ip = loop_end_ip;
369 /* Note that UNIFORM args have been turned into FIXED_GRF by
370 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
371 * the start (see interp_reg()).
373 for (int i = 0; i < inst->sources; i++) {
374 if (inst->src[i].file == FIXED_GRF) {
375 int node_nr = inst->src[i].nr;
376 if (node_nr >= payload_node_count)
379 for (int j = 0; j < inst->regs_read(i); j++) {
380 payload_last_use_ip[node_nr + j] = use_ip;
381 assert(node_nr + j < payload_node_count);
386 /* Special case instructions which have extra implied registers used. */
387 switch (inst->opcode) {
388 case CS_OPCODE_CS_TERMINATE:
389 payload_last_use_ip[0] = use_ip;
394 /* We could omit this for the !inst->header_present case, except
395 * that the simulator apparently incorrectly reads from g0/g1
396 * instead of sideband. It also really freaks out driver
397 * developers to see g0 used in unusual places, so just always
400 payload_last_use_ip[0] = use_ip;
401 payload_last_use_ip[1] = use_ip;
412 * Sets up interference between thread payload registers and the virtual GRFs
413 * to be allocated for program temporaries.
415 * We want to be able to reallocate the payload for our virtual GRFs, notably
416 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
419 * The layout of the payload registers is:
421 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
422 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
423 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
425 * And we have payload_node_count nodes covering these registers in order
426 * (note that in SIMD16, a node is two registers).
429 fs_visitor::setup_payload_interference(struct ra_graph *g,
430 int payload_node_count,
431 int first_payload_node)
433 int payload_last_use_ip[payload_node_count];
434 calculate_payload_ranges(payload_node_count, payload_last_use_ip);
436 for (int i = 0; i < payload_node_count; i++) {
437 if (payload_last_use_ip[i] == -1)
440 /* Mark the payload node as interfering with any virtual grf that is
441 * live between the start of the program and our last use of the payload
444 for (unsigned j = 0; j < this->alloc.count; j++) {
445 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
446 * in order to not have to worry about the uniform issue described in
447 * calculate_live_intervals().
449 if (this->virtual_grf_start[j] <= payload_last_use_ip[i]) {
450 ra_add_node_interference(g, first_payload_node + i, j);
455 for (int i = 0; i < payload_node_count; i++) {
456 /* Mark each payload node as being allocated to its physical register.
458 * The alternative would be to have per-physical-register classes, which
459 * would just be silly.
461 if (devinfo->gen <= 5 && dispatch_width == 16) {
462 /* We have to divide by 2 here because we only have even numbered
463 * registers. Some of the payload registers will be odd, but
464 * that's ok because their physical register numbers have already
465 * been assigned. The only thing this is used for is interference.
467 ra_set_node_reg(g, first_payload_node + i, i / 2);
469 ra_set_node_reg(g, first_payload_node + i, i);
475 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
477 * This is used in assign_regs() to decide which of the GRFs that we use as
478 * MRFs on gen7 get normally register allocated, and in register spilling to
479 * see if we can actually use MRFs to do spills without overwriting normal MRF
483 get_used_mrfs(fs_visitor *v, bool *mrf_used)
485 int reg_width = v->dispatch_width / 8;
487 memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->gen) * sizeof(bool));
489 foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
490 if (inst->dst.file == MRF) {
491 int reg = inst->dst.nr & ~BRW_MRF_COMPR4;
492 mrf_used[reg] = true;
493 if (reg_width == 2) {
494 if (inst->dst.nr & BRW_MRF_COMPR4) {
495 mrf_used[reg + 4] = true;
497 mrf_used[reg + 1] = true;
502 if (inst->mlen > 0) {
503 for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
504 mrf_used[inst->base_mrf + i] = true;
511 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
512 * messages (treated as MRFs in code generation).
515 setup_mrf_hack_interference(fs_visitor *v, struct ra_graph *g,
516 int first_mrf_node, int *first_used_mrf)
518 bool mrf_used[BRW_MAX_MRF(v->devinfo->gen)];
519 get_used_mrfs(v, mrf_used);
521 *first_used_mrf = BRW_MAX_MRF(v->devinfo->gen);
522 for (int i = 0; i < BRW_MAX_MRF(v->devinfo->gen); i++) {
523 /* Mark each MRF reg node as being allocated to its physical register.
525 * The alternative would be to have per-physical-register classes, which
526 * would just be silly.
528 ra_set_node_reg(g, first_mrf_node + i, GEN7_MRF_HACK_START + i);
530 /* Since we don't have any live/dead analysis on the MRFs, just mark all
531 * that are used as conflicting with all virtual GRFs.
534 if (i < *first_used_mrf)
537 for (unsigned j = 0; j < v->alloc.count; j++) {
538 ra_add_node_interference(g, first_mrf_node + i, j);
545 fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
547 /* Most of this allocation was written for a reg_width of 1
548 * (dispatch_width == 8). In extending to SIMD16, the code was
549 * left in place and it was converted to have the hardware
550 * registers it's allocating be contiguous physical pairs of regs
551 * for reg_width == 2.
553 int reg_width = dispatch_width / 8;
554 unsigned hw_reg_mapping[this->alloc.count];
555 int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width);
556 int rsi = reg_width - 1; /* Which compiler->fs_reg_sets[] to use */
557 calculate_live_intervals();
559 int node_count = this->alloc.count;
560 int first_payload_node = node_count;
561 node_count += payload_node_count;
562 int first_mrf_hack_node = node_count;
563 if (devinfo->gen >= 7)
564 node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
566 ra_alloc_interference_graph(compiler->fs_reg_sets[rsi].regs, node_count);
568 for (unsigned i = 0; i < this->alloc.count; i++) {
569 unsigned size = this->alloc.sizes[i];
572 assert(size <= ARRAY_SIZE(compiler->fs_reg_sets[rsi].classes) &&
573 "Register allocation relies on split_virtual_grfs()");
574 c = compiler->fs_reg_sets[rsi].classes[size - 1];
576 /* Special case: on pre-GEN6 hardware that supports PLN, the
577 * second operand of a PLN instruction needs to be an
578 * even-numbered register, so we have a special register class
579 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
580 * uses this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
581 * second operand of a PLN instruction (since it doesn't support
582 * any other interpolation modes). So all we need to do is find
583 * that register and set it to the appropriate class.
585 if (compiler->fs_reg_sets[rsi].aligned_pairs_class >= 0 &&
586 this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == VGRF &&
587 this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].nr == i) {
588 c = compiler->fs_reg_sets[rsi].aligned_pairs_class;
591 ra_set_node_class(g, i, c);
593 for (unsigned j = 0; j < i; j++) {
594 if (virtual_grf_interferes(i, j)) {
595 ra_add_node_interference(g, i, j);
600 /* Certain instructions can't safely use the same register for their
601 * sources and destination. Add interference.
603 foreach_block_and_inst(block, fs_inst, inst, cfg) {
604 if (inst->dst.file == VGRF && inst->has_source_and_destination_hazard()) {
605 for (unsigned i = 0; i < 3; i++) {
606 if (inst->src[i].file == VGRF) {
607 ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr);
613 setup_payload_interference(g, payload_node_count, first_payload_node);
614 if (devinfo->gen >= 7) {
615 int first_used_mrf = BRW_MAX_MRF(devinfo->gen);
616 setup_mrf_hack_interference(this, g, first_mrf_hack_node,
619 foreach_block_and_inst(block, fs_inst, inst, cfg) {
620 /* When we do send-from-GRF for FB writes, we need to ensure that
621 * the last write instruction sends from a high register. This is
622 * because the vertex fetcher wants to start filling the low
623 * payload registers while the pixel data port is still working on
624 * writing out the memory. If we don't do this, we get rendering
627 * We could just do "something high". Instead, we just pick the
628 * highest register that works.
631 int size = alloc.sizes[inst->src[0].nr];
632 int reg = compiler->fs_reg_sets[rsi].class_to_ra_reg_range[size] - 1;
634 /* If something happened to spill, we want to push the EOT send
635 * register early enough in the register file that we don't
636 * conflict with any used MRF hack registers.
638 reg -= BRW_MAX_MRF(devinfo->gen) - first_used_mrf;
640 ra_set_node_reg(g, inst->src[0].nr, reg);
646 if (dispatch_width > 8) {
647 /* In 16-wide dispatch we have an issue where a compressed
648 * instruction is actually two instructions executed simultaneiously.
649 * It's actually ok to have the source and destination registers be
650 * the same. In this case, each instruction over-writes its own
651 * source and there's no problem. The real problem here is if the
652 * source and destination registers are off by one. Then you can end
653 * up in a scenario where the first instruction over-writes the
654 * source of the second instruction. Since the compiler doesn't know
655 * about this level of granularity, we simply make the source and
656 * destination interfere.
658 foreach_block_and_inst(block, fs_inst, inst, cfg) {
659 if (inst->dst.file != VGRF)
662 for (int i = 0; i < inst->sources; ++i) {
663 if (inst->src[i].file == VGRF) {
664 ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr);
670 /* Debug of register spilling: Go spill everything. */
671 if (unlikely(spill_all)) {
672 int reg = choose_spill_reg(g);
681 if (!ra_allocate(g)) {
682 /* Failed to allocate registers. Spill a reg, and the caller will
683 * loop back into here to try again.
685 int reg = choose_spill_reg(g);
688 fail("no register to spill:\n");
689 dump_instructions(NULL);
690 } else if (allow_spilling) {
699 /* Get the chosen virtual registers for each node, and map virtual
700 * regs in the register classes back down to real hardware reg
703 this->grf_used = payload_node_count;
704 for (unsigned i = 0; i < this->alloc.count; i++) {
705 int reg = ra_get_node_reg(g, i);
707 hw_reg_mapping[i] = compiler->fs_reg_sets[rsi].ra_reg_to_grf[reg];
708 this->grf_used = MAX2(this->grf_used,
709 hw_reg_mapping[i] + this->alloc.sizes[i]);
712 foreach_block_and_inst(block, fs_inst, inst, cfg) {
713 assign_reg(hw_reg_mapping, &inst->dst);
714 for (int i = 0; i < inst->sources; i++) {
715 assign_reg(hw_reg_mapping, &inst->src[i]);
719 this->alloc.count = this->grf_used;
728 * Maximum spill block size we expect to encounter in 32B units.
730 * This is somewhat arbitrary and doesn't necessarily limit the maximum
731 * variable size that can be spilled -- A higher value will allow a
732 * variable of a given size to be spilled more efficiently with a smaller
733 * number of scratch messages, but will increase the likelihood of a
734 * collision between the MRFs reserved for spilling and other MRFs used by
735 * the program (and possibly increase GRF register pressure on platforms
736 * without hardware MRFs), what could cause register allocation to fail.
738 * For the moment reserve just enough space so a register of 32 bit
739 * component type and natural region width can be spilled without splitting
740 * into multiple (force_writemask_all) scratch messages.
743 spill_max_size(const backend_shader *s)
745 /* FINISHME - On Gen7+ it should be possible to avoid this limit
746 * altogether by spilling directly from the temporary GRF
747 * allocated to hold the result of the instruction (and the
748 * scratch write header).
750 /* FINISHME - The shader's dispatch width probably belongs in
751 * backend_shader (or some nonexistent fs_shader class?)
752 * rather than in the visitor class.
754 return static_cast<const fs_visitor *>(s)->dispatch_width / 8;
758 * First MRF register available for spilling.
761 spill_base_mrf(const backend_shader *s)
763 return BRW_MAX_MRF(s->devinfo->gen) - spill_max_size(s) - 1;
768 emit_unspill(const fs_builder &bld, fs_reg dst,
769 uint32_t spill_offset, unsigned count)
771 const brw_device_info *devinfo = bld.shader->devinfo;
772 const unsigned reg_size = dst.component_size(bld.dispatch_width()) /
774 assert(count % reg_size == 0);
776 for (unsigned i = 0; i < count / reg_size; i++) {
777 /* The Gen7 descriptor-based offset is 12 bits of HWORD units. Because
778 * the Gen7-style scratch block read is hardwired to BTI 255, on Gen9+
779 * it would cause the DC to do an IA-coherent read, what largely
780 * outweighs the slight advantage from not having to provide the address
781 * as part of the message header, so we're better off using plain old
784 bool gen7_read = (devinfo->gen >= 7 && devinfo->gen < 9 &&
785 spill_offset < (1 << 12) * REG_SIZE);
786 fs_inst *unspill_inst = bld.emit(gen7_read ?
787 SHADER_OPCODE_GEN7_SCRATCH_READ :
788 SHADER_OPCODE_GEN4_SCRATCH_READ,
790 unspill_inst->offset = spill_offset;
793 unspill_inst->base_mrf = spill_base_mrf(bld.shader);
794 unspill_inst->mlen = 1; /* header contains offset */
797 dst.reg_offset += reg_size;
798 spill_offset += reg_size * REG_SIZE;
803 emit_spill(const fs_builder &bld, fs_reg src,
804 uint32_t spill_offset, unsigned count)
806 const unsigned reg_size = src.component_size(bld.dispatch_width()) /
808 assert(count % reg_size == 0);
810 for (unsigned i = 0; i < count / reg_size; i++) {
811 fs_inst *spill_inst =
812 bld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, bld.null_reg_f(), src);
813 src.reg_offset += reg_size;
814 spill_inst->offset = spill_offset + i * reg_size * REG_SIZE;
815 spill_inst->mlen = 1 + reg_size; /* header, value */
816 spill_inst->base_mrf = spill_base_mrf(bld.shader);
821 fs_visitor::choose_spill_reg(struct ra_graph *g)
823 float loop_scale = 1.0;
824 float spill_costs[this->alloc.count];
825 bool no_spill[this->alloc.count];
827 for (unsigned i = 0; i < this->alloc.count; i++) {
828 spill_costs[i] = 0.0;
832 /* Calculate costs for spilling nodes. Call it a cost of 1 per
833 * spill/unspill we'll have to do, and guess that the insides of
834 * loops run 10 times.
836 foreach_block_and_inst(block, fs_inst, inst, cfg) {
837 for (unsigned int i = 0; i < inst->sources; i++) {
838 if (inst->src[i].file == VGRF) {
839 spill_costs[inst->src[i].nr] += loop_scale;
841 /* Register spilling logic assumes full-width registers; smeared
842 * registers have a width of 1 so if we try to spill them we'll
843 * generate invalid assembly. This shouldn't be a problem because
844 * smeared registers are only used as short-term temporaries when
845 * loading pull constants, so spilling them is unlikely to reduce
846 * register pressure anyhow.
848 if (!inst->src[i].is_contiguous()) {
849 no_spill[inst->src[i].nr] = true;
854 if (inst->dst.file == VGRF) {
855 spill_costs[inst->dst.nr] += inst->regs_written * loop_scale;
857 if (!inst->dst.is_contiguous()) {
858 no_spill[inst->dst.nr] = true;
862 switch (inst->opcode) {
868 case BRW_OPCODE_WHILE:
872 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
873 if (inst->src[0].file == VGRF)
874 no_spill[inst->src[0].nr] = true;
877 case SHADER_OPCODE_GEN4_SCRATCH_READ:
878 case SHADER_OPCODE_GEN7_SCRATCH_READ:
879 if (inst->dst.file == VGRF)
880 no_spill[inst->dst.nr] = true;
888 for (unsigned i = 0; i < this->alloc.count; i++) {
890 ra_set_node_spill_cost(g, i, spill_costs[i]);
893 return ra_get_best_spill_node(g);
897 fs_visitor::spill_reg(int spill_reg)
899 int size = alloc.sizes[spill_reg];
900 unsigned int spill_offset = last_scratch;
901 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
903 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
904 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
905 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
906 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
907 * depth), starting from m1. In summary: We may not be able to spill in
908 * SIMD16 mode, because we'd stomp the FB writes.
910 if (!spilled_any_registers) {
911 bool mrf_used[BRW_MAX_MRF(devinfo->gen)];
912 get_used_mrfs(this, mrf_used);
914 for (int i = spill_base_mrf(this); i < BRW_MAX_MRF(devinfo->gen); i++) {
916 fail("Register spilling not supported with m%d used", i);
921 spilled_any_registers = true;
924 last_scratch += size * REG_SIZE;
926 /* Generate spill/unspill instructions for the objects being
927 * spilled. Right now, we spill or unspill the whole thing to a
928 * virtual grf of the same size. For most instructions, though, we
929 * could just spill/unspill the GRF being accessed.
931 foreach_block_and_inst (block, fs_inst, inst, cfg) {
932 const fs_builder ibld = fs_builder(this, block, inst);
934 for (unsigned int i = 0; i < inst->sources; i++) {
935 if (inst->src[i].file == VGRF &&
936 inst->src[i].nr == spill_reg) {
937 int regs_read = inst->regs_read(i);
938 int subset_spill_offset = (spill_offset +
939 REG_SIZE * inst->src[i].reg_offset);
940 fs_reg unspill_dst(VGRF, alloc.allocate(regs_read));
942 inst->src[i].nr = unspill_dst.nr;
943 inst->src[i].reg_offset = 0;
945 const unsigned width =
946 dispatch_width == 16 && regs_read % 2 == 0 ? 16 : 8;
948 /* Set exec_all() on unspill messages under the (rather
949 * pessimistic) assumption that there is no one-to-one
950 * correspondence between channels of the spilled variable in
951 * scratch space and the scratch read message, which operates on
952 * 32 bit channels. It shouldn't hurt in any case because the
953 * unspill destination is a block-local temporary.
955 emit_unspill(ibld.exec_all().group(width, 0),
956 unspill_dst, subset_spill_offset, regs_read);
960 if (inst->dst.file == VGRF &&
961 inst->dst.nr == spill_reg) {
962 int subset_spill_offset = (spill_offset +
963 REG_SIZE * inst->dst.reg_offset);
964 fs_reg spill_src(VGRF, alloc.allocate(inst->regs_written));
966 inst->dst.nr = spill_src.nr;
967 inst->dst.reg_offset = 0;
969 /* If we're immediately spilling the register, we should not use
970 * destination dependency hints. Doing so will cause the GPU do
971 * try to read and write the register at the same time and may
974 inst->no_dd_clear = false;
975 inst->no_dd_check = false;
977 const unsigned width =
978 dispatch_width == 16 && inst->regs_written % 2 == 0 ? 16 : 8;
980 /* Spills should only write data initialized by the instruction for
981 * whichever channels are enabled in the excution mask. If that's
982 * not possible we'll have to emit a matching unspill before the
983 * instruction and set force_writemask_all on the spill.
985 const bool per_channel =
986 inst->dst.is_contiguous() && type_sz(inst->dst.type) == 4 &&
987 inst->exec_size == width;
989 /* Builder used to emit the scratch messages. */
990 const fs_builder ubld = ibld.exec_all(!per_channel).group(width, 0);
992 /* If our write is going to affect just part of the
993 * inst->regs_written(), then we need to unspill the destination
994 * since we write back out all of the regs_written(). If the
995 * original instruction had force_writemask_all set and is not a
996 * partial write, there should be no need for the unspill since the
997 * instruction will be overwriting the whole destination in any case.
999 if (inst->is_partial_write() ||
1000 (!inst->force_writemask_all && !per_channel))
1001 emit_unspill(ubld, spill_src, subset_spill_offset,
1002 inst->regs_written);
1004 emit_spill(ubld.at(block, inst->next), spill_src,
1005 subset_spill_offset, inst->regs_written);
1009 invalidate_live_intervals();