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24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "program/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable *ir)
56 if (variable_storage(ir))
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
65 reg = emit_general_interpolation(ir);
68 hash_table_insert(this->variable_ht, reg, ir);
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
109 if (ir->is_in_uniform_block())
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
123 setup_uniform_values(ir);
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
133 hash_table_insert(this->variable_ht, reg, ir);
137 fs_visitor::visit(ir_dereference_variable *ir)
139 fs_reg *reg = variable_storage(ir->var);
144 fs_visitor::visit(ir_dereference_record *ir)
146 const glsl_type *struct_type = ir->record->type;
148 ir->record->accept(this);
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
154 offset += type_size(struct_type->fields.structure[i].type);
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
161 fs_visitor::visit(ir_dereference_array *ir)
163 ir_constant *constant_index;
165 int element_size = type_size(ir->type);
167 constant_index = ir->array_index->as_constant();
169 ir->array->accept(this);
171 src.type = brw_type_for_base_type(ir->type);
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
184 ir->array_index->accept(this);
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
212 emit(MUL(y_times_a, y, a));
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
223 emit(LRP(dst, a, y, x));
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
248 fs_visitor::try_emit_saturate(ir_expression *ir)
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
257 sat_val->accept(this);
258 fs_reg src = this->result;
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
271 modify->saturate = true;
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
282 /* 3-src instructions were introduced in gen6. */
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
293 if (!mul || mul->operation != ir_binop_mul)
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
317 fs_visitor::visit(ir_expression *ir)
319 unsigned int operand;
323 assert(ir->get_num_operands() <= 3);
325 if (try_emit_saturate(ir))
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
339 assert(this->result.is_valid_3src());
340 op[operand] = this->result;
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
345 assert(!ir->operands[operand]->type->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
348 assert(!ir->operands[operand]->type->is_vector());
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
354 this->result = fs_reg(this, ir->type);
356 switch (ir->operation) {
357 case ir_unop_logic_not:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
361 emit(XOR(this->result, op[0], fs_reg(1)));
364 op[0].negate = !op[0].negate;
365 emit(MOV(this->result, op[0]));
369 op[0].negate = false;
370 emit(MOV(this->result, op[0]));
373 temp = fs_reg(this, ir->type);
375 emit(MOV(this->result, fs_reg(0.0f)));
377 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
378 inst = emit(MOV(this->result, fs_reg(1.0f)));
379 inst->predicate = BRW_PREDICATE_NORMAL;
381 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
382 inst = emit(MOV(this->result, fs_reg(-1.0f)));
383 inst->predicate = BRW_PREDICATE_NORMAL;
387 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
391 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
394 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
401 case ir_unop_sin_reduced:
402 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
405 case ir_unop_cos_reduced:
406 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
410 emit(FS_OPCODE_DDX, this->result, op[0]);
413 emit(FS_OPCODE_DDY, this->result, op[0]);
417 emit(ADD(this->result, op[0], op[1]));
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
424 if (ir->type->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
430 * FINISHME: Emit just the MUL if we know an operand is small
433 if (brw->gen >= 7 && dispatch_width == 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
436 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
438 emit(MUL(acc, op[0], op[1]));
439 emit(MACH(reg_null_d, op[0], op[1]));
440 emit(MOV(this->result, fs_reg(acc)));
442 emit(MUL(this->result, op[0], op[1]));
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir->type->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir->type->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
457 case ir_binop_greater:
458 case ir_binop_lequal:
459 case ir_binop_gequal:
461 case ir_binop_all_equal:
462 case ir_binop_nequal:
463 case ir_binop_any_nequal:
464 resolve_bool_comparison(ir->operands[0], &op[0]);
465 resolve_bool_comparison(ir->operands[1], &op[1]);
467 emit(CMP(this->result, op[0], op[1],
468 brw_conditional_for_comparison(ir->operation)));
471 case ir_binop_logic_xor:
472 emit(XOR(this->result, op[0], op[1]));
475 case ir_binop_logic_or:
476 emit(OR(this->result, op[0], op[1]));
479 case ir_binop_logic_and:
480 emit(AND(this->result, op[0], op[1]));
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
489 assert(!"not reached: should be handled by lower_noise");
492 case ir_quadop_vector:
493 assert(!"not reached: should be handled by lower_quadop_vector");
496 case ir_binop_vector_extract:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
500 case ir_triop_vector_insert:
501 assert(!"not reached: should be handled by lower_vector_insert()");
505 assert(!"not reached: should be handled by ldexp_to_arith()");
509 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
513 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
516 case ir_unop_bitcast_i2f:
517 case ir_unop_bitcast_u2f:
518 op[0].type = BRW_REGISTER_TYPE_F;
519 this->result = op[0];
522 case ir_unop_bitcast_f2u:
523 op[0].type = BRW_REGISTER_TYPE_UD;
524 this->result = op[0];
527 case ir_unop_bitcast_f2i:
528 op[0].type = BRW_REGISTER_TYPE_D;
529 this->result = op[0];
535 emit(MOV(this->result, op[0]));
539 emit(AND(this->result, op[0], fs_reg(1)));
542 temp = fs_reg(this, glsl_type::int_type);
543 emit(AND(temp, op[0], fs_reg(1)));
544 emit(MOV(this->result, temp));
548 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
551 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
555 emit(RNDZ(this->result, op[0]));
558 op[0].negate = !op[0].negate;
559 emit(RNDD(this->result, op[0]));
560 this->result.negate = true;
563 emit(RNDD(this->result, op[0]));
566 emit(FRC(this->result, op[0]));
568 case ir_unop_round_even:
569 emit(RNDE(this->result, op[0]));
574 resolve_ud_negate(&op[0]);
575 resolve_ud_negate(&op[1]);
576 emit_minmax(ir->operation == ir_binop_min ?
577 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
578 this->result, op[0], op[1]);
580 case ir_unop_pack_snorm_2x16:
581 case ir_unop_pack_snorm_4x8:
582 case ir_unop_pack_unorm_2x16:
583 case ir_unop_pack_unorm_4x8:
584 case ir_unop_unpack_snorm_2x16:
585 case ir_unop_unpack_snorm_4x8:
586 case ir_unop_unpack_unorm_2x16:
587 case ir_unop_unpack_unorm_4x8:
588 case ir_unop_unpack_half_2x16:
589 case ir_unop_pack_half_2x16:
590 assert(!"not reached: should be handled by lower_packing_builtins");
592 case ir_unop_unpack_half_2x16_split_x:
593 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
595 case ir_unop_unpack_half_2x16_split_y:
596 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
599 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
602 case ir_unop_bitfield_reverse:
603 emit(BFREV(this->result, op[0]));
605 case ir_unop_bit_count:
606 emit(CBIT(this->result, op[0]));
608 case ir_unop_find_msb:
609 temp = fs_reg(this, glsl_type::uint_type);
610 emit(FBH(temp, op[0]));
612 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
613 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
614 * subtract the result from 31 to convert the MSB count into an LSB count.
617 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
618 emit(MOV(this->result, temp));
619 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
622 inst = emit(ADD(this->result, temp, fs_reg(31)));
623 inst->predicate = BRW_PREDICATE_NORMAL;
625 case ir_unop_find_lsb:
626 emit(FBL(this->result, op[0]));
628 case ir_triop_bitfield_extract:
629 /* Note that the instruction's argument order is reversed from GLSL
632 emit(BFE(this->result, op[2], op[1], op[0]));
635 emit(BFI1(this->result, op[0], op[1]));
638 emit(BFI2(this->result, op[0], op[1], op[2]));
640 case ir_quadop_bitfield_insert:
641 assert(!"not reached: should be handled by "
642 "lower_instructions::bitfield_insert_to_bfm_bfi");
645 case ir_unop_bit_not:
646 emit(NOT(this->result, op[0]));
648 case ir_binop_bit_and:
649 emit(AND(this->result, op[0], op[1]));
651 case ir_binop_bit_xor:
652 emit(XOR(this->result, op[0], op[1]));
654 case ir_binop_bit_or:
655 emit(OR(this->result, op[0], op[1]));
658 case ir_binop_lshift:
659 emit(SHL(this->result, op[0], op[1]));
662 case ir_binop_rshift:
663 if (ir->type->base_type == GLSL_TYPE_INT)
664 emit(ASR(this->result, op[0], op[1]));
666 emit(SHR(this->result, op[0], op[1]));
668 case ir_binop_pack_half_2x16_split:
669 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
671 case ir_binop_ubo_load: {
672 /* This IR node takes a constant uniform block and a constant or
673 * variable byte offset within the block and loads a vector from that.
675 ir_constant *uniform_block = ir->operands[0]->as_constant();
676 ir_constant *const_offset = ir->operands[1]->as_constant();
677 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
679 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
680 packed_consts.type = result.type;
682 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
683 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
684 packed_consts, surf_index, const_offset_reg));
686 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
687 for (int i = 0; i < ir->type->vector_elements; i++) {
688 /* UBO bools are any nonzero value. We consider bools to be
689 * values with the low bit set to 1. Convert them using CMP.
691 if (ir->type->base_type == GLSL_TYPE_BOOL) {
692 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
694 emit(MOV(result, packed_consts));
697 packed_consts.smear++;
700 /* The std140 packing rules don't allow vectors to cross 16-byte
701 * boundaries, and a reg is 32 bytes.
703 assert(packed_consts.smear < 8);
706 /* Turn the byte offset into a dword offset. */
707 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
708 emit(SHR(base_offset, op[1], fs_reg(2)));
710 for (int i = 0; i < ir->type->vector_elements; i++) {
711 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
714 if (ir->type->base_type == GLSL_TYPE_BOOL)
715 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
721 result.reg_offset = 0;
726 /* Note that the instruction's argument order is reversed from GLSL
729 emit(MAD(this->result, op[2], op[1], op[0]));
733 emit_lrp(this->result, op[0], op[1], op[2]);
737 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
738 inst = emit(BRW_OPCODE_SEL, this->result, op[1], op[2]);
739 inst->predicate = BRW_PREDICATE_NORMAL;
745 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
746 const glsl_type *type, bool predicated)
748 switch (type->base_type) {
749 case GLSL_TYPE_FLOAT:
753 for (unsigned int i = 0; i < type->components(); i++) {
754 l.type = brw_type_for_base_type(type);
755 r.type = brw_type_for_base_type(type);
757 if (predicated || !l.equals(r)) {
758 fs_inst *inst = emit(MOV(l, r));
759 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
766 case GLSL_TYPE_ARRAY:
767 for (unsigned int i = 0; i < type->length; i++) {
768 emit_assignment_writes(l, r, type->fields.array, predicated);
772 case GLSL_TYPE_STRUCT:
773 for (unsigned int i = 0; i < type->length; i++) {
774 emit_assignment_writes(l, r, type->fields.structure[i].type,
779 case GLSL_TYPE_SAMPLER:
783 case GLSL_TYPE_ERROR:
784 case GLSL_TYPE_INTERFACE:
785 assert(!"not reached");
790 /* If the RHS processing resulted in an instruction generating a
791 * temporary value, and it would be easy to rewrite the instruction to
792 * generate its result right into the LHS instead, do so. This ends
793 * up reliably removing instructions where it can be tricky to do so
794 * later without real UD chain information.
797 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
800 fs_inst *pre_rhs_inst,
801 fs_inst *last_rhs_inst)
803 /* Only attempt if we're doing a direct assignment. */
805 !(ir->lhs->type->is_scalar() ||
806 (ir->lhs->type->is_vector() &&
807 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
810 /* Make sure the last instruction generated our source reg. */
811 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
817 /* If last_rhs_inst wrote a different number of components than our LHS,
818 * we can't safely rewrite it.
820 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
823 /* Success! Rewrite the instruction. */
830 fs_visitor::visit(ir_assignment *ir)
835 /* FINISHME: arrays on the lhs */
836 ir->lhs->accept(this);
839 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
841 ir->rhs->accept(this);
844 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
846 assert(l.file != BAD_FILE);
847 assert(r.file != BAD_FILE);
849 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
853 emit_bool_to_cond_code(ir->condition);
856 if (ir->lhs->type->is_scalar() ||
857 ir->lhs->type->is_vector()) {
858 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
859 if (ir->write_mask & (1 << i)) {
860 inst = emit(MOV(l, r));
862 inst->predicate = BRW_PREDICATE_NORMAL;
868 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
873 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
874 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
884 if (ir->shadow_comparitor) {
885 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
886 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
887 coordinate.reg_offset++;
890 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
891 * the unused slots must be zeroed.
893 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
894 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
898 if (ir->op == ir_tex) {
899 /* There's no plain shadow compare message, so we use shadow
900 * compare with a bias of 0.0.
902 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
904 } else if (ir->op == ir_txb || ir->op == ir_txl) {
905 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
908 assert(!"Should not get here.");
911 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
913 } else if (ir->op == ir_tex) {
914 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
915 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
916 coordinate.reg_offset++;
918 /* zero the others. */
919 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
920 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
922 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
924 } else if (ir->op == ir_txd) {
927 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
928 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
929 coordinate.reg_offset++;
931 /* the slots for u and v are always present, but r is optional */
932 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
935 * dPdx = dudx, dvdx, drdx
936 * dPdy = dudy, dvdy, drdy
938 * 1-arg: Does not exist.
940 * 2-arg: dudx dvdx dudy dvdy
941 * dPdx.x dPdx.y dPdy.x dPdy.y
944 * 3-arg: dudx dvdx drdx dudy dvdy drdy
945 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
948 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
949 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
952 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
954 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
955 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
958 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
959 } else if (ir->op == ir_txs) {
960 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
962 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
965 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
966 * instructions. We'll need to do SIMD16 here.
969 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
971 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
972 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
974 coordinate.reg_offset++;
977 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
978 * be necessary for TXF (ld), but seems wise to do for all messages.
980 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
981 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
984 /* lod/bias appears after u/v/r. */
987 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
990 /* The unused upper half. */
995 /* Now, since we're doing simd16, the return is 2 interleaved
996 * vec4s where the odd-indexed ones are junk. We'll need to move
997 * this weirdness around to the expected layout.
1000 dst = fs_reg(GRF, virtual_grf_alloc(8),
1002 brw_type_for_base_type(ir->type) :
1003 BRW_REGISTER_TYPE_F));
1006 fs_inst *inst = NULL;
1009 inst = emit(SHADER_OPCODE_TEX, dst);
1012 inst = emit(FS_OPCODE_TXB, dst);
1015 inst = emit(SHADER_OPCODE_TXL, dst);
1018 inst = emit(SHADER_OPCODE_TXD, dst);
1021 inst = emit(SHADER_OPCODE_TXS, dst);
1024 inst = emit(SHADER_OPCODE_TXF, dst);
1027 fail("unrecognized texture opcode");
1029 inst->base_mrf = base_mrf;
1031 inst->header_present = true;
1032 inst->regs_written = simd16 ? 8 : 4;
1035 for (int i = 0; i < 4; i++) {
1036 emit(MOV(orig_dst, dst));
1037 orig_dst.reg_offset++;
1038 dst.reg_offset += 2;
1045 /* gen5's sampler has slots for u, v, r, array index, then optional
1046 * parameters like shadow comparitor or LOD bias. If optional
1047 * parameters aren't present, those base slots are optional and don't
1048 * need to be included in the message.
1050 * We don't fill in the unnecessary slots regardless, which may look
1051 * surprising in the disassembly.
1054 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1055 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1056 fs_reg sample_index)
1060 int reg_width = dispatch_width / 8;
1061 bool header_present = false;
1062 const int vector_elements =
1063 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1065 if (ir->offset != NULL && ir->op == ir_txf) {
1066 /* It appears that the ld instruction used for txf does its
1067 * address bounds check before adding in the offset. To work
1068 * around this, just add the integer offset to the integer texel
1069 * coordinate, and don't put the offset in the header.
1071 ir_constant *offset = ir->offset->as_constant();
1072 for (int i = 0; i < vector_elements; i++) {
1073 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1075 offset->value.i[i]));
1076 coordinate.reg_offset++;
1080 /* The offsets set up by the ir_texture visitor are in the
1081 * m1 header, so we can't go headerless.
1083 header_present = true;
1088 for (int i = 0; i < vector_elements; i++) {
1089 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1091 coordinate.reg_offset++;
1094 mlen += vector_elements * reg_width;
1096 if (ir->shadow_comparitor) {
1097 mlen = MAX2(mlen, header_present + 4 * reg_width);
1099 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1103 fs_inst *inst = NULL;
1106 inst = emit(SHADER_OPCODE_TEX, dst);
1109 mlen = MAX2(mlen, header_present + 4 * reg_width);
1110 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1113 inst = emit(FS_OPCODE_TXB, dst);
1116 mlen = MAX2(mlen, header_present + 4 * reg_width);
1117 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1120 inst = emit(SHADER_OPCODE_TXL, dst);
1123 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1127 * dPdx = dudx, dvdx, drdx
1128 * dPdy = dudy, dvdy, drdy
1130 * Load up these values:
1131 * - dudx dudy dvdx dvdy drdx drdy
1132 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1134 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1135 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1139 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1144 inst = emit(SHADER_OPCODE_TXD, dst);
1148 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1150 inst = emit(SHADER_OPCODE_TXS, dst);
1152 case ir_query_levels:
1153 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1155 inst = emit(SHADER_OPCODE_TXS, dst);
1158 mlen = header_present + 4 * reg_width;
1159 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1160 inst = emit(SHADER_OPCODE_TXF, dst);
1163 mlen = header_present + 4 * reg_width;
1166 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1168 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1170 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1173 inst = emit(SHADER_OPCODE_LOD, dst);
1176 inst = emit(SHADER_OPCODE_TG4, dst);
1179 fail("unrecognized texture opcode");
1182 inst->base_mrf = base_mrf;
1184 inst->header_present = header_present;
1185 inst->regs_written = 4;
1188 fail("Message length >11 disallowed by hardware\n");
1195 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1196 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1197 fs_reg sample_index)
1201 int reg_width = dispatch_width / 8;
1202 bool header_present = false;
1205 if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf)) {
1206 /* * The offsets set up by the ir_texture visitor are in the
1207 * m1 header, so we can't go headerless.
1209 * * ir4_tg4 needs to place its channel select in the header,
1210 * for interaction with ARB_texture_swizzle
1212 header_present = true;
1217 if (ir->shadow_comparitor) {
1218 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1222 /* Set up the LOD info */
1229 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1233 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1237 if (dispatch_width == 16)
1238 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1240 /* Load dPdx and the coordinate together:
1241 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1243 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1244 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1245 coordinate.reg_offset++;
1248 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1249 * only derivatives for (u, v, r).
1251 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1252 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1256 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1264 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1267 case ir_query_levels:
1268 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1272 /* It appears that the ld instruction used for txf does its
1273 * address bounds check before adding in the offset. To work
1274 * around this, just add the integer offset to the integer texel
1275 * coordinate, and don't put the offset in the header.
1278 ir_constant *offset = ir->offset->as_constant();
1279 offsets[0] = offset->value.i[0];
1280 offsets[1] = offset->value.i[1];
1281 offsets[2] = offset->value.i[2];
1283 memset(offsets, 0, sizeof(offsets));
1286 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1287 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1288 coordinate, offsets[0]));
1289 coordinate.reg_offset++;
1292 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1295 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1296 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1297 coordinate, offsets[i]));
1298 coordinate.reg_offset++;
1303 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1306 /* constant zero MCS; we arrange to never actually have a compressed
1307 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1308 * if we ever support texturing from compressed multisample surfaces
1310 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1313 /* there is no offsetting for this message; just copy in the integer
1314 * texture coordinates
1316 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1317 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1319 coordinate.reg_offset++;
1325 /* Set up the coordinate (except for cases where it was done above) */
1326 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms && ir->op != ir_query_levels) {
1327 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1328 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1329 coordinate.reg_offset++;
1334 /* Generate the SEND */
1335 fs_inst *inst = NULL;
1337 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1338 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1339 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1340 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1341 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1342 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1343 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1344 case ir_query_levels: inst = emit(SHADER_OPCODE_TXS, dst); break;
1345 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1346 case ir_tg4: inst = emit(SHADER_OPCODE_TG4, dst); break;
1348 inst->base_mrf = base_mrf;
1350 inst->header_present = header_present;
1351 inst->regs_written = 4;
1354 fail("Message length >11 disallowed by hardware\n");
1361 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1362 bool is_rect, int sampler, int texunit)
1364 fs_inst *inst = NULL;
1365 bool needs_gl_clamp = true;
1366 fs_reg scale_x, scale_y;
1368 /* The 965 requires the EU to do the normalization of GL rectangle
1369 * texture coordinates. We use the program parameter state
1370 * tracking to get the scaling factor.
1374 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1375 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1376 struct gl_program_parameter_list *params = fp->Base.Parameters;
1377 int tokens[STATE_LENGTH] = {
1379 STATE_TEXRECT_SCALE,
1385 if (dispatch_width == 16) {
1386 fail("rectangle scale uniform setup not supported on 16-wide\n");
1390 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1391 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1393 GLuint index = _mesa_add_state_reference(params,
1394 (gl_state_index *)tokens);
1395 c->prog_data.param[c->prog_data.nr_params++] =
1396 &fp->Base.Parameters->ParameterValues[index][0].f;
1397 c->prog_data.param[c->prog_data.nr_params++] =
1398 &fp->Base.Parameters->ParameterValues[index][1].f;
1401 /* The 965 requires the EU to do the normalization of GL rectangle
1402 * texture coordinates. We use the program parameter state
1403 * tracking to get the scaling factor.
1405 if (brw->gen < 6 && is_rect) {
1406 fs_reg dst = fs_reg(this, ir->coordinate->type);
1407 fs_reg src = coordinate;
1410 emit(MUL(dst, src, scale_x));
1413 emit(MUL(dst, src, scale_y));
1414 } else if (is_rect) {
1415 /* On gen6+, the sampler handles the rectangle coordinates
1416 * natively, without needing rescaling. But that means we have
1417 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1418 * not [0, 1] like the default case below.
1420 needs_gl_clamp = false;
1422 for (int i = 0; i < 2; i++) {
1423 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1424 fs_reg chan = coordinate;
1425 chan.reg_offset += i;
1427 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1428 inst->conditional_mod = BRW_CONDITIONAL_G;
1430 /* Our parameter comes in as 1.0/width or 1.0/height,
1431 * because that's what people normally want for doing
1432 * texture rectangle handling. We need width or height
1433 * for clamping, but we don't care enough to make a new
1434 * parameter type, so just invert back.
1436 fs_reg limit = fs_reg(this, glsl_type::float_type);
1437 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1438 emit(SHADER_OPCODE_RCP, limit, limit);
1440 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1441 inst->conditional_mod = BRW_CONDITIONAL_L;
1446 if (ir->coordinate && needs_gl_clamp) {
1447 for (unsigned int i = 0;
1448 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1449 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1450 fs_reg chan = coordinate;
1451 chan.reg_offset += i;
1453 fs_inst *inst = emit(MOV(chan, chan));
1454 inst->saturate = true;
1462 fs_visitor::visit(ir_texture *ir)
1464 fs_inst *inst = NULL;
1467 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1468 /* FINISHME: We're failing to recompile our programs when the sampler is
1469 * updated. This only matters for the texture rectangle scale parameters
1470 * (pre-gen6, or gen6+ with GL_CLAMP).
1472 int texunit = fp->Base.SamplerUnits[sampler];
1474 if (ir->op == ir_tg4) {
1475 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1476 * emitting anything other than setting up the constant result.
1478 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], 0);
1479 if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
1481 fs_reg res = fs_reg(this, glsl_type::vec4_type);
1484 for (int i=0; i<4; i++) {
1485 emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
1492 /* Should be lowered by do_lower_texture_projection */
1493 assert(!ir->projector);
1495 /* Generate code to compute all the subexpression trees. This has to be
1496 * done before loading any values into MRFs for the sampler message since
1497 * generating these values may involve SEND messages that need the MRFs.
1500 if (ir->coordinate) {
1501 ir->coordinate->accept(this);
1503 coordinate = rescale_texcoord(ir, this->result,
1504 ir->sampler->type->sampler_dimensionality ==
1505 GLSL_SAMPLER_DIM_RECT,
1509 fs_reg shadow_comparitor;
1510 if (ir->shadow_comparitor) {
1511 ir->shadow_comparitor->accept(this);
1512 shadow_comparitor = this->result;
1515 fs_reg lod, lod2, sample_index;
1520 case ir_query_levels:
1523 ir->lod_info.bias->accept(this);
1527 ir->lod_info.grad.dPdx->accept(this);
1530 ir->lod_info.grad.dPdy->accept(this);
1531 lod2 = this->result;
1536 ir->lod_info.lod->accept(this);
1540 ir->lod_info.sample_index->accept(this);
1541 sample_index = this->result;
1544 assert(!"Unrecognized texture opcode");
1547 /* Writemasking doesn't eliminate channels on SIMD8 texture
1548 * samples, so don't worry about them.
1550 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1552 if (brw->gen >= 7) {
1553 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1554 lod, lod2, sample_index);
1555 } else if (brw->gen >= 5) {
1556 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1557 lod, lod2, sample_index);
1559 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1563 /* The header is set up by generate_tex() when necessary. */
1564 inst->src[0] = reg_undef;
1566 if (ir->offset != NULL && ir->op != ir_txf)
1567 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1569 if (ir->op == ir_tg4)
1570 inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
1572 inst->sampler = sampler;
1574 if (ir->shadow_comparitor)
1575 inst->shadow_compare = true;
1577 /* fixup #layers for cube map arrays */
1578 if (ir->op == ir_txs) {
1579 glsl_type const *type = ir->sampler->type;
1580 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1581 type->sampler_array) {
1583 depth.reg_offset = 2;
1584 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1588 swizzle_result(ir, dst, sampler);
1592 * Set up the gather channel based on the swizzle, for gather4.
1595 fs_visitor::gather_channel(ir_texture *ir, int sampler)
1597 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], 0 /* red */);
1598 if (c->key.tex.gather_channel_quirk_mask & (1<<sampler))
1599 return 2; /* gather4 sampler is broken for green channel on RG32F --
1600 * we must ask for blue instead.
1603 case SWIZZLE_X: return 0;
1604 case SWIZZLE_Y: return 1;
1605 case SWIZZLE_Z: return 2;
1606 case SWIZZLE_W: return 3;
1608 assert(!"Not reached"); /* zero, one swizzles handled already */
1614 * Swizzle the result of a texture result. This is necessary for
1615 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1618 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1620 if (ir->op == ir_query_levels) {
1621 /* # levels is in .w */
1622 orig_val.reg_offset += 3;
1623 this->result = orig_val;
1627 this->result = orig_val;
1629 /* txs,lod don't actually sample the texture, so swizzling the result
1632 if (ir->op == ir_txs || ir->op == ir_lod || ir->op == ir_tg4)
1635 if (ir->type == glsl_type::float_type) {
1636 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1637 assert(ir->sampler->type->sampler_shadow);
1638 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1639 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1641 for (int i = 0; i < 4; i++) {
1642 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1643 fs_reg l = swizzled_result;
1646 if (swiz == SWIZZLE_ZERO) {
1647 emit(MOV(l, fs_reg(0.0f)));
1648 } else if (swiz == SWIZZLE_ONE) {
1649 emit(MOV(l, fs_reg(1.0f)));
1651 fs_reg r = orig_val;
1652 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1656 this->result = swizzled_result;
1661 fs_visitor::visit(ir_swizzle *ir)
1663 ir->val->accept(this);
1664 fs_reg val = this->result;
1666 if (ir->type->vector_elements == 1) {
1667 this->result.reg_offset += ir->mask.x;
1671 fs_reg result = fs_reg(this, ir->type);
1672 this->result = result;
1674 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1675 fs_reg channel = val;
1693 channel.reg_offset += swiz;
1694 emit(MOV(result, channel));
1695 result.reg_offset++;
1700 fs_visitor::visit(ir_discard *ir)
1702 assert(ir->condition == NULL); /* FINISHME */
1704 /* We track our discarded pixels in f0.1. By predicating on it, we can
1705 * update just the flag bits that aren't yet discarded. By emitting a
1706 * CMP of g0 != g0, all our currently executing channels will get turned
1709 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1710 BRW_REGISTER_TYPE_UW));
1711 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1712 BRW_CONDITIONAL_NZ));
1713 cmp->predicate = BRW_PREDICATE_NORMAL;
1714 cmp->flag_subreg = 1;
1716 if (brw->gen >= 6) {
1717 /* For performance, after a discard, jump to the end of the shader.
1718 * However, many people will do foliage by discarding based on a
1719 * texture's alpha mask, and then continue on to texture with the
1720 * remaining pixels. To avoid trashing the derivatives for those
1721 * texture samples, we'll only jump if all of the pixels in the subspan
1722 * have been discarded.
1724 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1725 discard_jump->flag_subreg = 1;
1726 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1727 discard_jump->predicate_inverse = true;
1732 fs_visitor::visit(ir_constant *ir)
1734 /* Set this->result to reg at the bottom of the function because some code
1735 * paths will cause this visitor to be applied to other fields. This will
1736 * cause the value stored in this->result to be modified.
1738 * Make reg constant so that it doesn't get accidentally modified along the
1739 * way. Yes, I actually had this problem. :(
1741 const fs_reg reg(this, ir->type);
1742 fs_reg dst_reg = reg;
1744 if (ir->type->is_array()) {
1745 const unsigned size = type_size(ir->type->fields.array);
1747 for (unsigned i = 0; i < ir->type->length; i++) {
1748 ir->array_elements[i]->accept(this);
1749 fs_reg src_reg = this->result;
1751 dst_reg.type = src_reg.type;
1752 for (unsigned j = 0; j < size; j++) {
1753 emit(MOV(dst_reg, src_reg));
1754 src_reg.reg_offset++;
1755 dst_reg.reg_offset++;
1758 } else if (ir->type->is_record()) {
1759 foreach_list(node, &ir->components) {
1760 ir_constant *const field = (ir_constant *) node;
1761 const unsigned size = type_size(field->type);
1763 field->accept(this);
1764 fs_reg src_reg = this->result;
1766 dst_reg.type = src_reg.type;
1767 for (unsigned j = 0; j < size; j++) {
1768 emit(MOV(dst_reg, src_reg));
1769 src_reg.reg_offset++;
1770 dst_reg.reg_offset++;
1774 const unsigned size = type_size(ir->type);
1776 for (unsigned i = 0; i < size; i++) {
1777 switch (ir->type->base_type) {
1778 case GLSL_TYPE_FLOAT:
1779 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1781 case GLSL_TYPE_UINT:
1782 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1785 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1787 case GLSL_TYPE_BOOL:
1788 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1791 assert(!"Non-float/uint/int/bool constant");
1793 dst_reg.reg_offset++;
1801 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1803 ir_expression *expr = ir->as_expression();
1806 expr->operation != ir_binop_logic_and &&
1807 expr->operation != ir_binop_logic_or &&
1808 expr->operation != ir_binop_logic_xor) {
1812 assert(expr->get_num_operands() <= 2);
1813 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1814 assert(expr->operands[i]->type->is_scalar());
1816 expr->operands[i]->accept(this);
1817 op[i] = this->result;
1819 resolve_ud_negate(&op[i]);
1822 switch (expr->operation) {
1823 case ir_unop_logic_not:
1824 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1825 inst->conditional_mod = BRW_CONDITIONAL_Z;
1829 if (brw->gen >= 6) {
1830 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1832 inst = emit(MOV(reg_null_f, op[0]));
1833 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1838 if (brw->gen >= 6) {
1839 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1841 inst = emit(MOV(reg_null_d, op[0]));
1842 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1846 case ir_binop_greater:
1847 case ir_binop_gequal:
1849 case ir_binop_lequal:
1850 case ir_binop_equal:
1851 case ir_binop_all_equal:
1852 case ir_binop_nequal:
1853 case ir_binop_any_nequal:
1854 resolve_bool_comparison(expr->operands[0], &op[0]);
1855 resolve_bool_comparison(expr->operands[1], &op[1]);
1857 emit(CMP(reg_null_d, op[0], op[1],
1858 brw_conditional_for_comparison(expr->operation)));
1862 assert(!"not reached");
1863 fail("bad cond code\n");
1871 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1872 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1876 * Emit a gen6 IF statement with the comparison folded into the IF
1880 fs_visitor::emit_if_gen6(ir_if *ir)
1882 ir_expression *expr = ir->condition->as_expression();
1889 assert(expr->get_num_operands() <= 2);
1890 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1891 assert(expr->operands[i]->type->is_scalar());
1893 expr->operands[i]->accept(this);
1894 op[i] = this->result;
1897 switch (expr->operation) {
1898 case ir_unop_logic_not:
1899 case ir_binop_logic_xor:
1900 case ir_binop_logic_or:
1901 case ir_binop_logic_and:
1902 /* For operations on bool arguments, only the low bit of the bool is
1903 * valid, and the others are undefined. Fall back to the condition
1909 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1910 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1914 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1917 case ir_binop_greater:
1918 case ir_binop_gequal:
1920 case ir_binop_lequal:
1921 case ir_binop_equal:
1922 case ir_binop_all_equal:
1923 case ir_binop_nequal:
1924 case ir_binop_any_nequal:
1925 resolve_bool_comparison(expr->operands[0], &op[0]);
1926 resolve_bool_comparison(expr->operands[1], &op[1]);
1928 emit(IF(op[0], op[1],
1929 brw_conditional_for_comparison(expr->operation)));
1932 assert(!"not reached");
1933 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1934 fail("bad condition\n");
1939 emit_bool_to_cond_code(ir->condition);
1940 fs_inst *inst = emit(BRW_OPCODE_IF);
1941 inst->predicate = BRW_PREDICATE_NORMAL;
1945 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1947 * Many GLSL shaders contain the following pattern:
1949 * x = condition ? foo : bar
1951 * The compiler emits an ir_if tree for this, since each subexpression might be
1952 * a complex tree that could have side-effects or short-circuit logic.
1954 * However, the common case is to simply select one of two constants or
1955 * variable values---which is exactly what SEL is for. In this case, the
1956 * assembly looks like:
1964 * which can be easily translated into:
1966 * (+f0) SEL dst src0 src1
1968 * If src0 is an immediate value, we promote it to a temporary GRF.
1971 fs_visitor::try_replace_with_sel()
1973 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1974 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1976 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1978 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1981 fs_inst *match = (fs_inst *) endif_inst->prev;
1982 for (int i = 0; i < 4; i++) {
1983 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1985 match = (fs_inst *) match->prev;
1988 /* The opcodes match; it looks like the right sequence of instructions. */
1989 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1990 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1991 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1993 /* Check that the MOVs are the right form. */
1994 if (then_mov->dst.equals(else_mov->dst) &&
1995 !then_mov->is_partial_write() &&
1996 !else_mov->is_partial_write()) {
1998 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1999 while (!if_inst->next->is_tail_sentinel())
2000 if_inst->next->remove();
2003 /* Only the last source register can be a constant, so if the MOV in
2004 * the "then" clause uses a constant, we need to put it in a temporary.
2006 fs_reg src0(then_mov->src[0]);
2007 if (src0.file == IMM) {
2008 src0 = fs_reg(this, glsl_type::float_type);
2009 src0.type = then_mov->src[0].type;
2010 emit(MOV(src0, then_mov->src[0]));
2014 if (if_inst->conditional_mod) {
2015 /* Sandybridge-specific IF with embedded comparison */
2016 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
2017 if_inst->conditional_mod));
2018 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
2019 sel->predicate = BRW_PREDICATE_NORMAL;
2021 /* Separate CMP and IF instructions */
2022 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
2023 sel->predicate = if_inst->predicate;
2024 sel->predicate_inverse = if_inst->predicate_inverse;
2030 fs_visitor::visit(ir_if *ir)
2032 if (brw->gen < 6 && dispatch_width == 16) {
2033 fail("Can't support (non-uniform) control flow on 16-wide\n");
2036 /* Don't point the annotation at the if statement, because then it plus
2037 * the then and else blocks get printed.
2039 this->base_ir = ir->condition;
2041 if (brw->gen == 6) {
2044 emit_bool_to_cond_code(ir->condition);
2046 emit(IF(BRW_PREDICATE_NORMAL));
2049 foreach_list(node, &ir->then_instructions) {
2050 ir_instruction *ir = (ir_instruction *)node;
2056 if (!ir->else_instructions.is_empty()) {
2057 emit(BRW_OPCODE_ELSE);
2059 foreach_list(node, &ir->else_instructions) {
2060 ir_instruction *ir = (ir_instruction *)node;
2067 emit(BRW_OPCODE_ENDIF);
2069 try_replace_with_sel();
2073 fs_visitor::visit(ir_loop *ir)
2075 fs_reg counter = reg_undef;
2077 if (brw->gen < 6 && dispatch_width == 16) {
2078 fail("Can't support (non-uniform) control flow on 16-wide\n");
2082 this->base_ir = ir->counter;
2083 ir->counter->accept(this);
2084 counter = *(variable_storage(ir->counter));
2087 this->base_ir = ir->from;
2088 ir->from->accept(this);
2090 emit(MOV(counter, this->result));
2094 this->base_ir = NULL;
2095 emit(BRW_OPCODE_DO);
2098 this->base_ir = ir->to;
2099 ir->to->accept(this);
2101 emit(CMP(reg_null_d, counter, this->result,
2102 brw_conditional_for_comparison(ir->cmp)));
2104 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2105 inst->predicate = BRW_PREDICATE_NORMAL;
2108 foreach_list(node, &ir->body_instructions) {
2109 ir_instruction *ir = (ir_instruction *)node;
2115 if (ir->increment) {
2116 this->base_ir = ir->increment;
2117 ir->increment->accept(this);
2118 emit(ADD(counter, counter, this->result));
2121 this->base_ir = NULL;
2122 emit(BRW_OPCODE_WHILE);
2126 fs_visitor::visit(ir_loop_jump *ir)
2129 case ir_loop_jump::jump_break:
2130 emit(BRW_OPCODE_BREAK);
2132 case ir_loop_jump::jump_continue:
2133 emit(BRW_OPCODE_CONTINUE);
2139 fs_visitor::visit(ir_call *ir)
2141 assert(!"FINISHME");
2145 fs_visitor::visit(ir_return *ir)
2147 assert(!"FINISHME");
2151 fs_visitor::visit(ir_function *ir)
2153 /* Ignore function bodies other than main() -- we shouldn't see calls to
2154 * them since they should all be inlined before we get to ir_to_mesa.
2156 if (strcmp(ir->name, "main") == 0) {
2157 const ir_function_signature *sig;
2160 sig = ir->matching_signature(NULL, &empty);
2164 foreach_list(node, &sig->body) {
2165 ir_instruction *ir = (ir_instruction *)node;
2174 fs_visitor::visit(ir_function_signature *ir)
2176 assert(!"not reached");
2181 fs_visitor::visit(ir_emit_vertex *)
2183 assert(!"not reached");
2187 fs_visitor::visit(ir_end_primitive *)
2189 assert(!"not reached");
2193 fs_visitor::emit(fs_inst inst)
2195 fs_inst *list_inst = new(mem_ctx) fs_inst;
2202 fs_visitor::emit(fs_inst *inst)
2204 if (force_uncompressed_stack > 0)
2205 inst->force_uncompressed = true;
2206 else if (force_sechalf_stack > 0)
2207 inst->force_sechalf = true;
2209 inst->annotation = this->current_annotation;
2210 inst->ir = this->base_ir;
2212 this->instructions.push_tail(inst);
2218 fs_visitor::emit(exec_list list)
2220 foreach_list_safe(node, &list) {
2221 fs_inst *inst = (fs_inst *)node;
2227 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2229 fs_visitor::emit_dummy_fs()
2231 int reg_width = dispatch_width / 8;
2233 /* Everyone's favorite color. */
2234 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2235 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2236 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2237 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2240 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2241 write->base_mrf = 2;
2242 write->mlen = 4 * reg_width;
2246 /* The register location here is relative to the start of the URB
2247 * data. It will get adjusted to be a real location before
2248 * generate_code() time.
2251 fs_visitor::interp_reg(int location, int channel)
2253 int regnr = c->prog_data.urb_setup[location] * 2 + channel / 2;
2254 int stride = (channel & 1) * 4;
2256 assert(c->prog_data.urb_setup[location] != -1);
2258 return brw_vec1_grf(regnr, stride);
2261 /** Emits the interpolation for the varying inputs. */
2263 fs_visitor::emit_interpolation_setup_gen4()
2265 this->current_annotation = "compute pixel centers";
2266 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2267 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2268 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2269 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2271 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2272 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2274 this->current_annotation = "compute pixel deltas from v0";
2276 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2277 fs_reg(this, glsl_type::vec2_type);
2278 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2279 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2280 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2282 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2283 fs_reg(this, glsl_type::float_type);
2284 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2285 fs_reg(this, glsl_type::float_type);
2287 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2288 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2289 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2290 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2292 this->current_annotation = "compute pos.w and 1/pos.w";
2293 /* Compute wpos.w. It's always in our setup, since it's needed to
2294 * interpolate the other attributes.
2296 this->wpos_w = fs_reg(this, glsl_type::float_type);
2297 emit(FS_OPCODE_LINTERP, wpos_w,
2298 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2299 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2300 interp_reg(VARYING_SLOT_POS, 3));
2301 /* Compute the pixel 1/W value from wpos.w. */
2302 this->pixel_w = fs_reg(this, glsl_type::float_type);
2303 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2304 this->current_annotation = NULL;
2307 /** Emits the interpolation for the varying inputs. */
2309 fs_visitor::emit_interpolation_setup_gen6()
2311 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2313 /* If the pixel centers end up used, the setup is the same as for gen4. */
2314 this->current_annotation = "compute pixel centers";
2315 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2316 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2317 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2318 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2319 emit(ADD(int_pixel_x,
2320 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2321 fs_reg(brw_imm_v(0x10101010))));
2322 emit(ADD(int_pixel_y,
2323 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2324 fs_reg(brw_imm_v(0x11001100))));
2326 /* As of gen6, we can no longer mix float and int sources. We have
2327 * to turn the integer pixel centers into floats for their actual
2330 this->pixel_x = fs_reg(this, glsl_type::float_type);
2331 this->pixel_y = fs_reg(this, glsl_type::float_type);
2332 emit(MOV(this->pixel_x, int_pixel_x));
2333 emit(MOV(this->pixel_y, int_pixel_y));
2335 this->current_annotation = "compute pos.w";
2336 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2337 this->wpos_w = fs_reg(this, glsl_type::float_type);
2338 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2340 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2341 uint8_t reg = c->barycentric_coord_reg[i];
2342 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2343 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2346 this->current_annotation = NULL;
2350 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2352 int reg_width = dispatch_width / 8;
2354 fs_reg color = outputs[target];
2357 /* If there's no color data to be written, skip it. */
2358 if (color.file == BAD_FILE)
2361 color.reg_offset += index;
2363 if (dispatch_width == 8 || brw->gen >= 6) {
2364 /* SIMD8 write looks like:
2370 * gen6 SIMD16 DP write looks like:
2380 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2383 inst->saturate = c->key.clamp_fragment_color;
2385 /* pre-gen6 SIMD16 single source DP write looks like:
2395 if (brw->has_compr4) {
2396 /* By setting the high bit of the MRF register number, we
2397 * indicate that we want COMPR4 mode - instead of doing the
2398 * usual destination + 1 for the second half we get
2401 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2404 inst->saturate = c->key.clamp_fragment_color;
2406 push_force_uncompressed();
2407 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2409 inst->saturate = c->key.clamp_fragment_color;
2410 pop_force_uncompressed();
2412 push_force_sechalf();
2413 color.sechalf = true;
2414 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2416 inst->saturate = c->key.clamp_fragment_color;
2417 pop_force_sechalf();
2418 color.sechalf = false;
2424 fs_visitor::emit_fb_writes()
2426 this->current_annotation = "FB write header";
2427 bool header_present = true;
2428 /* We can potentially have a message length of up to 15, so we have to set
2429 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2433 int reg_width = dispatch_width / 8;
2434 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2435 bool src0_alpha_to_render_target = false;
2437 if (dispatch_width == 16 && do_dual_src) {
2438 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2439 do_dual_src = false;
2442 /* From the Sandy Bridge PRM, volume 4, page 198:
2444 * "Dispatched Pixel Enables. One bit per pixel indicating
2445 * which pixels were originally enabled when the thread was
2446 * dispatched. This field is only required for the end-of-
2447 * thread message and on all dual-source messages."
2449 if (brw->gen >= 6 &&
2450 !this->fp->UsesKill &&
2452 c->key.nr_color_regions == 1) {
2453 header_present = false;
2456 if (header_present) {
2457 src0_alpha_to_render_target = brw->gen >= 6 &&
2459 c->key.replicate_alpha;
2464 if (c->aa_dest_stencil_reg) {
2465 push_force_uncompressed();
2466 emit(MOV(fs_reg(MRF, nr++),
2467 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2468 pop_force_uncompressed();
2471 /* Reserve space for color. It'll be filled in per MRT below. */
2473 nr += 4 * reg_width;
2476 if (src0_alpha_to_render_target)
2479 if (c->source_depth_to_render_target) {
2480 if (brw->gen == 6 && dispatch_width == 16) {
2481 /* For outputting oDepth on gen6, SIMD8 writes have to be
2482 * used. This would require 8-wide moves of each half to
2483 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2484 * Just bail on doing so for now.
2486 fail("Missing support for simd16 depth writes on gen6\n");
2489 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2490 /* Hand over gl_FragDepth. */
2491 assert(this->frag_depth.file != BAD_FILE);
2492 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2494 /* Pass through the payload depth. */
2495 emit(MOV(fs_reg(MRF, nr),
2496 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2501 if (c->dest_depth_reg) {
2502 emit(MOV(fs_reg(MRF, nr),
2503 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2508 fs_reg src0 = this->outputs[0];
2509 fs_reg src1 = this->dual_src_output;
2511 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2513 for (int i = 0; i < 4; i++) {
2514 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2516 inst->saturate = c->key.clamp_fragment_color;
2519 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2521 for (int i = 0; i < 4; i++) {
2522 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2525 inst->saturate = c->key.clamp_fragment_color;
2528 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2529 emit_shader_time_end();
2531 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2533 inst->base_mrf = base_mrf;
2534 inst->mlen = nr - base_mrf;
2536 inst->header_present = header_present;
2538 c->prog_data.dual_src_blend = true;
2539 this->current_annotation = NULL;
2543 for (int target = 0; target < c->key.nr_color_regions; target++) {
2544 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2545 "FB write target %d",
2547 /* If src0_alpha_to_render_target is true, include source zero alpha
2548 * data in RenderTargetWrite message for targets > 0.
2550 int write_color_mrf = color_mrf;
2551 if (src0_alpha_to_render_target && target != 0) {
2553 fs_reg color = outputs[0];
2554 color.reg_offset += 3;
2556 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2558 inst->saturate = c->key.clamp_fragment_color;
2559 write_color_mrf = color_mrf + reg_width;
2562 for (unsigned i = 0; i < this->output_components[target]; i++)
2563 emit_color_write(target, i, write_color_mrf);
2566 if (target == c->key.nr_color_regions - 1) {
2569 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2570 emit_shader_time_end();
2573 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2574 inst->target = target;
2575 inst->base_mrf = base_mrf;
2576 if (src0_alpha_to_render_target && target == 0)
2577 inst->mlen = nr - base_mrf - reg_width;
2579 inst->mlen = nr - base_mrf;
2581 inst->header_present = header_present;
2584 if (c->key.nr_color_regions == 0) {
2585 /* Even if there's no color buffers enabled, we still need to send
2586 * alpha out the pipeline to our null renderbuffer to support
2587 * alpha-testing, alpha-to-coverage, and so on.
2589 emit_color_write(0, 3, color_mrf);
2591 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2592 emit_shader_time_end();
2594 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2595 inst->base_mrf = base_mrf;
2596 inst->mlen = nr - base_mrf;
2598 inst->header_present = header_present;
2601 this->current_annotation = NULL;
2605 fs_visitor::resolve_ud_negate(fs_reg *reg)
2607 if (reg->type != BRW_REGISTER_TYPE_UD ||
2611 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2612 emit(MOV(temp, *reg));
2617 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2619 if (rvalue->type != glsl_type::bool_type)
2622 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2623 emit(AND(temp, *reg, fs_reg(1)));
2627 fs_visitor::fs_visitor(struct brw_context *brw,
2628 struct brw_wm_compile *c,
2629 struct gl_shader_program *shader_prog,
2630 struct gl_fragment_program *fp,
2631 unsigned dispatch_width)
2632 : dispatch_width(dispatch_width)
2637 this->shader_prog = shader_prog;
2638 this->ctx = &brw->ctx;
2639 this->mem_ctx = ralloc_context(NULL);
2641 shader = (struct brw_shader *)
2642 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2645 this->failed = false;
2646 this->variable_ht = hash_table_ctor(0,
2647 hash_table_pointer_hash,
2648 hash_table_pointer_compare);
2650 memset(this->outputs, 0, sizeof(this->outputs));
2651 memset(this->output_components, 0, sizeof(this->output_components));
2652 this->first_non_payload_grf = 0;
2653 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2655 this->current_annotation = NULL;
2656 this->base_ir = NULL;
2658 this->virtual_grf_sizes = NULL;
2659 this->virtual_grf_count = 0;
2660 this->virtual_grf_array_size = 0;
2661 this->virtual_grf_start = NULL;
2662 this->virtual_grf_end = NULL;
2663 this->live_intervals_valid = false;
2665 this->params_remap = NULL;
2666 this->nr_params_remap = 0;
2668 this->force_uncompressed_stack = 0;
2669 this->force_sechalf_stack = 0;
2671 memset(&this->param_size, 0, sizeof(this->param_size));
2674 fs_visitor::~fs_visitor()
2676 ralloc_free(this->mem_ctx);
2677 hash_table_dtor(this->variable_ht);