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24 #include "brw_context.h"
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
27 #include "intel_reg.h"
30 * According to the latest documentation, any PIPE_CONTROL with the
31 * "Command Streamer Stall" bit set must also have another bit set,
32 * with five different options:
34 * - Render Target Cache Flush
36 * - Stall at Pixel Scoreboard
37 * - Post-Sync Operation
41 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
42 * in the past, but the choice is fairly arbitrary.
45 gen8_add_cs_stall_workaround_bits(uint32_t *flags)
47 uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
48 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
49 PIPE_CONTROL_WRITE_IMMEDIATE |
50 PIPE_CONTROL_WRITE_DEPTH_COUNT |
51 PIPE_CONTROL_WRITE_TIMESTAMP |
52 PIPE_CONTROL_STALL_AT_SCOREBOARD |
53 PIPE_CONTROL_DEPTH_STALL |
54 PIPE_CONTROL_DATA_CACHE_FLUSH;
56 /* If we're doing a CS stall, and don't already have one of the
57 * workaround bits set, add "Stall at Pixel Scoreboard."
59 if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0)
60 *flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
65 * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
66 * only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
68 * Note that the kernel does CS stalls between batches, so we only need
69 * to count them within a batch.
72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
74 if (brw->gen == 7 && !brw->is_haswell) {
75 if (flags & PIPE_CONTROL_CS_STALL) {
76 /* If we're doing a CS stall, reset the counter and carry on. */
77 brw->pipe_controls_since_last_cs_stall = 0;
81 /* If this is the fourth pipe control without a CS stall, do one now. */
82 if (++brw->pipe_controls_since_last_cs_stall == 4) {
83 brw->pipe_controls_since_last_cs_stall = 0;
84 return PIPE_CONTROL_CS_STALL;
91 * Emit a PIPE_CONTROL with various flushing flags.
93 * The caller is responsible for deciding what flags are appropriate for the
97 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
101 gen8_add_cs_stall_workaround_bits(&flags);
104 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
111 } else if (brw->gen >= 6) {
112 flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
115 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
123 OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
132 * Emit a PIPE_CONTROL that writes to a buffer object.
134 * \p flags should contain one of the following items:
135 * - PIPE_CONTROL_WRITE_IMMEDIATE
136 * - PIPE_CONTROL_WRITE_TIMESTAMP
137 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
140 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
141 drm_intel_bo *bo, uint32_t offset,
142 uint32_t imm_lower, uint32_t imm_upper)
146 gen8_add_cs_stall_workaround_bits(&flags);
149 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
151 OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
153 OUT_BATCH(imm_lower);
154 OUT_BATCH(imm_upper);
156 } else if (brw->gen >= 6) {
157 flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
159 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
160 * on later platforms. We always use PPGTT on Gen7+.
162 unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0;
165 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
167 OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
169 OUT_BATCH(imm_lower);
170 OUT_BATCH(imm_upper);
174 OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
175 OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
176 PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
177 OUT_BATCH(imm_lower);
178 OUT_BATCH(imm_upper);
184 * Restriction [DevSNB, DevIVB]:
186 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
187 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
188 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
189 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
190 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
191 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
192 * unless SW can otherwise guarantee that the pipeline from WM onwards is
193 * already flushed (e.g., via a preceding MI_FLUSH).
196 brw_emit_depth_stall_flushes(struct brw_context *brw)
198 assert(brw->gen >= 6 && brw->gen <= 9);
200 /* Starting on BDW, these pipe controls are unnecessary.
202 * WM HW will internally manage the draining pipe and flushing of the caches
203 * when this command is issued. The PIPE_CONTROL restrictions are removed.
208 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
209 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
210 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
214 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
215 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
216 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
217 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
218 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
219 * to be sent before any combination of VS associated 3DSTATE."
222 gen7_emit_vs_workaround_flush(struct brw_context *brw)
224 assert(brw->gen == 7);
225 brw_emit_pipe_control_write(brw,
226 PIPE_CONTROL_WRITE_IMMEDIATE
227 | PIPE_CONTROL_DEPTH_STALL,
228 brw->workaround_bo, 0,
234 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
237 gen7_emit_cs_stall_flush(struct brw_context *brw)
239 brw_emit_pipe_control_write(brw,
240 PIPE_CONTROL_CS_STALL
241 | PIPE_CONTROL_WRITE_IMMEDIATE,
242 brw->workaround_bo, 0,
248 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
249 * implementing two workarounds on gen6. From section 1.4.7.1
250 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
252 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
253 * produced by non-pipelined state commands), software needs to first
254 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
257 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
258 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
260 * And the workaround for these two requires this workaround first:
262 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
263 * BEFORE the pipe-control with a post-sync op and no write-cache
266 * And this last workaround is tricky because of the requirements on
267 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
270 * "1 of the following must also be set:
271 * - Render Target Cache Flush Enable ([12] of DW1)
272 * - Depth Cache Flush Enable ([0] of DW1)
273 * - Stall at Pixel Scoreboard ([1] of DW1)
274 * - Depth Stall ([13] of DW1)
275 * - Post-Sync Operation ([13] of DW1)
276 * - Notify Enable ([8] of DW1)"
278 * The cache flushes require the workaround flush that triggered this
279 * one, so we can't use it. Depth stall would trigger the same.
280 * Post-sync nonzero is what triggered this second workaround, so we
281 * can't use that one either. Notify enable is IRQs, which aren't
282 * really our business. That leaves only stall at scoreboard.
285 brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
287 brw_emit_pipe_control_flush(brw,
288 PIPE_CONTROL_CS_STALL |
289 PIPE_CONTROL_STALL_AT_SCOREBOARD);
291 brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
292 brw->workaround_bo, 0, 0, 0);
295 /* Emit a pipelined flush to either flush render and texture cache for
296 * reading from a FBO-drawn texture, or flush so that frontbuffer
297 * render appears on the screen in DRI1.
299 * This is also used for the always_flush_cache driconf debug option.
302 brw_emit_mi_flush(struct brw_context *brw)
304 if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
306 OUT_BATCH(MI_FLUSH_DW);
312 int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
315 /* Hardware workaround: SKL
317 * Emit Pipe Control with all bits set to zero before emitting
318 * a Pipe Control with VF Cache Invalidate set.
320 brw_emit_pipe_control_flush(brw, 0);
323 flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
324 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
325 PIPE_CONTROL_VF_CACHE_INVALIDATE |
326 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
327 PIPE_CONTROL_CS_STALL;
330 /* Hardware workaround: SNB B-Spec says:
332 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
333 * Flush Enable =1, a PIPE_CONTROL with any non-zero
334 * post-sync-op is required.
336 brw_emit_post_sync_nonzero_flush(brw);
339 brw_emit_pipe_control_flush(brw, flags);
344 brw_init_pipe_control(struct brw_context *brw,
345 const struct brw_device_info *devinfo)
347 if (devinfo->gen < 6)
350 /* We can't just use brw_state_batch to get a chunk of space for
351 * the gen6 workaround because it involves actually writing to
352 * the buffer, and the kernel doesn't let us write to the batch.
354 brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
355 "pipe_control workaround",
357 if (brw->workaround_bo == NULL)
360 brw->pipe_controls_since_last_cs_stall = 0;
366 brw_fini_pipe_control(struct brw_context *brw)
368 drm_intel_bo_unreference(brw->workaround_bo);