2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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28 #include "brw_defines.h"
29 #include "brw_context.h"
32 #include "brw_ir_allocator.h"
35 #define MAX_SAMPLER_MESSAGE_SIZE 11
36 #define MAX_VGRF_SIZE 16
39 struct backend_reg : private brw_reg
42 backend_reg(const struct brw_reg ®) : brw_reg(reg) {}
44 const brw_reg &as_brw_reg() const
46 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
47 assert(reg_offset == 0);
48 return static_cast<const brw_reg &>(*this);
53 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
54 assert(reg_offset == 0);
55 return static_cast<brw_reg &>(*this);
58 bool equals(const backend_reg &r) const;
62 bool is_negative_one() const;
64 bool is_accumulator() const;
65 bool in_range(const backend_reg &r, unsigned n) const;
68 * Offset within the virtual register.
70 * In the scalar backend, this is in units of a float per pixel for pre-
71 * register allocation registers (i.e., one register in SIMD8 mode and two
72 * registers in SIMD16 mode).
74 * For uniforms, this is in units of 1 float.
80 using brw_reg::negate;
82 using brw_reg::address_mode;
86 using brw_reg::swizzle;
87 using brw_reg::writemask;
88 using brw_reg::indirect_offset;
89 using brw_reg::vstride;
91 using brw_reg::hstride;
103 struct backend_instruction : public exec_node {
104 bool is_3src() const;
106 bool is_math() const;
107 bool is_control_flow() const;
108 bool is_commutative() const;
109 bool can_do_source_mods() const;
110 bool can_do_saturate() const;
111 bool can_do_cmod() const;
112 bool reads_accumulator_implicitly() const;
113 bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
115 void remove(bblock_t *block);
116 void insert_after(bblock_t *block, backend_instruction *inst);
117 void insert_before(bblock_t *block, backend_instruction *inst);
118 void insert_before(bblock_t *block, exec_list *list);
121 * True if the instruction has side effects other than writing to
122 * its destination registers. You are expected not to reorder or
123 * optimize these out unless you know what you are doing.
125 bool has_side_effects() const;
128 * True if the instruction might be affected by side effects of other
131 bool is_volatile() const;
133 struct backend_instruction {
134 struct exec_node link;
137 * Annotation for the generated IR. One of the two can be set.
140 const char *annotation;
143 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
144 uint8_t mlen; /**< SEND message length */
145 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
146 uint8_t target; /**< MRT target. */
147 uint8_t regs_written; /**< Number of registers written by the instruction. */
149 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
150 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
151 enum brw_predicate predicate;
152 bool predicate_inverse:1;
153 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
154 bool force_writemask_all:1;
158 bool shadow_compare:1;
160 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
161 * mod and predication.
163 unsigned flag_subreg:1;
165 /** The number of hardware registers used for a message header. */
171 enum instruction_scheduler_mode {
173 SCHEDULE_PRE_NON_LIFO,
178 struct backend_shader {
181 backend_shader(const struct brw_compiler *compiler,
184 const nir_shader *shader,
185 struct brw_stage_prog_data *stage_prog_data);
189 const struct brw_compiler *compiler;
190 void *log_data; /* Passed to compiler->*_log functions */
192 const struct brw_device_info * const devinfo;
193 const nir_shader *nir;
194 struct brw_stage_prog_data * const stage_prog_data;
196 /** ralloc context for temporary data used during compile */
200 * List of either fs_inst or vec4_instruction (inheriting from
201 * backend_instruction)
203 exec_list instructions;
207 gl_shader_stage stage;
209 const char *stage_name;
210 const char *stage_abbrev;
212 brw::simple_allocator alloc;
214 virtual void dump_instruction(backend_instruction *inst) = 0;
215 virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
216 virtual void dump_instructions();
217 virtual void dump_instructions(const char *name);
219 void calculate_cfg();
220 void invalidate_cfg();
222 virtual void invalidate_live_intervals() = 0;
225 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
227 void brw_setup_image_uniform_values(gl_shader_stage stage,
228 struct brw_stage_prog_data *stage_prog_data,
229 unsigned param_start_index,
230 const gl_uniform_storage *storage);
233 struct backend_shader;
234 #endif /* __cplusplus */
236 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
237 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
238 uint32_t brw_math_function(enum opcode op);
239 const char *brw_instruction_name(enum opcode op);
240 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
241 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
242 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
244 bool opt_predicated_break(struct backend_shader *s);
251 * Scratch data used when compiling a GLSL geometry shader.
253 struct brw_gs_compile
255 struct brw_gs_prog_key key;
256 struct brw_vue_map input_vue_map;
258 unsigned control_data_bits_per_vertex;
259 unsigned control_data_header_size_bits;
262 struct brw_compiler *
263 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
266 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
267 const struct brw_device_info *devinfo,
268 const struct gl_shader_program *shader_prog,
269 const struct gl_program *prog,
270 struct brw_stage_prog_data *stage_prog_data,
271 uint32_t next_binding_table_offset);
273 bool brw_vs_precompile(struct gl_context *ctx,
274 struct gl_shader_program *shader_prog,
275 struct gl_program *prog);
276 bool brw_tes_precompile(struct gl_context *ctx,
277 struct gl_shader_program *shader_prog,
278 struct gl_program *prog);
279 bool brw_gs_precompile(struct gl_context *ctx,
280 struct gl_shader_program *shader_prog,
281 struct gl_program *prog);
282 bool brw_fs_precompile(struct gl_context *ctx,
283 struct gl_shader_program *shader_prog,
284 struct gl_program *prog);
285 bool brw_cs_precompile(struct gl_context *ctx,
286 struct gl_shader_program *shader_prog,
287 struct gl_program *prog);
289 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog);
290 struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type);
292 int type_size_scalar(const struct glsl_type *type);
293 int type_size_vec4(const struct glsl_type *type);
294 int type_size_vec4_times_4(const struct glsl_type *type);