2 * Copyright © 2011 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #include "brw_dead_control_flow.h"
30 #include "main/macros.h"
31 #include "main/shaderobj.h"
32 #include "program/prog_print.h"
33 #include "program/prog_parameter.h"
36 #define MAX_INSTRUCTION (1 << 30)
43 * Common helper for constructing swizzles. When only a subset of
44 * channels of a vec4 are used, we don't want to reference the other
45 * channels, as that will tell optimization passes that those other
49 swizzle_for_size(int size)
51 static const unsigned size_swizzles[4] = {
52 BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
53 BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
54 BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
55 BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
58 assert((size >= 1) && (size <= 4));
59 return size_swizzles[size - 1];
65 memset(this, 0, sizeof(*this));
67 this->file = BAD_FILE;
70 src_reg::src_reg(register_file file, int reg, const glsl_type *type)
76 if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
77 this->swizzle = swizzle_for_size(type->vector_elements);
79 this->swizzle = SWIZZLE_XYZW;
82 /** Generic unset register constructor. */
88 src_reg::src_reg(float f)
93 this->type = BRW_REGISTER_TYPE_F;
97 src_reg::src_reg(uint32_t u)
102 this->type = BRW_REGISTER_TYPE_UD;
106 src_reg::src_reg(int32_t i)
111 this->type = BRW_REGISTER_TYPE_D;
115 src_reg::src_reg(dst_reg reg)
119 this->file = reg.file;
121 this->reg_offset = reg.reg_offset;
122 this->type = reg.type;
123 this->reladdr = reg.reladdr;
124 this->fixed_hw_reg = reg.fixed_hw_reg;
130 for (int i = 0; i < 4; i++) {
131 if (!(reg.writemask & (1 << i)))
134 swizzles[next_chan++] = last = i;
137 for (; next_chan < 4; next_chan++) {
138 swizzles[next_chan] = last;
141 this->swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
142 swizzles[2], swizzles[3]);
148 memset(this, 0, sizeof(*this));
149 this->file = BAD_FILE;
150 this->writemask = WRITEMASK_XYZW;
158 dst_reg::dst_reg(register_file file, int reg)
166 dst_reg::dst_reg(register_file file, int reg, const glsl_type *type,
173 this->type = brw_type_for_base_type(type);
174 this->writemask = writemask;
177 dst_reg::dst_reg(struct brw_reg reg)
182 this->fixed_hw_reg = reg;
185 dst_reg::dst_reg(src_reg reg)
189 this->file = reg.file;
191 this->reg_offset = reg.reg_offset;
192 this->type = reg.type;
193 /* How should we do writemasking when converting from a src_reg? It seems
194 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
195 * what about for src.wx? Just special-case src.xxxx for now.
197 if (reg.swizzle == BRW_SWIZZLE_XXXX)
198 this->writemask = WRITEMASK_X;
200 this->writemask = WRITEMASK_XYZW;
201 this->reladdr = reg.reladdr;
202 this->fixed_hw_reg = reg.fixed_hw_reg;
206 vec4_instruction::is_send_from_grf()
209 case SHADER_OPCODE_SHADER_TIME_ADD:
210 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
218 vec4_visitor::can_do_source_mods(vec4_instruction *inst)
220 if (brw->gen == 6 && inst->is_math())
223 if (inst->is_send_from_grf())
226 if (!inst->can_do_source_mods())
233 * Returns how many MRFs an opcode will write over.
235 * Note that this is not the 0 or 1 implied writes in an actual gen
236 * instruction -- the generate_* functions generate additional MOVs
240 vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
245 switch (inst->opcode) {
246 case SHADER_OPCODE_RCP:
247 case SHADER_OPCODE_RSQ:
248 case SHADER_OPCODE_SQRT:
249 case SHADER_OPCODE_EXP2:
250 case SHADER_OPCODE_LOG2:
251 case SHADER_OPCODE_SIN:
252 case SHADER_OPCODE_COS:
254 case SHADER_OPCODE_INT_QUOTIENT:
255 case SHADER_OPCODE_INT_REMAINDER:
256 case SHADER_OPCODE_POW:
258 case VS_OPCODE_URB_WRITE:
260 case VS_OPCODE_PULL_CONSTANT_LOAD:
262 case SHADER_OPCODE_GEN4_SCRATCH_READ:
264 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
266 case GS_OPCODE_URB_WRITE:
267 case GS_OPCODE_THREAD_END:
269 case SHADER_OPCODE_SHADER_TIME_ADD:
271 case SHADER_OPCODE_TEX:
272 case SHADER_OPCODE_TXL:
273 case SHADER_OPCODE_TXD:
274 case SHADER_OPCODE_TXF:
275 case SHADER_OPCODE_TXF_CMS:
276 case SHADER_OPCODE_TXF_MCS:
277 case SHADER_OPCODE_TXS:
278 case SHADER_OPCODE_TG4:
279 case SHADER_OPCODE_TG4_OFFSET:
280 return inst->header_present ? 1 : 0;
281 case SHADER_OPCODE_UNTYPED_ATOMIC:
282 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
285 assert(!"not reached");
291 src_reg::equals(src_reg *r)
293 return (file == r->file &&
295 reg_offset == r->reg_offset &&
297 negate == r->negate &&
299 swizzle == r->swizzle &&
300 !reladdr && !r->reladdr &&
301 memcmp(&fixed_hw_reg, &r->fixed_hw_reg,
302 sizeof(fixed_hw_reg)) == 0 &&
307 * Must be called after calculate_live_intervales() to remove unused
308 * writes to registers -- register allocation will fail otherwise
309 * because something deffed but not used won't be considered to
310 * interfere with other regs.
313 vec4_visitor::dead_code_eliminate()
315 bool progress = false;
318 calculate_live_intervals();
320 foreach_list_safe(node, &this->instructions) {
321 vec4_instruction *inst = (vec4_instruction *)node;
323 if (inst->dst.file == GRF && !inst->has_side_effects()) {
324 assert(this->virtual_grf_end[inst->dst.reg] >= pc);
325 if (this->virtual_grf_end[inst->dst.reg] == pc) {
326 /* Don't dead code eliminate instructions that write to the
327 * accumulator as a side-effect. Instead just set the destination
328 * to the null register to free it.
330 switch (inst->opcode) {
331 case BRW_OPCODE_ADDC:
332 case BRW_OPCODE_SUBB:
333 case BRW_OPCODE_MACH:
334 inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
348 invalidate_live_intervals();
354 vec4_visitor::split_uniform_registers()
356 /* Prior to this, uniforms have been in an array sized according to
357 * the number of vector uniforms present, sparsely filled (so an
358 * aggregate results in reg indices being skipped over). Now we're
359 * going to cut those aggregates up so each .reg index is one
360 * vector. The goal is to make elimination of unused uniform
361 * components easier later.
363 foreach_list(node, &this->instructions) {
364 vec4_instruction *inst = (vec4_instruction *)node;
366 for (int i = 0 ; i < 3; i++) {
367 if (inst->src[i].file != UNIFORM)
370 assert(!inst->src[i].reladdr);
372 inst->src[i].reg += inst->src[i].reg_offset;
373 inst->src[i].reg_offset = 0;
377 /* Update that everything is now vector-sized. */
378 for (int i = 0; i < this->uniforms; i++) {
379 this->uniform_size[i] = 1;
384 vec4_visitor::pack_uniform_registers()
386 bool uniform_used[this->uniforms];
387 int new_loc[this->uniforms];
388 int new_chan[this->uniforms];
390 memset(uniform_used, 0, sizeof(uniform_used));
391 memset(new_loc, 0, sizeof(new_loc));
392 memset(new_chan, 0, sizeof(new_chan));
394 /* Find which uniform vectors are actually used by the program. We
395 * expect unused vector elements when we've moved array access out
396 * to pull constants, and from some GLSL code generators like wine.
398 foreach_list(node, &this->instructions) {
399 vec4_instruction *inst = (vec4_instruction *)node;
401 for (int i = 0 ; i < 3; i++) {
402 if (inst->src[i].file != UNIFORM)
405 uniform_used[inst->src[i].reg] = true;
409 int new_uniform_count = 0;
411 /* Now, figure out a packing of the live uniform vectors into our
414 for (int src = 0; src < uniforms; src++) {
415 int size = this->uniform_vector_size[src];
417 if (!uniform_used[src]) {
418 this->uniform_vector_size[src] = 0;
423 /* Find the lowest place we can slot this uniform in. */
424 for (dst = 0; dst < src; dst++) {
425 if (this->uniform_vector_size[dst] + size <= 4)
434 new_chan[src] = this->uniform_vector_size[dst];
436 /* Move the references to the data */
437 for (int j = 0; j < size; j++) {
438 prog_data->param[dst * 4 + new_chan[src] + j] =
439 prog_data->param[src * 4 + j];
442 this->uniform_vector_size[dst] += size;
443 this->uniform_vector_size[src] = 0;
446 new_uniform_count = MAX2(new_uniform_count, dst + 1);
449 this->uniforms = new_uniform_count;
451 /* Now, update the instructions for our repacked uniforms. */
452 foreach_list(node, &this->instructions) {
453 vec4_instruction *inst = (vec4_instruction *)node;
455 for (int i = 0 ; i < 3; i++) {
456 int src = inst->src[i].reg;
458 if (inst->src[i].file != UNIFORM)
461 inst->src[i].reg = new_loc[src];
463 int sx = BRW_GET_SWZ(inst->src[i].swizzle, 0) + new_chan[src];
464 int sy = BRW_GET_SWZ(inst->src[i].swizzle, 1) + new_chan[src];
465 int sz = BRW_GET_SWZ(inst->src[i].swizzle, 2) + new_chan[src];
466 int sw = BRW_GET_SWZ(inst->src[i].swizzle, 3) + new_chan[src];
467 inst->src[i].swizzle = BRW_SWIZZLE4(sx, sy, sz, sw);
473 src_reg::is_zero() const
478 if (type == BRW_REGISTER_TYPE_F) {
486 src_reg::is_one() const
491 if (type == BRW_REGISTER_TYPE_F) {
499 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
501 * While GLSL IR also performs this optimization, we end up with it in
502 * our instruction stream for a couple of reasons. One is that we
503 * sometimes generate silly instructions, for example in array access
504 * where we'll generate "ADD offset, index, base" even if base is 0.
505 * The other is that GLSL IR's constant propagation doesn't track the
506 * components of aggregates, so some VS patterns (initialize matrix to
507 * 0, accumulate in vertex blending factors) end up breaking down to
508 * instructions involving 0.
511 vec4_visitor::opt_algebraic()
513 bool progress = false;
515 foreach_list(node, &this->instructions) {
516 vec4_instruction *inst = (vec4_instruction *)node;
518 switch (inst->opcode) {
520 if (inst->src[1].is_zero()) {
521 inst->opcode = BRW_OPCODE_MOV;
522 inst->src[1] = src_reg();
528 if (inst->src[1].is_zero()) {
529 inst->opcode = BRW_OPCODE_MOV;
530 switch (inst->src[0].type) {
531 case BRW_REGISTER_TYPE_F:
532 inst->src[0] = src_reg(0.0f);
534 case BRW_REGISTER_TYPE_D:
535 inst->src[0] = src_reg(0);
537 case BRW_REGISTER_TYPE_UD:
538 inst->src[0] = src_reg(0u);
541 assert(!"not reached");
542 inst->src[0] = src_reg(0.0f);
545 inst->src[1] = src_reg();
547 } else if (inst->src[1].is_one()) {
548 inst->opcode = BRW_OPCODE_MOV;
549 inst->src[1] = src_reg();
559 invalidate_live_intervals();
565 * Only a limited number of hardware registers may be used for push
566 * constants, so this turns access to the overflowed constants into
570 vec4_visitor::move_push_constants_to_pull_constants()
572 int pull_constant_loc[this->uniforms];
574 /* Only allow 32 registers (256 uniform components) as push constants,
575 * which is the limit on gen6.
577 int max_uniform_components = 32 * 8;
578 if (this->uniforms * 4 <= max_uniform_components)
581 /* Make some sort of choice as to which uniforms get sent to pull
582 * constants. We could potentially do something clever here like
583 * look for the most infrequently used uniform vec4s, but leave
586 for (int i = 0; i < this->uniforms * 4; i += 4) {
587 pull_constant_loc[i / 4] = -1;
589 if (i >= max_uniform_components) {
590 const float **values = &prog_data->param[i];
592 /* Try to find an existing copy of this uniform in the pull
593 * constants if it was part of an array access already.
595 for (unsigned int j = 0; j < prog_data->nr_pull_params; j += 4) {
598 for (matches = 0; matches < 4; matches++) {
599 if (prog_data->pull_param[j + matches] != values[matches])
604 pull_constant_loc[i / 4] = j / 4;
609 if (pull_constant_loc[i / 4] == -1) {
610 assert(prog_data->nr_pull_params % 4 == 0);
611 pull_constant_loc[i / 4] = prog_data->nr_pull_params / 4;
613 for (int j = 0; j < 4; j++) {
614 prog_data->pull_param[prog_data->nr_pull_params++] = values[j];
620 /* Now actually rewrite usage of the things we've moved to pull
623 foreach_list_safe(node, &this->instructions) {
624 vec4_instruction *inst = (vec4_instruction *)node;
626 for (int i = 0 ; i < 3; i++) {
627 if (inst->src[i].file != UNIFORM ||
628 pull_constant_loc[inst->src[i].reg] == -1)
631 int uniform = inst->src[i].reg;
633 dst_reg temp = dst_reg(this, glsl_type::vec4_type);
635 emit_pull_constant_load(inst, temp, inst->src[i],
636 pull_constant_loc[uniform]);
638 inst->src[i].file = temp.file;
639 inst->src[i].reg = temp.reg;
640 inst->src[i].reg_offset = temp.reg_offset;
641 inst->src[i].reladdr = NULL;
645 /* Repack push constants to remove the now-unused ones. */
646 pack_uniform_registers();
650 * Sets the dependency control fields on instructions after register
651 * allocation and before the generator is run.
653 * When you have a sequence of instructions like:
655 * DP4 temp.x vertex uniform[0]
656 * DP4 temp.y vertex uniform[0]
657 * DP4 temp.z vertex uniform[0]
658 * DP4 temp.w vertex uniform[0]
660 * The hardware doesn't know that it can actually run the later instructions
661 * while the previous ones are in flight, producing stalls. However, we have
662 * manual fields we can set in the instructions that let it do so.
665 vec4_visitor::opt_set_dependency_control()
667 vec4_instruction *last_grf_write[BRW_MAX_GRF];
668 uint8_t grf_channels_written[BRW_MAX_GRF];
669 vec4_instruction *last_mrf_write[BRW_MAX_GRF];
670 uint8_t mrf_channels_written[BRW_MAX_GRF];
672 cfg_t cfg(&instructions);
674 assert(prog_data->total_grf ||
675 !"Must be called after register allocation");
677 for (int i = 0; i < cfg.num_blocks; i++) {
678 bblock_t *bblock = cfg.blocks[i];
679 vec4_instruction *inst;
681 memset(last_grf_write, 0, sizeof(last_grf_write));
682 memset(last_mrf_write, 0, sizeof(last_mrf_write));
684 for (inst = (vec4_instruction *)bblock->start;
685 inst != (vec4_instruction *)bblock->end->next;
686 inst = (vec4_instruction *)inst->next) {
687 /* If we read from a register that we were doing dependency control
688 * on, don't do dependency control across the read.
690 for (int i = 0; i < 3; i++) {
691 int reg = inst->src[i].reg + inst->src[i].reg_offset;
692 if (inst->src[i].file == GRF) {
693 last_grf_write[reg] = NULL;
694 } else if (inst->src[i].file == HW_REG) {
695 memset(last_grf_write, 0, sizeof(last_grf_write));
698 assert(inst->src[i].file != MRF);
701 /* In the presence of send messages, totally interrupt dependency
702 * control. They're long enough that the chance of dependency
703 * control around them just doesn't matter.
706 memset(last_grf_write, 0, sizeof(last_grf_write));
707 memset(last_mrf_write, 0, sizeof(last_mrf_write));
711 /* It looks like setting dependency control on a predicated
712 * instruction hangs the GPU.
714 if (inst->predicate) {
715 memset(last_grf_write, 0, sizeof(last_grf_write));
716 memset(last_mrf_write, 0, sizeof(last_mrf_write));
720 /* Now, see if we can do dependency control for this instruction
721 * against a previous one writing to its destination.
723 int reg = inst->dst.reg + inst->dst.reg_offset;
724 if (inst->dst.file == GRF) {
725 if (last_grf_write[reg] &&
726 !(inst->dst.writemask & grf_channels_written[reg])) {
727 last_grf_write[reg]->no_dd_clear = true;
728 inst->no_dd_check = true;
730 grf_channels_written[reg] = 0;
733 last_grf_write[reg] = inst;
734 grf_channels_written[reg] |= inst->dst.writemask;
735 } else if (inst->dst.file == MRF) {
736 if (last_mrf_write[reg] &&
737 !(inst->dst.writemask & mrf_channels_written[reg])) {
738 last_mrf_write[reg]->no_dd_clear = true;
739 inst->no_dd_check = true;
741 mrf_channels_written[reg] = 0;
744 last_mrf_write[reg] = inst;
745 mrf_channels_written[reg] |= inst->dst.writemask;
746 } else if (inst->dst.reg == HW_REG) {
747 if (inst->dst.fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE)
748 memset(last_grf_write, 0, sizeof(last_grf_write));
749 if (inst->dst.fixed_hw_reg.file == BRW_MESSAGE_REGISTER_FILE)
750 memset(last_mrf_write, 0, sizeof(last_mrf_write));
757 vec4_instruction::can_reswizzle_dst(int dst_writemask,
761 /* If this instruction sets anything not referenced by swizzle, then we'd
762 * totally break it when we reswizzle.
764 if (dst.writemask & ~swizzle_mask)
773 /* Check if there happens to be no reswizzling required. */
774 for (int c = 0; c < 4; c++) {
775 int bit = 1 << BRW_GET_SWZ(swizzle, c);
776 /* Skip components of the swizzle not used by the dst. */
777 if (!(dst_writemask & (1 << c)))
780 /* We don't do the reswizzling yet, so just sanity check that we
791 * For any channels in the swizzle's source that were populated by this
792 * instruction, rewrite the instruction to put the appropriate result directly
795 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
798 vec4_instruction::reswizzle_dst(int dst_writemask, int swizzle)
800 int new_writemask = 0;
806 for (int c = 0; c < 4; c++) {
807 int bit = 1 << BRW_GET_SWZ(swizzle, c);
808 /* Skip components of the swizzle not used by the dst. */
809 if (!(dst_writemask & (1 << c)))
811 /* If we were populating this component, then populate the
812 * corresponding channel of the new dst.
814 if (dst.writemask & bit)
815 new_writemask |= (1 << c);
817 dst.writemask = new_writemask;
820 for (int c = 0; c < 4; c++) {
821 /* Skip components of the swizzle not used by the dst. */
822 if (!(dst_writemask & (1 << c)))
825 /* We don't do the reswizzling yet, so just sanity check that we
828 assert((1 << BRW_GET_SWZ(swizzle, c)) == (1 << c));
835 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
836 * just written and then MOVed into another reg and making the original write
837 * of the GRF write directly to the final destination instead.
840 vec4_visitor::opt_register_coalesce()
842 bool progress = false;
845 calculate_live_intervals();
847 foreach_list_safe(node, &this->instructions) {
848 vec4_instruction *inst = (vec4_instruction *)node;
853 if (inst->opcode != BRW_OPCODE_MOV ||
854 (inst->dst.file != GRF && inst->dst.file != MRF) ||
856 inst->src[0].file != GRF ||
857 inst->dst.type != inst->src[0].type ||
858 inst->src[0].abs || inst->src[0].negate || inst->src[0].reladdr)
861 bool to_mrf = (inst->dst.file == MRF);
863 /* Can't coalesce this GRF if someone else was going to
866 if (this->virtual_grf_end[inst->src[0].reg] > ip)
869 /* We need to check interference with the final destination between this
870 * instruction and the earliest instruction involved in writing the GRF
871 * we're eliminating. To do that, keep track of which of our source
872 * channels we've seen initialized.
874 bool chans_needed[4] = {false, false, false, false};
875 int chans_remaining = 0;
876 int swizzle_mask = 0;
877 for (int i = 0; i < 4; i++) {
878 int chan = BRW_GET_SWZ(inst->src[0].swizzle, i);
880 if (!(inst->dst.writemask & (1 << i)))
883 swizzle_mask |= (1 << chan);
885 if (!chans_needed[chan]) {
886 chans_needed[chan] = true;
891 /* Now walk up the instruction stream trying to see if we can rewrite
892 * everything writing to the temporary to write into the destination
895 vec4_instruction *scan_inst;
896 for (scan_inst = (vec4_instruction *)inst->prev;
897 scan_inst->prev != NULL;
898 scan_inst = (vec4_instruction *)scan_inst->prev) {
899 if (scan_inst->dst.file == GRF &&
900 scan_inst->dst.reg == inst->src[0].reg &&
901 scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
902 /* Found something writing to the reg we want to coalesce away. */
904 /* SEND instructions can't have MRF as a destination. */
909 /* gen6 math instructions must have the destination be
910 * GRF, so no compute-to-MRF for them.
912 if (scan_inst->is_math()) {
918 /* If we can't handle the swizzle, bail. */
919 if (!scan_inst->can_reswizzle_dst(inst->dst.writemask,
920 inst->src[0].swizzle,
925 /* Mark which channels we found unconditional writes for. */
926 if (!scan_inst->predicate) {
927 for (int i = 0; i < 4; i++) {
928 if (scan_inst->dst.writemask & (1 << i) &&
930 chans_needed[i] = false;
936 if (chans_remaining == 0)
940 /* We don't handle flow control here. Most computation of values
941 * that could be coalesced happens just before their use.
943 if (scan_inst->opcode == BRW_OPCODE_DO ||
944 scan_inst->opcode == BRW_OPCODE_WHILE ||
945 scan_inst->opcode == BRW_OPCODE_ELSE ||
946 scan_inst->opcode == BRW_OPCODE_ENDIF) {
950 /* You can't read from an MRF, so if someone else reads our MRF's
951 * source GRF that we wanted to rewrite, that stops us. If it's a
952 * GRF we're trying to coalesce to, we don't actually handle
953 * rewriting sources so bail in that case as well.
955 bool interfered = false;
956 for (int i = 0; i < 3; i++) {
957 if (scan_inst->src[i].file == GRF &&
958 scan_inst->src[i].reg == inst->src[0].reg &&
959 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
966 /* If somebody else writes our destination here, we can't coalesce
969 if (scan_inst->dst.file == inst->dst.file &&
970 scan_inst->dst.reg == inst->dst.reg) {
974 /* Check for reads of the register we're trying to coalesce into. We
975 * can't go rewriting instructions above that to put some other value
976 * in the register instead.
978 if (to_mrf && scan_inst->mlen > 0) {
979 if (inst->dst.reg >= scan_inst->base_mrf &&
980 inst->dst.reg < scan_inst->base_mrf + scan_inst->mlen) {
984 for (int i = 0; i < 3; i++) {
985 if (scan_inst->src[i].file == inst->dst.file &&
986 scan_inst->src[i].reg == inst->dst.reg &&
987 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
996 if (chans_remaining == 0) {
997 /* If we've made it here, we have an MOV we want to coalesce out, and
998 * a scan_inst pointing to the earliest instruction involved in
999 * computing the value. Now go rewrite the instruction stream
1003 while (scan_inst != inst) {
1004 if (scan_inst->dst.file == GRF &&
1005 scan_inst->dst.reg == inst->src[0].reg &&
1006 scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
1007 scan_inst->reswizzle_dst(inst->dst.writemask,
1008 inst->src[0].swizzle);
1009 scan_inst->dst.file = inst->dst.file;
1010 scan_inst->dst.reg = inst->dst.reg;
1011 scan_inst->dst.reg_offset = inst->dst.reg_offset;
1012 scan_inst->saturate |= inst->saturate;
1014 scan_inst = (vec4_instruction *)scan_inst->next;
1022 invalidate_live_intervals();
1028 * Splits virtual GRFs requesting more than one contiguous physical register.
1030 * We initially create large virtual GRFs for temporary structures, arrays,
1031 * and matrices, so that the dereference visitor functions can add reg_offsets
1032 * to work their way down to the actual member being accessed. But when it
1033 * comes to optimization, we'd like to treat each register as individual
1034 * storage if possible.
1036 * So far, the only thing that might prevent splitting is a send message from
1040 vec4_visitor::split_virtual_grfs()
1042 int num_vars = this->virtual_grf_count;
1043 int new_virtual_grf[num_vars];
1044 bool split_grf[num_vars];
1046 memset(new_virtual_grf, 0, sizeof(new_virtual_grf));
1048 /* Try to split anything > 0 sized. */
1049 for (int i = 0; i < num_vars; i++) {
1050 split_grf[i] = this->virtual_grf_sizes[i] != 1;
1053 /* Check that the instructions are compatible with the registers we're trying
1056 foreach_list(node, &this->instructions) {
1057 vec4_instruction *inst = (vec4_instruction *)node;
1059 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1062 if (inst->is_send_from_grf()) {
1063 for (int i = 0; i < 3; i++) {
1064 if (inst->src[i].file == GRF) {
1065 split_grf[inst->src[i].reg] = false;
1071 /* Allocate new space for split regs. Note that the virtual
1072 * numbers will be contiguous.
1074 for (int i = 0; i < num_vars; i++) {
1078 new_virtual_grf[i] = virtual_grf_alloc(1);
1079 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
1080 int reg = virtual_grf_alloc(1);
1081 assert(reg == new_virtual_grf[i] + j - 1);
1084 this->virtual_grf_sizes[i] = 1;
1087 foreach_list(node, &this->instructions) {
1088 vec4_instruction *inst = (vec4_instruction *)node;
1090 if (inst->dst.file == GRF && split_grf[inst->dst.reg] &&
1091 inst->dst.reg_offset != 0) {
1092 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
1093 inst->dst.reg_offset - 1);
1094 inst->dst.reg_offset = 0;
1096 for (int i = 0; i < 3; i++) {
1097 if (inst->src[i].file == GRF && split_grf[inst->src[i].reg] &&
1098 inst->src[i].reg_offset != 0) {
1099 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
1100 inst->src[i].reg_offset - 1);
1101 inst->src[i].reg_offset = 0;
1105 invalidate_live_intervals();
1109 vec4_visitor::dump_instruction(backend_instruction *be_inst)
1111 vec4_instruction *inst = (vec4_instruction *)be_inst;
1113 printf("%s", brw_instruction_name(inst->opcode));
1114 if (inst->conditional_mod) {
1115 printf("%s", conditional_modifier[inst->conditional_mod]);
1119 switch (inst->dst.file) {
1121 printf("vgrf%d.%d", inst->dst.reg, inst->dst.reg_offset);
1124 printf("m%d", inst->dst.reg);
1127 if (inst->dst.fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1128 switch (inst->dst.fixed_hw_reg.nr) {
1132 case BRW_ARF_ADDRESS:
1133 printf("a0.%d", inst->dst.fixed_hw_reg.subnr);
1135 case BRW_ARF_ACCUMULATOR:
1136 printf("acc%d", inst->dst.fixed_hw_reg.subnr);
1139 printf("f%d.%d", inst->dst.fixed_hw_reg.nr & 0xf,
1140 inst->dst.fixed_hw_reg.subnr);
1143 printf("arf%d.%d", inst->dst.fixed_hw_reg.nr & 0xf,
1144 inst->dst.fixed_hw_reg.subnr);
1148 printf("hw_reg%d", inst->dst.fixed_hw_reg.nr);
1150 if (inst->dst.fixed_hw_reg.subnr)
1151 printf("+%d", inst->dst.fixed_hw_reg.subnr);
1160 if (inst->dst.writemask != WRITEMASK_XYZW) {
1162 if (inst->dst.writemask & 1)
1164 if (inst->dst.writemask & 2)
1166 if (inst->dst.writemask & 4)
1168 if (inst->dst.writemask & 8)
1171 printf(":%s, ", brw_reg_type_letters(inst->dst.type));
1173 for (int i = 0; i < 3 && inst->src[i].file != BAD_FILE; i++) {
1174 if (inst->src[i].negate)
1176 if (inst->src[i].abs)
1178 switch (inst->src[i].file) {
1180 printf("vgrf%d", inst->src[i].reg);
1183 printf("attr%d", inst->src[i].reg);
1186 printf("u%d", inst->src[i].reg);
1189 switch (inst->src[i].type) {
1190 case BRW_REGISTER_TYPE_F:
1191 printf("%fF", inst->src[i].imm.f);
1193 case BRW_REGISTER_TYPE_D:
1194 printf("%dD", inst->src[i].imm.i);
1196 case BRW_REGISTER_TYPE_UD:
1197 printf("%uU", inst->src[i].imm.u);
1205 if (inst->src[i].fixed_hw_reg.negate)
1207 if (inst->src[i].fixed_hw_reg.abs)
1209 if (inst->src[i].fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1210 switch (inst->src[i].fixed_hw_reg.nr) {
1214 case BRW_ARF_ADDRESS:
1215 printf("a0.%d", inst->src[i].fixed_hw_reg.subnr);
1217 case BRW_ARF_ACCUMULATOR:
1218 printf("acc%d", inst->src[i].fixed_hw_reg.subnr);
1221 printf("f%d.%d", inst->src[i].fixed_hw_reg.nr & 0xf,
1222 inst->src[i].fixed_hw_reg.subnr);
1225 printf("arf%d.%d", inst->src[i].fixed_hw_reg.nr & 0xf,
1226 inst->src[i].fixed_hw_reg.subnr);
1230 printf("hw_reg%d", inst->src[i].fixed_hw_reg.nr);
1232 if (inst->src[i].fixed_hw_reg.subnr)
1233 printf("+%d", inst->src[i].fixed_hw_reg.subnr);
1234 if (inst->src[i].fixed_hw_reg.abs)
1245 if (virtual_grf_sizes[inst->src[i].reg] != 1)
1246 printf(".%d", inst->src[i].reg_offset);
1248 if (inst->src[i].file != IMM) {
1249 static const char *chans[4] = {"x", "y", "z", "w"};
1251 for (int c = 0; c < 4; c++) {
1252 printf("%s", chans[BRW_GET_SWZ(inst->src[i].swizzle, c)]);
1256 if (inst->src[i].abs)
1259 if (inst->src[i].file != IMM) {
1260 printf(":%s", reg_encoding[inst->src[i].type]);
1263 if (i < 2 && inst->src[i + 1].file != BAD_FILE)
1271 static inline struct brw_reg
1272 attribute_to_hw_reg(int attr, bool interleaved)
1275 return stride(brw_vec4_grf(attr / 2, (attr % 2) * 4), 0, 4, 1);
1277 return brw_vec8_grf(attr, 0);
1282 * Replace each register of type ATTR in this->instructions with a reference
1283 * to a fixed HW register.
1285 * If interleaved is true, then each attribute takes up half a register, with
1286 * register N containing attribute 2*N in its first half and attribute 2*N+1
1287 * in its second half (this corresponds to the payload setup used by geometry
1288 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1289 * false, then each attribute takes up a whole register, with register N
1290 * containing attribute N (this corresponds to the payload setup used by
1291 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1294 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
1297 foreach_list(node, &this->instructions) {
1298 vec4_instruction *inst = (vec4_instruction *)node;
1300 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1301 if (inst->dst.file == ATTR) {
1302 int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
1304 /* All attributes used in the shader need to have been assigned a
1305 * hardware register by the caller
1309 struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
1310 reg.type = inst->dst.type;
1311 reg.dw1.bits.writemask = inst->dst.writemask;
1313 inst->dst.file = HW_REG;
1314 inst->dst.fixed_hw_reg = reg;
1317 for (int i = 0; i < 3; i++) {
1318 if (inst->src[i].file != ATTR)
1321 int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
1323 /* All attributes used in the shader need to have been assigned a
1324 * hardware register by the caller
1328 struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
1329 reg.dw1.bits.swizzle = inst->src[i].swizzle;
1330 reg.type = inst->src[i].type;
1331 if (inst->src[i].abs)
1333 if (inst->src[i].negate)
1336 inst->src[i].file = HW_REG;
1337 inst->src[i].fixed_hw_reg = reg;
1343 vec4_vs_visitor::setup_attributes(int payload_reg)
1346 int attribute_map[VERT_ATTRIB_MAX + 1];
1347 memset(attribute_map, 0, sizeof(attribute_map));
1350 for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
1351 if (vs_prog_data->inputs_read & BITFIELD64_BIT(i)) {
1352 attribute_map[i] = payload_reg + nr_attributes;
1357 /* VertexID is stored by the VF as the last vertex element, but we
1358 * don't represent it with a flag in inputs_read, so we call it
1361 if (vs_prog_data->uses_vertexid) {
1362 attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
1366 lower_attributes_to_hw_regs(attribute_map, false /* interleaved */);
1368 /* The BSpec says we always have to read at least one thing from
1369 * the VF, and it appears that the hardware wedges otherwise.
1371 if (nr_attributes == 0)
1374 prog_data->urb_read_length = (nr_attributes + 1) / 2;
1376 unsigned vue_entries =
1377 MAX2(nr_attributes, prog_data->vue_map.num_slots);
1380 prog_data->urb_entry_size = ALIGN(vue_entries, 8) / 8;
1382 prog_data->urb_entry_size = ALIGN(vue_entries, 4) / 4;
1384 return payload_reg + nr_attributes;
1388 vec4_visitor::setup_uniforms(int reg)
1390 prog_data->dispatch_grf_start_reg = reg;
1392 /* The pre-gen6 VS requires that some push constants get loaded no
1393 * matter what, or the GPU would hang.
1395 if (brw->gen < 6 && this->uniforms == 0) {
1396 this->uniform_vector_size[this->uniforms] = 1;
1398 prog_data->param = reralloc(NULL, prog_data->param, const float *, 4);
1399 for (unsigned int i = 0; i < 4; i++) {
1400 unsigned int slot = this->uniforms * 4 + i;
1401 static float zero = 0.0;
1402 prog_data->param[slot] = &zero;
1408 reg += ALIGN(uniforms, 2) / 2;
1411 prog_data->nr_params = this->uniforms * 4;
1413 prog_data->curb_read_length = reg - prog_data->dispatch_grf_start_reg;
1419 vec4_vs_visitor::setup_payload(void)
1423 /* The payload always contains important data in g0, which contains
1424 * the URB handles that are passed on to the URB write at the end
1425 * of the thread. So, we always start push constants at g1.
1429 reg = setup_uniforms(reg);
1431 reg = setup_attributes(reg);
1433 this->first_non_payload_grf = reg;
1437 vec4_visitor::get_timestamp()
1439 assert(brw->gen >= 7);
1441 src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
1444 BRW_REGISTER_TYPE_UD,
1445 BRW_VERTICAL_STRIDE_0,
1447 BRW_HORIZONTAL_STRIDE_4,
1451 dst_reg dst = dst_reg(this, glsl_type::uvec4_type);
1453 vec4_instruction *mov = emit(MOV(dst, ts));
1454 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1455 * even if it's not enabled in the dispatch.
1457 mov->force_writemask_all = true;
1459 return src_reg(dst);
1463 vec4_visitor::emit_shader_time_begin()
1465 current_annotation = "shader time start";
1466 shader_start_time = get_timestamp();
1470 vec4_visitor::emit_shader_time_end()
1472 current_annotation = "shader time end";
1473 src_reg shader_end_time = get_timestamp();
1476 /* Check that there weren't any timestamp reset events (assuming these
1477 * were the only two timestamp reads that happened).
1479 src_reg reset_end = shader_end_time;
1480 reset_end.swizzle = BRW_SWIZZLE_ZZZZ;
1481 vec4_instruction *test = emit(AND(dst_null_d(), reset_end, src_reg(1u)));
1482 test->conditional_mod = BRW_CONDITIONAL_Z;
1484 emit(IF(BRW_PREDICATE_NORMAL));
1486 /* Take the current timestamp and get the delta. */
1487 shader_start_time.negate = true;
1488 dst_reg diff = dst_reg(this, glsl_type::uint_type);
1489 emit(ADD(diff, shader_start_time, shader_end_time));
1491 /* If there were no instructions between the two timestamp gets, the diff
1492 * is 2 cycles. Remove that overhead, so I can forget about that when
1493 * trying to determine the time taken for single instructions.
1495 emit(ADD(diff, src_reg(diff), src_reg(-2u)));
1497 emit_shader_time_write(st_base, src_reg(diff));
1498 emit_shader_time_write(st_written, src_reg(1u));
1499 emit(BRW_OPCODE_ELSE);
1500 emit_shader_time_write(st_reset, src_reg(1u));
1501 emit(BRW_OPCODE_ENDIF);
1505 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type,
1508 int shader_time_index =
1509 brw_get_shader_time_index(brw, shader_prog, prog, type);
1512 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, 2));
1514 dst_reg offset = dst;
1518 offset.type = BRW_REGISTER_TYPE_UD;
1519 emit(MOV(offset, src_reg(shader_time_index * SHADER_TIME_STRIDE)));
1521 time.type = BRW_REGISTER_TYPE_UD;
1522 emit(MOV(time, src_reg(value)));
1524 emit(SHADER_OPCODE_SHADER_TIME_ADD, dst_reg(), src_reg(dst));
1530 sanity_param_count = prog->Parameters->NumParameters;
1532 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
1533 emit_shader_time_begin();
1535 assign_common_binding_table_offsets(0);
1539 /* Generate VS IR for main(). (the visitor only descends into
1540 * functions called "main").
1543 visit_instructions(shader->base.ir);
1545 emit_program_code();
1549 if (key->userclip_active && !prog->UsesClipDistanceOut)
1550 setup_uniform_clipplane_values();
1554 /* Before any optimization, push array accesses out to scratch
1555 * space where we need them to be. This pass may allocate new
1556 * virtual GRFs, so we want to do it early. It also makes sure
1557 * that we have reladdr computations available for CSE, since we'll
1558 * often do repeated subexpressions for those.
1561 move_grf_array_access_to_scratch();
1562 move_uniform_array_access_to_pull_constants();
1564 /* The ARB_vertex_program frontend emits pull constant loads directly
1565 * rather than using reladdr, so we don't need to walk through all the
1566 * instructions looking for things to move. There isn't anything.
1568 * We do still need to split things to vec4 size.
1570 split_uniform_registers();
1572 pack_uniform_registers();
1573 move_push_constants_to_pull_constants();
1574 split_virtual_grfs();
1579 progress = dead_code_eliminate() || progress;
1580 progress = dead_control_flow_eliminate(this) || progress;
1581 progress = opt_copy_propagation() || progress;
1582 progress = opt_algebraic() || progress;
1583 progress = opt_register_coalesce() || progress;
1593 /* Debug of register spilling: Go spill everything. */
1594 const int grf_count = virtual_grf_count;
1595 float spill_costs[virtual_grf_count];
1596 bool no_spill[virtual_grf_count];
1597 evaluate_spill_costs(spill_costs, no_spill);
1598 for (int i = 0; i < grf_count; i++) {
1605 while (!reg_allocate()) {
1610 opt_schedule_instructions();
1612 opt_set_dependency_control();
1614 /* If any state parameters were appended, then ParameterValues could have
1615 * been realloced, in which case the driver uniform storage set up by
1616 * _mesa_associate_uniform_storage() would point to freed memory. Make
1617 * sure that didn't happen.
1619 assert(sanity_param_count == prog->Parameters->NumParameters);
1624 } /* namespace brw */
1629 * Compile a vertex shader.
1631 * Returns the final assembly and the program's size.
1634 brw_vs_emit(struct brw_context *brw,
1635 struct gl_shader_program *prog,
1636 struct brw_vs_compile *c,
1637 struct brw_vs_prog_data *prog_data,
1639 unsigned *final_assembly_size)
1641 bool start_busy = false;
1642 float start_time = 0;
1644 if (unlikely(brw->perf_debug)) {
1645 start_busy = (brw->batch.last_bo &&
1646 drm_intel_bo_busy(brw->batch.last_bo));
1647 start_time = get_time();
1650 struct brw_shader *shader = NULL;
1652 shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1654 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1656 printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1657 _mesa_print_ir(shader->base.ir, NULL);
1660 printf("ARB_vertex_program %d for native vertex shader\n",
1661 c->vp->program.Base.Id);
1662 _mesa_print_program(&c->vp->program.Base);
1666 vec4_vs_visitor v(brw, c, prog_data, prog, shader, mem_ctx);
1669 prog->LinkStatus = false;
1670 ralloc_strcat(&prog->InfoLog, v.fail_msg);
1673 _mesa_problem(NULL, "Failed to compile vertex shader: %s\n",
1679 const unsigned *assembly = NULL;
1680 if (brw->gen >= 8) {
1681 gen8_vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
1682 mem_ctx, INTEL_DEBUG & DEBUG_VS);
1683 assembly = g.generate_assembly(&v.instructions, final_assembly_size);
1685 vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base,
1686 mem_ctx, INTEL_DEBUG & DEBUG_VS);
1687 assembly = g.generate_assembly(&v.instructions, final_assembly_size);
1690 if (unlikely(brw->perf_debug) && shader) {
1691 if (shader->compiled_once) {
1692 brw_vs_debug_recompile(brw, prog, &c->key);
1694 if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
1695 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1696 (get_time() - start_time) * 1000);
1698 shader->compiled_once = true;
1706 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
1707 struct brw_vec4_prog_key *key,
1708 GLuint id, struct gl_program *prog)
1710 key->program_string_id = id;
1711 key->clamp_vertex_color = ctx->API == API_OPENGL_COMPAT;
1713 unsigned sampler_count = _mesa_fls(prog->SamplersUsed);
1714 for (unsigned i = 0; i < sampler_count; i++) {
1715 if (prog->ShadowSamplers & (1 << i)) {
1716 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1717 key->tex.swizzles[i] =
1718 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);
1720 /* Color sampler: assume no swizzling. */
1721 key->tex.swizzles[i] = SWIZZLE_XYZW;
1728 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
1729 const struct brw_vec4_prog_data *b)
1731 /* Compare all the struct (including the base) up to the pointers. */
1732 if (memcmp(a, b, offsetof(struct brw_vec4_prog_data, param)))
1735 if (memcmp(a->param, b->param, a->nr_params * sizeof(void *)))
1738 if (memcmp(a->pull_param, b->pull_param, a->nr_pull_params * sizeof(void *)))
1746 brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data)
1748 ralloc_free((void *)prog_data->param);
1749 ralloc_free((void *)prog_data->pull_param);