2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
34 #include "brw_ir_vec4.h"
39 #include "brw_context.h"
41 #include "intel_asm_annotation.h"
50 struct brw_vec4_compile {
51 GLuint last_scratch; /**< measured in 32-byte (register size) units */
59 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
60 struct brw_vue_prog_key *key,
61 GLuint id, struct gl_program *prog);
68 class vec4_live_variables;
71 * The vertex shader front-end.
73 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
74 * fixed-function) into VS IR.
76 class vec4_visitor : public backend_visitor
79 vec4_visitor(struct brw_context *brw,
80 struct brw_vec4_compile *c,
81 struct gl_program *prog,
82 const struct brw_vue_prog_key *key,
83 struct brw_vue_prog_data *prog_data,
84 struct gl_shader_program *shader_prog,
85 gl_shader_stage stage,
88 shader_time_shader_type st_base,
89 shader_time_shader_type st_written,
90 shader_time_shader_type st_reset);
95 return dst_reg(brw_null_reg());
100 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
103 dst_reg dst_null_ud()
105 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
108 struct brw_vec4_compile * const c;
109 const struct brw_vue_prog_key * const key;
110 struct brw_vue_prog_data * const prog_data;
111 unsigned int sanity_param_count;
117 * GLSL IR currently being processed, which is associated with our
118 * driver IR instructions for debugging purposes.
121 const char *current_annotation;
123 int first_non_payload_grf;
124 unsigned int max_grf;
125 int *virtual_grf_start;
126 int *virtual_grf_end;
127 brw::vec4_live_variables *live_intervals;
128 dst_reg userplane[MAX_CLIP_PLANES];
130 dst_reg *variable_storage(ir_variable *var);
132 void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
134 bool need_all_constants_in_pull_buffer;
137 * \name Visit methods
139 * As typical for the visitor pattern, there must be one \c visit method for
140 * each concrete subclass of \c ir_instruction. Virtual base classes within
141 * the hierarchy should not have \c visit methods.
144 virtual void visit(ir_variable *);
145 virtual void visit(ir_loop *);
146 virtual void visit(ir_loop_jump *);
147 virtual void visit(ir_function_signature *);
148 virtual void visit(ir_function *);
149 virtual void visit(ir_expression *);
150 virtual void visit(ir_swizzle *);
151 virtual void visit(ir_dereference_variable *);
152 virtual void visit(ir_dereference_array *);
153 virtual void visit(ir_dereference_record *);
154 virtual void visit(ir_assignment *);
155 virtual void visit(ir_constant *);
156 virtual void visit(ir_call *);
157 virtual void visit(ir_return *);
158 virtual void visit(ir_discard *);
159 virtual void visit(ir_texture *);
160 virtual void visit(ir_if *);
161 virtual void visit(ir_emit_vertex *);
162 virtual void visit(ir_end_primitive *);
167 /* Regs for vertex results. Generated at ir_variable visiting time
168 * for the ir->location's used.
170 dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
171 const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
173 int *uniform_vector_size;
174 int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
177 src_reg shader_start_time;
179 struct hash_table *variable_ht;
182 void fail(const char *msg, ...);
184 void setup_uniform_clipplane_values();
185 void setup_uniform_values(ir_variable *ir);
186 void setup_builtin_uniform_values(ir_variable *ir);
187 int setup_uniforms(int payload_reg);
188 bool reg_allocate_trivial();
190 void evaluate_spill_costs(float *spill_costs, bool *no_spill);
191 int choose_spill_reg(struct ra_graph *g);
192 void spill_reg(int spill_reg);
193 void move_grf_array_access_to_scratch();
194 void move_uniform_array_access_to_pull_constants();
195 void move_push_constants_to_pull_constants();
196 void split_uniform_registers();
197 void pack_uniform_registers();
198 void calculate_live_intervals();
199 void invalidate_live_intervals();
200 void split_virtual_grfs();
201 bool opt_vector_float();
202 bool opt_reduce_swizzle();
203 bool dead_code_eliminate();
204 int var_range_start(unsigned v, unsigned n) const;
205 int var_range_end(unsigned v, unsigned n) const;
206 bool virtual_grf_interferes(int a, int b);
207 bool opt_copy_propagation(bool do_constant_prop = true);
208 bool opt_cse_local(bblock_t *block);
210 bool opt_algebraic();
211 bool opt_register_coalesce();
212 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
213 void opt_set_dependency_control();
214 void opt_schedule_instructions();
216 vec4_instruction *emit(vec4_instruction *inst);
218 vec4_instruction *emit(enum opcode opcode);
219 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
220 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
221 const src_reg &src0);
222 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
223 const src_reg &src0, const src_reg &src1);
224 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
225 const src_reg &src0, const src_reg &src1,
226 const src_reg &src2);
228 vec4_instruction *emit_before(bblock_t *block,
229 vec4_instruction *inst,
230 vec4_instruction *new_inst);
232 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
233 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
234 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
256 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
257 enum brw_conditional_mod condition);
258 vec4_instruction *IF(src_reg src0, src_reg src1,
259 enum brw_conditional_mod condition);
260 vec4_instruction *IF(enum brw_predicate predicate);
278 int implied_mrf_writes(vec4_instruction *inst);
280 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
283 vec4_instruction *pre_rhs_inst,
284 vec4_instruction *last_rhs_inst);
286 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
287 void visit_instructions(const exec_list *list);
289 void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
290 src_reg src0, src_reg src1, src_reg one);
292 void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
293 void emit_if_gen6(ir_if *ir);
295 void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
296 src_reg src0, src_reg src1);
298 void emit_lrp(const dst_reg &dst,
299 const src_reg &x, const src_reg &y, const src_reg &a);
301 void emit_block_move(dst_reg *dst, src_reg *src,
302 const struct glsl_type *type, brw_predicate predicate);
304 void emit_constant_values(dst_reg *dst, ir_constant *value);
307 * Emit the correct dot-product instruction for the type of arguments
309 void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
311 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
312 dst_reg dst, src_reg src0);
314 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
315 dst_reg dst, src_reg src0, src_reg src1);
317 src_reg fix_3src_operand(src_reg src);
319 void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
320 const src_reg &src1 = src_reg());
321 src_reg fix_math_operand(src_reg src);
323 void emit_pack_half_2x16(dst_reg dst, src_reg src0);
324 void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
325 void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
326 void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
327 void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
328 void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
330 uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
331 src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
332 void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
333 void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
335 void emit_ndc_computation();
336 void emit_psiz_and_flags(dst_reg reg);
337 void emit_clip_distances(dst_reg reg, int offset);
338 vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
339 void emit_urb_slot(dst_reg reg, int varying);
341 void emit_shader_time_begin();
342 void emit_shader_time_end();
343 void emit_shader_time_write(enum shader_time_shader_type type,
346 void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
347 dst_reg dst, src_reg offset, src_reg src0,
350 void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
353 src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
354 src_reg *reladdr, int reg_offset);
355 src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
356 src_reg *reladdr, int reg_offset);
357 void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
361 void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
363 void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
367 void emit_pull_constant_load_reg(dst_reg dst,
370 bblock_t *before_block,
371 vec4_instruction *before_inst);
372 src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
373 vec4_instruction *inst, src_reg src);
375 bool try_emit_mad(ir_expression *ir);
376 bool try_emit_b2f_of_compare(ir_expression *ir);
377 void resolve_ud_negate(src_reg *reg);
378 void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
380 src_reg get_timestamp();
382 bool process_move_condition(ir_rvalue *ir);
384 void dump_instruction(backend_instruction *inst);
385 void dump_instruction(backend_instruction *inst, FILE *file);
387 void visit_atomic_counter_intrinsic(ir_call *ir);
391 void lower_attributes_to_hw_regs(const int *attribute_map,
393 void setup_payload_interference(struct ra_graph *g, int first_payload_node,
395 virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
396 virtual void assign_binding_table_offsets();
397 virtual void setup_payload() = 0;
398 virtual void emit_prolog() = 0;
399 virtual void emit_program_code() = 0;
400 virtual void emit_thread_end() = 0;
401 virtual void emit_urb_write_header(int mrf) = 0;
402 virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
403 virtual int compute_array_stride(ir_dereference_array *ir);
407 * If true, then register allocation should fail instead of spilling.
409 const bool no_spills;
411 const shader_time_shader_type st_base;
412 const shader_time_shader_type st_written;
413 const shader_time_shader_type st_reset;
418 * The vertex shader code generator.
420 * Translates VS IR to actual i965 assembly code.
425 vec4_generator(struct brw_context *brw,
426 struct gl_shader_program *shader_prog,
427 struct gl_program *prog,
428 struct brw_vue_prog_data *prog_data,
431 const char *stage_name,
432 const char *stage_abbrev);
435 const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
438 void generate_code(const cfg_t *cfg);
440 void generate_math1_gen4(vec4_instruction *inst,
443 void generate_math2_gen4(vec4_instruction *inst,
446 struct brw_reg src1);
447 void generate_math_gen6(vec4_instruction *inst,
450 struct brw_reg src1);
452 void generate_tex(vec4_instruction *inst,
455 struct brw_reg sampler_index);
457 void generate_vs_urb_write(vec4_instruction *inst);
458 void generate_gs_urb_write(vec4_instruction *inst);
459 void generate_gs_urb_write_allocate(vec4_instruction *inst);
460 void generate_gs_thread_end(vec4_instruction *inst);
461 void generate_gs_set_write_offset(struct brw_reg dst,
463 struct brw_reg src1);
464 void generate_gs_set_vertex_count(struct brw_reg dst,
466 void generate_gs_svb_write(vec4_instruction *inst,
469 struct brw_reg src1);
470 void generate_gs_svb_set_destination_index(vec4_instruction *inst,
473 void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
474 void generate_gs_prepare_channel_masks(struct brw_reg dst);
475 void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
476 void generate_gs_get_instance_id(struct brw_reg dst);
477 void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
480 struct brw_reg src2);
481 void generate_gs_ff_sync(vec4_instruction *inst,
484 struct brw_reg src1);
485 void generate_gs_set_primitive_id(struct brw_reg dst);
486 void generate_oword_dual_block_offsets(struct brw_reg m1,
487 struct brw_reg index);
488 void generate_scratch_write(vec4_instruction *inst,
491 struct brw_reg index);
492 void generate_scratch_read(vec4_instruction *inst,
494 struct brw_reg index);
495 void generate_pull_constant_load(vec4_instruction *inst,
497 struct brw_reg index,
498 struct brw_reg offset);
499 void generate_pull_constant_load_gen7(vec4_instruction *inst,
501 struct brw_reg surf_index,
502 struct brw_reg offset);
503 void generate_unpack_flags(struct brw_reg dst);
505 void generate_untyped_atomic(vec4_instruction *inst,
507 struct brw_reg atomic_op,
508 struct brw_reg surf_index);
510 void generate_untyped_surface_read(vec4_instruction *inst,
512 struct brw_reg surf_index);
514 struct brw_context *brw;
516 struct brw_compile *p;
518 struct gl_shader_program *shader_prog;
519 const struct gl_program *prog;
521 struct brw_vue_prog_data *prog_data;
524 const char *stage_name;
525 const char *stage_abbrev;
526 const bool debug_flag;
529 } /* namespace brw */
530 #endif /* __cplusplus */
532 #endif /* BRW_VEC4_H */