2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
34 #include "brw_context.h"
45 swizzle_for_size(int size);
48 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
49 GRF = BRW_GENERAL_REGISTER_FILE,
50 MRF = BRW_MESSAGE_REGISTER_FILE,
51 IMM = BRW_IMMEDIATE_VALUE,
52 HW_REG, /* a struct brw_reg */
54 UNIFORM, /* prog_data->params[hw_reg] */
61 /** Register file: ARF, GRF, MRF, IMM. */
62 enum register_file file;
63 /** virtual register number. 0 = fixed hw reg */
65 /** Offset within the virtual register. */
67 /** Register type. BRW_REGISTER_TYPE_* */
69 struct brw_reg fixed_hw_reg;
71 /** Value for file == BRW_IMMMEDIATE_FILE */
79 class src_reg : public reg
82 /* Callers of this ralloc-based new need not call delete. It's
83 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
84 static void* operator new(size_t size, void *ctx)
88 node = ralloc_size(ctx, size);
96 src_reg(register_file file, int reg, const glsl_type *type);
102 bool equals(src_reg *r);
103 bool is_zero() const;
106 src_reg(class vec4_visitor *v, const struct glsl_type *type);
108 explicit src_reg(dst_reg reg);
110 GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
117 class dst_reg : public reg
120 /* Callers of this ralloc-based new need not call delete. It's
121 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
122 static void* operator new(size_t size, void *ctx)
126 node = ralloc_size(ctx, size);
127 assert(node != NULL);
135 dst_reg(register_file file, int reg);
136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
137 dst_reg(struct brw_reg reg);
138 dst_reg(class vec4_visitor *v, const struct glsl_type *type);
140 explicit dst_reg(src_reg reg);
142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
147 class vec4_instruction : public backend_instruction {
149 /* Callers of this ralloc-based new need not call delete. It's
150 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
151 static void* operator new(size_t size, void *ctx)
155 node = rzalloc_size(ctx, size);
156 assert(node != NULL);
161 vec4_instruction(vec4_visitor *v, enum opcode opcode,
162 dst_reg dst = dst_reg(),
163 src_reg src0 = src_reg(),
164 src_reg src1 = src_reg(),
165 src_reg src2 = src_reg());
167 struct brw_reg get_dst(void);
168 struct brw_reg get_src(int i);
174 bool force_writemask_all;
175 bool no_dd_clear, no_dd_check;
177 int conditional_mod; /**< BRW_CONDITIONAL_* */
180 uint32_t texture_offset; /**< Texture Offset bitfield */
181 int target; /**< MRT target. */
186 int mlen; /**< SEND message length */
187 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
189 uint32_t offset; /* spill/unspill offset */
191 * Annotation for the generated IR. One of the two can be set.
194 const char *annotation;
198 bool is_send_from_grf();
199 bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
200 void reswizzle_dst(int dst_writemask, int swizzle);
204 * The vertex shader front-end.
206 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
207 * fixed-function) into VS IR.
209 class vec4_visitor : public backend_visitor
212 vec4_visitor(struct brw_context *brw,
213 struct brw_vec4_compile *c,
214 struct gl_program *prog,
215 const struct brw_vec4_prog_key *key,
216 struct brw_vec4_prog_data *prog_data,
217 struct gl_shader_program *shader_prog,
218 struct brw_shader *shader,
224 return dst_reg(brw_null_reg());
229 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
232 struct gl_program *prog;
233 struct brw_vec4_compile *c;
234 const struct brw_vec4_prog_key *key;
235 struct brw_vec4_prog_data *prog_data;
236 unsigned int sanity_param_count;
242 * GLSL IR currently being processed, which is associated with our
243 * driver IR instructions for debugging purposes.
246 const char *current_annotation;
248 int *virtual_grf_sizes;
249 int virtual_grf_count;
250 int virtual_grf_array_size;
251 int first_non_payload_grf;
252 unsigned int max_grf;
253 int *virtual_grf_def;
254 int *virtual_grf_use;
255 dst_reg userplane[MAX_CLIP_PLANES];
258 * This is the size to be used for an array with an element per
261 int virtual_grf_reg_count;
262 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
263 int *virtual_grf_reg_map;
265 bool live_intervals_valid;
267 dst_reg *variable_storage(ir_variable *var);
269 void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
271 bool need_all_constants_in_pull_buffer;
274 * \name Visit methods
276 * As typical for the visitor pattern, there must be one \c visit method for
277 * each concrete subclass of \c ir_instruction. Virtual base classes within
278 * the hierarchy should not have \c visit methods.
281 virtual void visit(ir_variable *);
282 virtual void visit(ir_loop *);
283 virtual void visit(ir_loop_jump *);
284 virtual void visit(ir_function_signature *);
285 virtual void visit(ir_function *);
286 virtual void visit(ir_expression *);
287 virtual void visit(ir_swizzle *);
288 virtual void visit(ir_dereference_variable *);
289 virtual void visit(ir_dereference_array *);
290 virtual void visit(ir_dereference_record *);
291 virtual void visit(ir_assignment *);
292 virtual void visit(ir_constant *);
293 virtual void visit(ir_call *);
294 virtual void visit(ir_return *);
295 virtual void visit(ir_discard *);
296 virtual void visit(ir_texture *);
297 virtual void visit(ir_if *);
302 /* Regs for vertex results. Generated at ir_variable visiting time
303 * for the ir->location's used.
305 dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
306 const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
307 int uniform_size[MAX_UNIFORMS];
308 int uniform_vector_size[MAX_UNIFORMS];
311 src_reg shader_start_time;
313 struct hash_table *variable_ht;
316 void fail(const char *msg, ...);
318 int virtual_grf_alloc(int size);
319 void setup_uniform_clipplane_values();
320 void setup_uniform_values(ir_variable *ir);
321 void setup_builtin_uniform_values(ir_variable *ir);
322 int setup_uniforms(int payload_reg);
323 void setup_payload();
324 bool reg_allocate_trivial();
326 void evaluate_spill_costs(float *spill_costs, bool *no_spill);
327 int choose_spill_reg(struct ra_graph *g);
328 void spill_reg(int spill_reg);
329 void move_grf_array_access_to_scratch();
330 void move_uniform_array_access_to_pull_constants();
331 void move_push_constants_to_pull_constants();
332 void split_uniform_registers();
333 void pack_uniform_registers();
334 void calculate_live_intervals();
335 void split_virtual_grfs();
336 bool dead_code_eliminate();
337 bool virtual_grf_interferes(int a, int b);
338 bool opt_copy_propagation();
339 bool opt_algebraic();
340 bool opt_register_coalesce();
341 void opt_set_dependency_control();
343 bool can_do_source_mods(vec4_instruction *inst);
345 vec4_instruction *emit(vec4_instruction *inst);
347 vec4_instruction *emit(enum opcode opcode);
349 vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
351 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
352 src_reg src0, src_reg src1);
354 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
355 src_reg src0, src_reg src1, src_reg src2);
357 vec4_instruction *emit_before(vec4_instruction *inst,
358 vec4_instruction *new_inst);
360 vec4_instruction *MOV(dst_reg dst, src_reg src0);
361 vec4_instruction *NOT(dst_reg dst, src_reg src0);
362 vec4_instruction *RNDD(dst_reg dst, src_reg src0);
363 vec4_instruction *RNDE(dst_reg dst, src_reg src0);
364 vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
365 vec4_instruction *FRC(dst_reg dst, src_reg src0);
366 vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
367 vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
368 vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
369 vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
370 vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
371 vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
372 vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
373 vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
374 vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
375 vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
376 vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
377 vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
378 vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
379 vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
380 vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
381 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
383 vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
384 vec4_instruction *IF(uint32_t predicate);
385 vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
386 vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
387 vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
389 int implied_mrf_writes(vec4_instruction *inst);
391 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
394 vec4_instruction *pre_rhs_inst,
395 vec4_instruction *last_rhs_inst);
397 bool try_copy_propagation(struct intel_context *intel,
398 vec4_instruction *inst, int arg,
401 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
402 void visit_instructions(const exec_list *list);
404 void emit_vp_sop(uint32_t condmod, dst_reg dst,
405 src_reg src0, src_reg src1, src_reg one);
407 void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
408 void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
409 void emit_if_gen6(ir_if *ir);
411 void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
413 void emit_block_move(dst_reg *dst, src_reg *src,
414 const struct glsl_type *type, uint32_t predicate);
416 void emit_constant_values(dst_reg *dst, ir_constant *value);
419 * Emit the correct dot-product instruction for the type of arguments
421 void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
423 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
424 dst_reg dst, src_reg src0);
426 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
427 dst_reg dst, src_reg src0, src_reg src1);
429 void emit_scs(ir_instruction *ir, enum prog_opcode op,
430 dst_reg dst, const src_reg &src);
432 void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
433 void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
434 void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
435 void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
436 void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
437 void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
438 src_reg fix_math_operand(src_reg src);
440 void emit_pack_half_2x16(dst_reg dst, src_reg src0);
441 void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
443 void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
445 void emit_ndc_computation();
446 void emit_psiz_and_flags(struct brw_reg reg);
447 void emit_clip_distances(struct brw_reg reg, int offset);
448 void emit_generic_urb_slot(dst_reg reg, int varying);
449 void emit_urb_slot(int mrf, int varying);
451 void emit_shader_time_begin();
452 void emit_shader_time_end();
453 void emit_shader_time_write(enum shader_time_shader_type type,
456 src_reg get_scratch_offset(vec4_instruction *inst,
457 src_reg *reladdr, int reg_offset);
458 src_reg get_pull_constant_offset(vec4_instruction *inst,
459 src_reg *reladdr, int reg_offset);
460 void emit_scratch_read(vec4_instruction *inst,
464 void emit_scratch_write(vec4_instruction *inst,
466 void emit_pull_constant_load(vec4_instruction *inst,
471 bool try_emit_sat(ir_expression *ir);
472 void resolve_ud_negate(src_reg *reg);
474 src_reg get_timestamp();
476 bool process_move_condition(ir_rvalue *ir);
478 void dump_instruction(vec4_instruction *inst);
479 void dump_instructions();
483 void lower_attributes_to_hw_regs(const int *attribute_map);
484 virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
485 virtual int setup_attributes(int payload_reg) = 0;
486 virtual void emit_prolog() = 0;
487 virtual void emit_program_code() = 0;
488 virtual void emit_thread_end() = 0;
489 virtual void emit_urb_write_header(int mrf) = 0;
490 virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
491 virtual int compute_array_stride(ir_dereference_array *ir);
494 class vec4_vs_visitor : public vec4_visitor
497 vec4_vs_visitor(struct brw_context *brw,
498 struct brw_vs_compile *vs_compile,
499 struct brw_vs_prog_data *vs_prog_data,
500 struct gl_shader_program *prog,
501 struct brw_shader *shader,
505 virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
506 virtual int setup_attributes(int payload_reg);
507 virtual void emit_prolog();
508 virtual void emit_program_code();
509 virtual void emit_thread_end();
510 virtual void emit_urb_write_header(int mrf);
511 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
514 void setup_vp_regs();
515 dst_reg get_vp_dst_reg(const prog_dst_register &dst);
516 src_reg get_vp_src_reg(const prog_src_register &src);
518 struct brw_vs_compile * const vs_compile;
519 struct brw_vs_prog_data * const vs_prog_data;
520 src_reg *vp_temp_regs;
525 * The vertex shader code generator.
527 * Translates VS IR to actual i965 assembly code.
532 vec4_generator(struct brw_context *brw,
533 struct gl_shader_program *shader_prog,
534 struct gl_program *prog,
538 const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
541 void generate_code(exec_list *instructions);
542 void generate_vec4_instruction(vec4_instruction *inst,
544 struct brw_reg *src);
546 void generate_math1_gen4(vec4_instruction *inst,
549 void generate_math1_gen6(vec4_instruction *inst,
552 void generate_math2_gen4(vec4_instruction *inst,
555 struct brw_reg src1);
556 void generate_math2_gen6(vec4_instruction *inst,
559 struct brw_reg src1);
560 void generate_math2_gen7(vec4_instruction *inst,
563 struct brw_reg src1);
565 void generate_tex(vec4_instruction *inst,
569 void generate_urb_write(vec4_instruction *inst);
570 void generate_oword_dual_block_offsets(struct brw_reg m1,
571 struct brw_reg index);
572 void generate_scratch_write(vec4_instruction *inst,
575 struct brw_reg index);
576 void generate_scratch_read(vec4_instruction *inst,
578 struct brw_reg index);
579 void generate_pull_constant_load(vec4_instruction *inst,
581 struct brw_reg index,
582 struct brw_reg offset);
583 void generate_pull_constant_load_gen7(vec4_instruction *inst,
585 struct brw_reg surf_index,
586 struct brw_reg offset);
588 struct brw_context *brw;
589 struct intel_context *intel;
590 struct gl_context *ctx;
592 struct brw_compile *p;
594 struct gl_shader_program *shader_prog;
595 struct gl_shader *shader;
596 const struct gl_program *prog;
601 } /* namespace brw */
603 #endif /* BRW_VEC4_H */