2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
37 #include "brw_context.h"
42 #include "gen8_generator.h"
48 struct brw_vec4_compile {
49 GLuint last_scratch; /**< measured in 32-byte (register size) units */
53 struct brw_vec4_prog_key {
54 GLuint program_string_id;
57 * True if at least one clip flag is enabled, regardless of whether the
58 * shader uses clip planes or gl_ClipDistance.
60 GLuint userclip_active:1;
63 * How many user clipping planes are being uploaded to the vertex shader as
66 GLuint nr_userclip_plane_consts:4;
68 GLuint clamp_vertex_color:1;
70 struct brw_sampler_prog_key_data tex;
79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
80 struct brw_vec4_prog_key *key,
81 GLuint id, struct gl_program *prog);
91 swizzle_for_size(int size);
96 /** Register file: GRF, MRF, IMM. */
97 enum register_file file;
98 /** virtual register number. 0 = fixed hw reg */
100 /** Offset within the virtual register. */
102 /** Register type. BRW_REGISTER_TYPE_* */
104 struct brw_reg fixed_hw_reg;
106 /** Value for file == BRW_IMMMEDIATE_FILE */
114 class src_reg : public reg
117 DECLARE_RALLOC_CXX_OPERATORS(src_reg)
121 src_reg(register_file file, int reg, const glsl_type *type);
126 src_reg(struct brw_reg reg);
128 bool equals(src_reg *r);
129 bool is_zero() const;
132 src_reg(class vec4_visitor *v, const struct glsl_type *type);
134 explicit src_reg(dst_reg reg);
136 GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
143 class dst_reg : public reg
146 DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
151 dst_reg(register_file file, int reg);
152 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
153 dst_reg(struct brw_reg reg);
154 dst_reg(class vec4_visitor *v, const struct glsl_type *type);
156 explicit dst_reg(src_reg reg);
158 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
164 with_writemask(dst_reg const &r, int mask);
166 class vec4_instruction : public backend_instruction {
168 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
170 vec4_instruction(vec4_visitor *v, enum opcode opcode,
171 dst_reg dst = dst_reg(),
172 src_reg src0 = src_reg(),
173 src_reg src1 = src_reg(),
174 src_reg src2 = src_reg());
176 struct brw_reg get_dst(void);
177 struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
183 bool force_writemask_all;
184 bool no_dd_clear, no_dd_check;
186 int conditional_mod; /**< BRW_CONDITIONAL_* */
189 uint32_t texture_offset; /**< Texture Offset bitfield */
190 int target; /**< MRT target. */
193 enum brw_urb_write_flags urb_write_flags;
195 int mlen; /**< SEND message length */
196 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
198 uint32_t offset; /* spill/unspill offset */
200 * Annotation for the generated IR. One of the two can be set.
203 const char *annotation;
205 bool is_send_from_grf();
206 bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
207 void reswizzle_dst(int dst_writemask, int swizzle);
209 bool depends_on_flags()
211 return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
216 * The vertex shader front-end.
218 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
219 * fixed-function) into VS IR.
221 class vec4_visitor : public backend_visitor
224 vec4_visitor(struct brw_context *brw,
225 struct brw_vec4_compile *c,
226 struct gl_program *prog,
227 const struct brw_vec4_prog_key *key,
228 struct brw_vec4_prog_data *prog_data,
229 struct gl_shader_program *shader_prog,
230 struct brw_shader *shader,
234 shader_time_shader_type st_base,
235 shader_time_shader_type st_written,
236 shader_time_shader_type st_reset);
241 return dst_reg(brw_null_reg());
246 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
249 dst_reg dst_null_ud()
251 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
254 struct brw_vec4_compile *c;
255 const struct brw_vec4_prog_key *key;
256 struct brw_vec4_prog_data *prog_data;
257 unsigned int sanity_param_count;
263 * GLSL IR currently being processed, which is associated with our
264 * driver IR instructions for debugging purposes.
267 const char *current_annotation;
269 int *virtual_grf_sizes;
270 int virtual_grf_count;
271 int virtual_grf_array_size;
272 int first_non_payload_grf;
273 unsigned int max_grf;
274 int *virtual_grf_start;
275 int *virtual_grf_end;
276 dst_reg userplane[MAX_CLIP_PLANES];
279 * This is the size to be used for an array with an element per
282 int virtual_grf_reg_count;
283 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
284 int *virtual_grf_reg_map;
286 bool live_intervals_valid;
288 dst_reg *variable_storage(ir_variable *var);
290 void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
292 bool need_all_constants_in_pull_buffer;
295 * \name Visit methods
297 * As typical for the visitor pattern, there must be one \c visit method for
298 * each concrete subclass of \c ir_instruction. Virtual base classes within
299 * the hierarchy should not have \c visit methods.
302 virtual void visit(ir_variable *);
303 virtual void visit(ir_loop *);
304 virtual void visit(ir_loop_jump *);
305 virtual void visit(ir_function_signature *);
306 virtual void visit(ir_function *);
307 virtual void visit(ir_expression *);
308 virtual void visit(ir_swizzle *);
309 virtual void visit(ir_dereference_variable *);
310 virtual void visit(ir_dereference_array *);
311 virtual void visit(ir_dereference_record *);
312 virtual void visit(ir_assignment *);
313 virtual void visit(ir_constant *);
314 virtual void visit(ir_call *);
315 virtual void visit(ir_return *);
316 virtual void visit(ir_discard *);
317 virtual void visit(ir_texture *);
318 virtual void visit(ir_if *);
319 virtual void visit(ir_emit_vertex *);
320 virtual void visit(ir_end_primitive *);
325 /* Regs for vertex results. Generated at ir_variable visiting time
326 * for the ir->location's used.
328 dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
329 const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
330 int uniform_size[MAX_UNIFORMS];
331 int uniform_vector_size[MAX_UNIFORMS];
334 src_reg shader_start_time;
336 struct hash_table *variable_ht;
339 void fail(const char *msg, ...);
341 int virtual_grf_alloc(int size);
342 void setup_uniform_clipplane_values();
343 void setup_uniform_values(ir_variable *ir);
344 void setup_builtin_uniform_values(ir_variable *ir);
345 int setup_uniforms(int payload_reg);
346 bool reg_allocate_trivial();
348 void evaluate_spill_costs(float *spill_costs, bool *no_spill);
349 int choose_spill_reg(struct ra_graph *g);
350 void spill_reg(int spill_reg);
351 void move_grf_array_access_to_scratch();
352 void move_uniform_array_access_to_pull_constants();
353 void move_push_constants_to_pull_constants();
354 void split_uniform_registers();
355 void pack_uniform_registers();
356 void calculate_live_intervals();
357 void invalidate_live_intervals();
358 void split_virtual_grfs();
359 bool dead_code_eliminate();
360 bool virtual_grf_interferes(int a, int b);
361 bool opt_copy_propagation();
362 bool opt_algebraic();
363 bool opt_register_coalesce();
364 void opt_set_dependency_control();
365 void opt_schedule_instructions();
367 bool can_do_source_mods(vec4_instruction *inst);
369 vec4_instruction *emit(vec4_instruction *inst);
371 vec4_instruction *emit(enum opcode opcode);
373 vec4_instruction *emit(enum opcode opcode, dst_reg dst);
375 vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
377 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
378 src_reg src0, src_reg src1);
380 vec4_instruction *emit(enum opcode opcode, dst_reg dst,
381 src_reg src0, src_reg src1, src_reg src2);
383 vec4_instruction *emit_before(vec4_instruction *inst,
384 vec4_instruction *new_inst);
386 vec4_instruction *MOV(dst_reg dst, src_reg src0);
387 vec4_instruction *NOT(dst_reg dst, src_reg src0);
388 vec4_instruction *RNDD(dst_reg dst, src_reg src0);
389 vec4_instruction *RNDE(dst_reg dst, src_reg src0);
390 vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
391 vec4_instruction *FRC(dst_reg dst, src_reg src0);
392 vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
393 vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
394 vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
395 vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
396 vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
397 vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
398 vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
399 vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
400 vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
401 vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
402 vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
403 vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
404 vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
405 vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
406 vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
407 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
409 vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
410 vec4_instruction *IF(uint32_t predicate);
411 vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
412 vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
413 vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
414 vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
415 vec4_instruction *BFREV(dst_reg dst, src_reg value);
416 vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
417 vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
418 vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
419 vec4_instruction *FBH(dst_reg dst, src_reg value);
420 vec4_instruction *FBL(dst_reg dst, src_reg value);
421 vec4_instruction *CBIT(dst_reg dst, src_reg value);
422 vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
423 vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1);
424 vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1);
426 int implied_mrf_writes(vec4_instruction *inst);
428 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
431 vec4_instruction *pre_rhs_inst,
432 vec4_instruction *last_rhs_inst);
434 bool try_copy_propagation(vec4_instruction *inst, int arg,
437 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
438 void visit_instructions(const exec_list *list);
440 void emit_vp_sop(uint32_t condmod, dst_reg dst,
441 src_reg src0, src_reg src1, src_reg one);
443 void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
444 void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
445 void emit_if_gen6(ir_if *ir);
447 void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
449 void emit_block_move(dst_reg *dst, src_reg *src,
450 const struct glsl_type *type, uint32_t predicate);
452 void emit_constant_values(dst_reg *dst, ir_constant *value);
455 * Emit the correct dot-product instruction for the type of arguments
457 void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
459 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
460 dst_reg dst, src_reg src0);
462 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
463 dst_reg dst, src_reg src0, src_reg src1);
465 void emit_scs(ir_instruction *ir, enum prog_opcode op,
466 dst_reg dst, const src_reg &src);
468 src_reg fix_3src_operand(src_reg src);
470 void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
471 void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
472 void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
473 void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
474 void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
475 void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
476 src_reg fix_math_operand(src_reg src);
478 void emit_pack_half_2x16(dst_reg dst, src_reg src0);
479 void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
481 uint32_t gather_channel(ir_texture *ir, int sampler);
482 src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
483 void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
484 void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
486 void emit_ndc_computation();
487 void emit_psiz_and_flags(struct brw_reg reg);
488 void emit_clip_distances(dst_reg reg, int offset);
489 void emit_generic_urb_slot(dst_reg reg, int varying);
490 void emit_urb_slot(int mrf, int varying);
492 void emit_shader_time_begin();
493 void emit_shader_time_end();
494 void emit_shader_time_write(enum shader_time_shader_type type,
497 void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
498 dst_reg dst, src_reg offset, src_reg src0,
501 void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
504 src_reg get_scratch_offset(vec4_instruction *inst,
505 src_reg *reladdr, int reg_offset);
506 src_reg get_pull_constant_offset(vec4_instruction *inst,
507 src_reg *reladdr, int reg_offset);
508 void emit_scratch_read(vec4_instruction *inst,
512 void emit_scratch_write(vec4_instruction *inst,
514 void emit_pull_constant_load(vec4_instruction *inst,
519 bool try_emit_sat(ir_expression *ir);
520 bool try_emit_mad(ir_expression *ir, int mul_arg);
521 void resolve_ud_negate(src_reg *reg);
523 src_reg get_timestamp();
525 bool process_move_condition(ir_rvalue *ir);
527 void dump_instruction(backend_instruction *inst);
529 void visit_atomic_counter_intrinsic(ir_call *ir);
533 void lower_attributes_to_hw_regs(const int *attribute_map,
535 void setup_payload_interference(struct ra_graph *g, int first_payload_node,
537 virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
538 virtual void setup_payload() = 0;
539 virtual void emit_prolog() = 0;
540 virtual void emit_program_code() = 0;
541 virtual void emit_thread_end() = 0;
542 virtual void emit_urb_write_header(int mrf) = 0;
543 virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
544 virtual int compute_array_stride(ir_dereference_array *ir);
546 const bool debug_flag;
550 * If true, then register allocation should fail instead of spilling.
552 const bool no_spills;
554 const shader_time_shader_type st_base;
555 const shader_time_shader_type st_written;
556 const shader_time_shader_type st_reset;
561 * The vertex shader code generator.
563 * Translates VS IR to actual i965 assembly code.
568 vec4_generator(struct brw_context *brw,
569 struct gl_shader_program *shader_prog,
570 struct gl_program *prog,
571 struct brw_vec4_prog_data *prog_data,
576 const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
579 void generate_code(exec_list *instructions);
580 void generate_vec4_instruction(vec4_instruction *inst,
582 struct brw_reg *src);
584 void generate_math1_gen4(vec4_instruction *inst,
587 void generate_math1_gen6(vec4_instruction *inst,
590 void generate_math2_gen4(vec4_instruction *inst,
593 struct brw_reg src1);
594 void generate_math2_gen6(vec4_instruction *inst,
597 struct brw_reg src1);
598 void generate_math2_gen7(vec4_instruction *inst,
601 struct brw_reg src1);
603 void generate_tex(vec4_instruction *inst,
607 void generate_vs_urb_write(vec4_instruction *inst);
608 void generate_gs_urb_write(vec4_instruction *inst);
609 void generate_gs_thread_end(vec4_instruction *inst);
610 void generate_gs_set_write_offset(struct brw_reg dst,
612 struct brw_reg src1);
613 void generate_gs_set_vertex_count(struct brw_reg dst,
615 void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
616 void generate_gs_prepare_channel_masks(struct brw_reg dst);
617 void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
618 void generate_oword_dual_block_offsets(struct brw_reg m1,
619 struct brw_reg index);
620 void generate_scratch_write(vec4_instruction *inst,
623 struct brw_reg index);
624 void generate_scratch_read(vec4_instruction *inst,
626 struct brw_reg index);
627 void generate_pull_constant_load(vec4_instruction *inst,
629 struct brw_reg index,
630 struct brw_reg offset);
631 void generate_pull_constant_load_gen7(vec4_instruction *inst,
633 struct brw_reg surf_index,
634 struct brw_reg offset);
635 void generate_unpack_flags(vec4_instruction *inst,
638 void generate_untyped_atomic(vec4_instruction *inst,
640 struct brw_reg atomic_op,
641 struct brw_reg surf_index);
643 void generate_untyped_surface_read(vec4_instruction *inst,
645 struct brw_reg surf_index);
647 void mark_surface_used(unsigned surf_index);
649 struct brw_context *brw;
651 struct brw_compile *p;
653 struct gl_shader_program *shader_prog;
654 const struct gl_program *prog;
656 struct brw_vec4_prog_data *prog_data;
659 const bool debug_flag;
663 * The vertex shader code generator.
665 * Translates VS IR to actual i965 assembly code.
667 class gen8_vec4_generator : public gen8_generator
670 gen8_vec4_generator(struct brw_context *brw,
671 struct gl_shader_program *shader_prog,
672 struct gl_program *prog,
673 struct brw_vec4_prog_data *prog_data,
676 ~gen8_vec4_generator();
678 const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
681 void generate_code(exec_list *instructions);
682 void generate_vec4_instruction(vec4_instruction *inst,
684 struct brw_reg *src);
686 void generate_tex(vec4_instruction *inst,
689 void generate_urb_write(vec4_instruction *ir, bool copy_g0);
690 void generate_gs_thread_end(vec4_instruction *ir);
691 void generate_gs_set_write_offset(struct brw_reg dst,
693 struct brw_reg src1);
694 void generate_gs_set_vertex_count(struct brw_reg dst,
696 void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
697 void generate_gs_prepare_channel_masks(struct brw_reg dst);
698 void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
700 void generate_oword_dual_block_offsets(struct brw_reg m1,
701 struct brw_reg index);
702 void generate_scratch_write(vec4_instruction *inst,
705 struct brw_reg index);
706 void generate_scratch_read(vec4_instruction *inst,
708 struct brw_reg index);
709 void generate_pull_constant_load(vec4_instruction *inst,
711 struct brw_reg index,
712 struct brw_reg offset);
714 void mark_surface_used(unsigned surf_index);
716 struct brw_vec4_prog_data *prog_data;
718 const bool debug_flag;
722 } /* namespace brw */
723 #endif /* __cplusplus */
725 #endif /* BRW_VEC4_H */