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25 #include "brw_vec4_live_variables.h"
30 /** @file brw_vec4_cse.cpp
32 * Support for local common subexpression elimination.
34 * See Muchnick's Advanced Compiler Design and Implementation, section
39 struct aeb_entry : public exec_node {
40 /** The instruction that generates the expression value. */
41 vec4_instruction *generator;
43 /** The temporary where the value is stored. */
49 is_expression(const vec4_instruction *const inst)
51 switch (inst->opcode) {
74 case VEC4_OPCODE_UNPACK_UNIFORM:
76 case SHADER_OPCODE_RCP:
77 case SHADER_OPCODE_RSQ:
78 case SHADER_OPCODE_SQRT:
79 case SHADER_OPCODE_EXP2:
80 case SHADER_OPCODE_LOG2:
81 case SHADER_OPCODE_POW:
82 case SHADER_OPCODE_INT_QUOTIENT:
83 case SHADER_OPCODE_INT_REMAINDER:
84 case SHADER_OPCODE_SIN:
85 case SHADER_OPCODE_COS:
86 return inst->mlen == 0;
93 operands_match(const vec4_instruction *a, const vec4_instruction *b)
95 const src_reg *xs = a->src;
96 const src_reg *ys = b->src;
98 if (a->opcode == BRW_OPCODE_MAD) {
99 return xs[0].equals(ys[0]) &&
100 ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
101 (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
102 } else if (!a->is_commutative()) {
103 return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
105 return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
106 (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
111 instructions_match(vec4_instruction *a, vec4_instruction *b)
113 return a->opcode == b->opcode &&
114 a->saturate == b->saturate &&
115 a->conditional_mod == b->conditional_mod &&
116 a->dst.type == b->dst.type &&
117 a->dst.writemask == b->dst.writemask &&
118 a->force_writemask_all == b->force_writemask_all &&
119 a->regs_written == b->regs_written &&
120 operands_match(a, b);
124 vec4_visitor::opt_cse_local(bblock_t *block)
126 bool progress = false;
129 void *cse_ctx = ralloc_context(NULL);
131 int ip = block->start_ip;
132 foreach_inst_in_block (vec4_instruction, inst, block) {
133 /* Skip some cases. */
134 if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
135 (inst->dst.file != HW_REG || inst->dst.is_null()))
139 foreach_in_list_use_after(aeb_entry, entry, &aeb) {
140 /* Match current instruction's expression against those in AEB. */
141 if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
142 instructions_match(inst, entry->generator)) {
150 if (inst->opcode != BRW_OPCODE_MOV ||
151 (inst->opcode == BRW_OPCODE_MOV &&
152 inst->src[0].file == IMM &&
153 inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
154 /* Our first sighting of this expression. Create an entry. */
155 aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
156 entry->tmp = src_reg(); /* file will be BAD_FILE */
157 entry->generator = inst;
158 aeb.push_tail(entry);
161 /* This is at least our second sighting of this expression.
162 * If we don't have a temporary already, make one.
164 bool no_existing_temp = entry->tmp.file == BAD_FILE;
165 if (no_existing_temp && !entry->generator->dst.is_null()) {
166 entry->tmp = retype(src_reg(GRF, alloc.allocate(
167 entry->generator->regs_written),
168 NULL), inst->dst.type);
170 for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
171 vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
172 offset(entry->tmp, i));
173 copy->force_writemask_all =
174 entry->generator->force_writemask_all;
175 entry->generator->insert_after(block, copy);
178 entry->generator->dst = dst_reg(entry->tmp);
182 if (!inst->dst.is_null()) {
183 assert(inst->dst.type == entry->tmp.type);
185 for (unsigned i = 0; i < inst->regs_written; ++i) {
186 vec4_instruction *copy = MOV(offset(inst->dst, i),
187 offset(entry->tmp, i));
188 copy->force_writemask_all = inst->force_writemask_all;
189 inst->insert_before(block, copy);
193 /* Set our iterator so that next time through the loop inst->next
194 * will get the instruction in the basic block after the one we've
197 vec4_instruction *prev = (vec4_instruction *)inst->prev;
204 foreach_in_list_safe(aeb_entry, entry, &aeb) {
205 /* Kill all AEB entries that write a different value to or read from
206 * the flag register if we just wrote it.
208 if (inst->writes_flag()) {
209 if (entry->generator->reads_flag() ||
210 (entry->generator->writes_flag() &&
211 !instructions_match(inst, entry->generator))) {
218 for (int i = 0; i < 3; i++) {
219 src_reg *src = &entry->generator->src[i];
221 /* Kill all AEB entries that use the destination we just
224 if (inst->dst.file == entry->generator->src[i].file &&
225 inst->dst.reg == entry->generator->src[i].reg) {
231 /* Kill any AEB entries using registers that don't get reused any
232 * more -- a sure sign they'll fail operands_match().
234 if (src->file == GRF) {
235 if (var_range_end(var_from_reg(alloc, *src), 4) < ip) {
247 ralloc_free(cse_ctx);
253 vec4_visitor::opt_cse()
255 bool progress = false;
257 calculate_live_intervals();
259 foreach_block (block, cfg) {
260 progress = opt_cse_local(block) || progress;
264 invalidate_live_intervals();