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25 #include "brw_vec4_live_variables.h"
28 /** @file brw_vec4_dead_code_eliminate.cpp
30 * Dataflow-aware dead code elimination.
32 * Walks the instruction list from the bottom, removing instructions that
33 * have results that both aren't used in later blocks and haven't been read
34 * yet in the tail end of this block.
40 can_do_writemask(const struct brw_context *brw,
41 const vec4_instruction *inst)
43 switch (inst->opcode) {
44 case SHADER_OPCODE_GEN4_SCRATCH_READ:
45 case VS_OPCODE_PULL_CONSTANT_LOAD:
46 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
47 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
50 /* The MATH instruction on Gen6 only executes in align1 mode, which does
51 * not support writemasking.
53 if (brw->gen == 6 && inst->is_math())
64 vec4_visitor::dead_code_eliminate()
66 bool progress = false;
68 calculate_live_intervals();
70 int num_vars = live_intervals->num_vars;
71 BITSET_WORD *live = ralloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
72 BITSET_WORD *flag_live = ralloc_array(NULL, BITSET_WORD, 1);
74 foreach_block(block, cfg) {
75 memcpy(live, live_intervals->block_data[block->num].liveout,
76 sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
77 memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout,
80 foreach_inst_in_block_reverse(vec4_instruction, inst, block) {
81 if (inst->dst.file == GRF && !inst->has_side_effects()) {
82 bool result_live[4] = { false };
84 for (unsigned i = 0; i < inst->regs_written; i++) {
85 for (int c = 0; c < 4; c++)
86 result_live[c] |= BITSET_TEST(
87 live, var_from_reg(alloc, offset(inst->dst, i), c));
90 /* If the instruction can't do writemasking, then it's all or
93 if (!can_do_writemask(brw, inst)) {
94 bool result = result_live[0] | result_live[1] |
95 result_live[2] | result_live[3];
96 result_live[0] = result;
97 result_live[1] = result;
98 result_live[2] = result;
99 result_live[3] = result;
102 for (int c = 0; c < 4; c++) {
103 if (!result_live[c] && inst->dst.writemask & (1 << c)) {
104 inst->dst.writemask &= ~(1 << c);
107 if (inst->dst.writemask == 0) {
108 if (inst->writes_accumulator || inst->writes_flag()) {
109 inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
111 inst->opcode = BRW_OPCODE_NOP;
119 if (inst->dst.is_null() && inst->writes_flag()) {
120 if (!BITSET_TEST(flag_live, 0)) {
121 inst->opcode = BRW_OPCODE_NOP;
127 if (inst->dst.file == GRF && !inst->predicate) {
128 for (unsigned i = 0; i < inst->regs_written; i++) {
129 for (int c = 0; c < 4; c++) {
130 if (inst->dst.writemask & (1 << c)) {
131 BITSET_CLEAR(live, var_from_reg(alloc,
132 offset(inst->dst, i), c));
138 if (inst->writes_flag()) {
139 BITSET_CLEAR(flag_live, 0);
142 for (int i = 0; i < 3; i++) {
143 if (inst->src[i].file == GRF) {
144 for (unsigned j = 0; j < inst->regs_read(i); j++) {
145 for (int c = 0; c < 4; c++) {
146 BITSET_SET(live, var_from_reg(alloc,
147 offset(inst->src[i], j), c));
153 if (inst->reads_flag()) {
154 BITSET_SET(flag_live, 0);
160 ralloc_free(flag_live);
163 foreach_block_and_inst_safe(block, backend_instruction, inst, cfg) {
164 if (inst->opcode == BRW_OPCODE_NOP) {
169 invalidate_live_intervals();