2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "main/texformat.h"
33 #include "brw_context.h"
36 #include "brw_state.h"
39 /** Return number of src args for given instruction */
40 GLuint brw_wm_nr_args( GLuint opcode )
57 assert(opcode < MAX_OPCODE);
58 return _mesa_num_inst_src_regs(opcode);
63 GLuint brw_wm_is_scalar_result( GLuint opcode )
86 * Do GPU code generation for non-GLSL shader. non-GLSL shaders have
87 * no flow control instructions so we can more readily do SSA-style
91 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
93 /* Augment fragment program. Add instructions for pre- and
94 * post-fragment-program tasks such as interpolation and fogging.
98 /* Translate to intermediate representation. Build register usage
103 /* Dead code removal.
107 /* Register allocation.
108 * Divide by two because we operate on 16 pixels at a time and require
109 * two GRF entries for each logical shader register.
111 c->grf_limit = BRW_WM_MAX_GRF / 2;
115 /* how many general-purpose registers are used */
116 c->prog_data.total_grf = c->max_wm_grf;
118 /* Scratch space is used for register spilling */
119 if (c->last_scratch) {
120 c->prog_data.total_scratch = c->last_scratch + 0x40;
123 c->prog_data.total_scratch = 0;
133 * All Mesa program -> GPU code generation goes through this function.
134 * Depending on the instructions used (i.e. flow control instructions)
135 * we'll use one of two code generators.
137 static void do_wm_prog( struct brw_context *brw,
138 struct brw_fragment_program *fp,
139 struct brw_wm_prog_key *key)
141 struct brw_wm_compile *c;
142 const GLuint *program;
145 c = brw->wm.compile_data;
147 brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
148 c = brw->wm.compile_data;
150 memset(c, 0, sizeof(*brw->wm.compile_data));
152 memcpy(&c->key, key, sizeof(*key));
155 c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
157 brw_init_compile(brw, &c->func);
159 /* temporary sanity check assertion */
160 ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
163 * Shader which use GLSL features such as flow control are handled
164 * differently from "simple" shaders.
167 brw_wm_glsl_emit(brw, c);
170 brw_wm_non_glsl_emit(brw, c);
173 if (INTEL_DEBUG & DEBUG_WM)
174 fprintf(stderr, "\n");
178 program = brw_get_program(&c->func, &program_size);
180 dri_bo_unreference(brw->wm.prog_bo);
181 brw->wm.prog_bo = brw_upload_cache( &brw->cache, BRW_WM_PROG,
182 &c->key, sizeof(c->key),
184 program, program_size,
186 &brw->wm.prog_data );
191 static void brw_wm_populate_key( struct brw_context *brw,
192 struct brw_wm_prog_key *key )
194 GLcontext *ctx = &brw->intel.ctx;
195 /* BRW_NEW_FRAGMENT_PROGRAM */
196 const struct brw_fragment_program *fp =
197 (struct brw_fragment_program *)brw->fragment_program;
202 memset(key, 0, sizeof(*key));
204 /* Build the index for table lookup
207 if (fp->program.UsesKill ||
208 ctx->Color.AlphaEnabled)
209 lookup |= IZ_PS_KILL_ALPHATEST_BIT;
211 if (fp->program.Base.OutputsWritten & (1<<FRAG_RESULT_DEPTH))
212 lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
216 lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
218 if (ctx->Depth.Test &&
219 ctx->Depth.Mask) /* ?? */
220 lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
223 if (ctx->Stencil._Enabled) {
224 lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
226 if (ctx->Stencil.WriteMask[0] ||
227 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
228 lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
233 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
234 if (ctx->Line.SmoothFlag) {
235 if (brw->intel.reduced_primitive == GL_LINES) {
238 else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
239 if (ctx->Polygon.FrontMode == GL_LINE) {
240 line_aa = AA_SOMETIMES;
242 if (ctx->Polygon.BackMode == GL_LINE ||
243 (ctx->Polygon.CullFlag &&
244 ctx->Polygon.CullFaceMode == GL_BACK))
247 else if (ctx->Polygon.BackMode == GL_LINE) {
248 line_aa = AA_SOMETIMES;
250 if ((ctx->Polygon.CullFlag &&
251 ctx->Polygon.CullFaceMode == GL_FRONT))
257 brw_wm_lookup_iz(line_aa,
262 /* BRW_NEW_WM_INPUT_DIMENSIONS */
263 key->projtex_mask = brw->wm.input_size_masks[4-1] >> (FRAG_ATTRIB_TEX0 - FRAG_ATTRIB_WPOS);
266 key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
269 for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
270 const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
272 if (unit->_ReallyEnabled) {
273 const struct gl_texture_object *t = unit->_Current;
274 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
275 if (img->InternalFormat == GL_YCBCR_MESA) {
276 key->yuvtex_mask |= 1 << i;
277 if (img->TexFormat->MesaFormat == MESA_FORMAT_YCBCR)
278 key->yuvtex_swap_mask |= 1 << i;
281 key->tex_swizzles[i] = t->_Swizzle;
284 key->tex_swizzles[i] = SWIZZLE_NOOP;
289 key->shadowtex_mask = fp->program.Base.ShadowSamplers;
293 * Include the draw buffer origin and height so that we can calculate
294 * fragment position values relative to the bottom left of the drawable,
295 * from the incoming screen origin relative position we get as part of our
298 * We could avoid recompiling by including this as a constant referenced by
299 * our program, but if we were to do that it would also be nice to handle
300 * getting that constant updated at batchbuffer submit time (when we
301 * hold the lock and know where the buffer really is) rather than at emit
302 * time when we don't hold the lock and are just guessing. We could also
303 * just avoid using this as key data if the program doesn't use
306 * This pretty much becomes moot with DRI2 and redirected buffers anyway,
307 * as our origins will always be zero then.
309 if (brw->intel.driDrawable != NULL) {
310 key->origin_x = brw->intel.driDrawable->x;
311 key->origin_y = brw->intel.driDrawable->y;
312 key->drawable_height = brw->intel.driDrawable->h;
315 /* The unique fragment program ID */
316 key->program_string_id = fp->id;
320 static void brw_prepare_wm_prog(struct brw_context *brw)
322 struct brw_wm_prog_key key;
323 struct brw_fragment_program *fp = (struct brw_fragment_program *)
324 brw->fragment_program;
326 brw_wm_populate_key(brw, &key);
328 /* Make an early check for the key.
330 dri_bo_unreference(brw->wm.prog_bo);
331 brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
335 if (brw->wm.prog_bo == NULL)
336 do_wm_prog(brw, fp, &key);
340 const struct brw_tracked_state brw_wm_prog = {
342 .mesa = (_NEW_COLOR |
350 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
351 BRW_NEW_WM_INPUT_DIMENSIONS |
352 BRW_NEW_REDUCED_PRIMITIVE),
355 .prepare = brw_prepare_wm_prog