src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_RGBX8888] = 0,
 295       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 296       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 297       [MESA_FORMAT_XRGB8888_REV] = 0,
 298       [MESA_FORMAT_RGB888] = 0,
 299       [MESA_FORMAT_BGR888] = 0,
 300       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 301       [MESA_FORMAT_RGB565_REV] = 0,
 302       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 303       [MESA_FORMAT_ARGB4444_REV] = 0,
 304       [MESA_FORMAT_RGBA5551] = 0,
 305       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 306       [MESA_FORMAT_ARGB1555_REV] = 0,
 307       [MESA_FORMAT_AL44] = 0,
 308       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 309       [MESA_FORMAT_AL88_REV] = 0,
 310       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 311       [MESA_FORMAT_AL1616_REV] = 0,
 312       [MESA_FORMAT_RGB332] = 0,
 313       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 314       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 315       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 316       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 317       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 318       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 319       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 320       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 321       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 322       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 323       [MESA_FORMAT_RG88] = 0,
 324       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 325       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 326       [MESA_FORMAT_RG1616_REV] = 0,
 327       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 328       [MESA_FORMAT_Z24_S8] = 0,
 329       [MESA_FORMAT_S8_Z24] = 0,
 330       [MESA_FORMAT_Z16] = 0,
 331       [MESA_FORMAT_X8_Z24] = 0,
 332       [MESA_FORMAT_Z24_X8] = 0,
 333       [MESA_FORMAT_Z32] = 0,
 334       [MESA_FORMAT_S8] = 0,
 335
 336       [MESA_FORMAT_SRGB8] = 0,
 337       [MESA_FORMAT_SRGBA8] = 0,
 338       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 340       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 341       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 343       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 344       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 345
 346       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 347       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 348       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 349       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 350       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 351       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 352
 353       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 354       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 355       [MESA_FORMAT_RGB_FLOAT32] = 0,
 356       [MESA_FORMAT_RGB_FLOAT16] = 0,
 357       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 358       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 361       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 362       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 363       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 364       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 365       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 366       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 367       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 368       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 369
 370       [MESA_FORMAT_ALPHA_UINT8] = 0,
 371       [MESA_FORMAT_ALPHA_UINT16] = 0,
 372       [MESA_FORMAT_ALPHA_UINT32] = 0,
 373       [MESA_FORMAT_ALPHA_INT8] = 0,
 374       [MESA_FORMAT_ALPHA_INT16] = 0,
 375       [MESA_FORMAT_ALPHA_INT32] = 0,
 376
 377       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 378       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 379       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 380       [MESA_FORMAT_INTENSITY_INT8] = 0,
 381       [MESA_FORMAT_INTENSITY_INT16] = 0,
 382       [MESA_FORMAT_INTENSITY_INT32] = 0,
 383
 384       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 385       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 386       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 388       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 389       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 390
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 395       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 396       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 397
 398       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 399       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 400       [MESA_FORMAT_RGB_INT8] = 0,
 401       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 402       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 403       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 404       [MESA_FORMAT_RGB_INT16] = 0,
 405       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 406       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 407       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 408       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 409       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 410
 411       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 412       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 413       [MESA_FORMAT_RGB_UINT8] = 0,
 414       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 415       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 416       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 417       [MESA_FORMAT_RGB_UINT16] = 0,
 418       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 419       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 420       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 421       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 422       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 423
 424       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 426       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 427       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 428       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 429       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 430       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 431       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 432       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 433       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 434       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 435
 436       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 437       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 438       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 439       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 440
 441       [MESA_FORMAT_L_LATC1] = 0,
 442       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 443       [MESA_FORMAT_LA_LATC2] = 0,
 444       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 445
 446       [MESA_FORMAT_SIGNED_A8] = 0,
 447       [MESA_FORMAT_SIGNED_L8] = 0,
 448       [MESA_FORMAT_SIGNED_AL88] = 0,
 449       [MESA_FORMAT_SIGNED_I8] = 0,
 450       [MESA_FORMAT_SIGNED_A16] = 0,
 451       [MESA_FORMAT_SIGNED_L16] = 0,
 452       [MESA_FORMAT_SIGNED_AL1616] = 0,
 453       [MESA_FORMAT_SIGNED_I16] = 0,
 454
 455       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 456       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 457
 458       [MESA_FORMAT_Z32_FLOAT] = 0,
 459       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 460    };
 461    assert(mesa_format < MESA_FORMAT_COUNT);
 462    return table[mesa_format];
 463 }
 464
 465 void
 466 brw_init_surface_formats(struct brw_context *brw)
 467 {
 468    struct intel_context *intel = &brw->intel;
 469    struct gl_context *ctx = &intel->ctx;
 470    int gen;
 471    gl_format format;
 472
 473    gen = intel->gen * 10;
 474    if (intel->is_g4x)
 475       gen += 5;
 476
 477    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 478       uint32_t texture, render;
 479       const struct surface_format_info *rinfo, *tinfo;
 480       bool is_integer = _mesa_is_format_integer_color(format);
 481
 482       render = texture = brw_format_for_mesa_format(format);
 483       tinfo = &surface_formats[texture];
 484
 485       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 486        * it.
 487        */
 488       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 489          continue;
 490
 491       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 492          ctx->TextureFormatSupported[format] = true;
 493
 494       /* Re-map some render target formats to make them supported when they
 495        * wouldn't be using their format for texturing.
 496        */
 497       switch (render) {
 498          /* For these formats, we just need to read/write the first
 499           * channel into R, which is to say that we just treat them as
 500           * GL_RED.
 501           */
 502       case BRW_SURFACEFORMAT_I32_FLOAT:
 503       case BRW_SURFACEFORMAT_L32_FLOAT:
 504          render = BRW_SURFACEFORMAT_R32_FLOAT;
 505          break;
 506       case BRW_SURFACEFORMAT_I16_FLOAT:
 507       case BRW_SURFACEFORMAT_L16_FLOAT:
 508          render = BRW_SURFACEFORMAT_R16_FLOAT;
 509          break;
 510       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 511          /* XRGB is handled as ARGB because the chips in this family
 512           * cannot render to XRGB targets.  This means that we have to
 513           * mask writes to alpha (ala glColorMask) and reconfigure the
 514           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 515           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 516           * used.
 517           */
 518          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 519          break;
 520       }
 521
 522       rinfo = &surface_formats[render];
 523
 524       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 525        * integer, so we don't need hardware support for blending on it.  Other
 526        * than that, GL in general requires alpha blending for render targets,
 527        * even though we don't support it for some formats.
 528        */
 529       if (gen >= rinfo->render_target &&
 530           (gen >= rinfo->alpha_blend || is_integer)) {
 531          brw->render_target_format[format] = render;
 532          brw->format_supported_as_render_target[format] = true;
 533       }
 534    }
 535
 536    /* We will check this table for FBO completeness, but the surface format
 537     * table above only covered color rendering.
 538     */
 539    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 540    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 541    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 542    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 543    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 544    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 545
 546    /* We remap depth formats to a supported texturing format in
 547     * translate_tex_format().
 548     */
 549    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 550    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 551    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 552    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 553    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 554
 555    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 556     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 557     */
 558    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 559 }
 560
 561 bool
 562 brw_render_target_supported(struct intel_context *intel,
 563                             struct gl_renderbuffer *rb)
 564 {
 565    struct brw_context *brw = brw_context(&intel->ctx);
 566    gl_format format = rb->Format;
 567
 568    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 569     * we would consider them renderable even though we don't have surface
 570     * support for their alpha behavior and don't have the blending unit
 571     * available to fake it like we do for XRGB8888.  Force them to being
 572     * unsupported.
 573     */
 574    if ((rb->_BaseFormat != GL_RGBA &&
 575         rb->_BaseFormat != GL_RG &&
 576         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 577       return false;
 578
 579    /* Under some conditions, MSAA is not supported for formats whose width is
 580     * more than 64 bits.
 581     */
 582    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 583       /* Gen6: MSAA on >64 bit formats is unsupported. */
 584       if (intel->gen <= 6)
 585          return false;
 586
 587       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 588       if (rb->NumSamples >= 8)
 589          return false;
 590    }
 591
 592    return brw->format_supported_as_render_target[format];
 593 }
 594
 595 GLuint
 596 translate_tex_format(gl_format mesa_format,
 597                      GLenum internal_format,
 598                      GLenum depth_mode,
 599                      GLenum srgb_decode)
 600 {
 601    switch( mesa_format ) {
 602
 603    case MESA_FORMAT_Z16:
 604       return BRW_SURFACEFORMAT_I16_UNORM;
 605
 606    case MESA_FORMAT_S8_Z24:
 607    case MESA_FORMAT_X8_Z24:
 608       return BRW_SURFACEFORMAT_I24X8_UNORM;
 609
 610    case MESA_FORMAT_Z32_FLOAT:
 611       return BRW_SURFACEFORMAT_I32_FLOAT;
 612
 613    case MESA_FORMAT_Z32_FLOAT_X24S8:
 614       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 615
 616    case MESA_FORMAT_SARGB8:
 617    case MESA_FORMAT_SLA8:
 618    case MESA_FORMAT_SL8:
 619       if (srgb_decode == GL_DECODE_EXT)
 620          return brw_format_for_mesa_format(mesa_format);
 621       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 622          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 623
 624    case MESA_FORMAT_RGBA_FLOAT32:
 625       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 626        * assertion below.
 627        */
 628       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 629
 630    default:
 631       assert(brw_format_for_mesa_format(mesa_format) != 0);
 632       return brw_format_for_mesa_format(mesa_format);
 633    }
 634 }
 635
 636 uint32_t
 637 brw_get_surface_tiling_bits(uint32_t tiling)
 638 {
 639    switch (tiling) {
 640    case I915_TILING_X:
 641       return BRW_SURFACE_TILED;
 642    case I915_TILING_Y:
 643       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 644    default:
 645       return 0;
 646    }
 647 }
 648
 649
 650 uint32_t
 651 brw_get_surface_num_multisamples(unsigned num_samples)
 652 {
 653    if (num_samples > 0)
 654       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 655    else
 656       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 657 }
 658
 659
 660 static void
 661 brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit)
 662 {
 663    struct brw_context *brw = brw_context(ctx);
 664    struct intel_context *intel = &brw->intel;
 665    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 666    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 667    uint32_t *surf;
 668    struct intel_buffer_object *intel_obj =
 669       intel_buffer_object(tObj->BufferObject);
 670    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 671    gl_format format = tObj->_BufferObjectFormat;
 672    uint32_t brw_format = brw_format_for_mesa_format(format);
 673    int texel_size = _mesa_get_format_bytes(format);
 674
 675    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 676       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 677                     _mesa_get_format_name(format));
 678    }
 679
 680    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 681                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 682
 683    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 684               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 685
 686    if (intel->gen >= 6)
 687       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 688
 689    if (bo) {
 690       surf[1] = bo->offset; /* reloc */
 691
 692       /* Emit relocation to surface contents. */
 693       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 694                               brw->wm.surf_offset[surf_index] + 4,
 695                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 696
 697       int w = intel_obj->Base.Size / texel_size;
 698       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 699                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 700       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 701                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 702    } else {
 703       surf[1] = 0;
 704       surf[2] = 0;
 705       surf[3] = 0;
 706    }
 707
 708    surf[4] = 0;
 709    surf[5] = 0;
 710 }
 711
 712 static void
 713 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 714 {
 715    struct brw_context *brw = brw_context(ctx);
 716    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 717    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 718    struct intel_mipmap_tree *mt = intelObj->mt;
 719    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 720    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 721    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 722    uint32_t *surf;
 723    int width, height, depth;
 724
 725    if (tObj->Target == GL_TEXTURE_BUFFER) {
 726       brw_update_buffer_texture_surface(ctx, unit);
 727       return;
 728    }
 729
 730    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 731
 732    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 733                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 734
 735    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 736               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 737               BRW_SURFACE_CUBEFACE_ENABLES |
 738               (translate_tex_format(mt->format,
 739                                     firstImage->InternalFormat,
 740                                     sampler->DepthMode,
 741                                     sampler->sRGBDecode) <<
 742                BRW_SURFACE_FORMAT_SHIFT));
 743
 744    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 745
 746    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 747               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 748               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 749
 750    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 751               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 752               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 753               BRW_SURFACE_PITCH_SHIFT);
 754
 755    surf[4] = 0;
 756
 757    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 758
 759    /* Emit relocation to surface contents */
 760    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 761                            brw->wm.surf_offset[surf_index] + 4,
 762                            intelObj->mt->region->bo,
 763                            intelObj->mt->offset,
 764                            I915_GEM_DOMAIN_SAMPLER, 0);
 765 }
 766
 767 /**
 768  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 769  * read from this buffer with Data Port Read instructions/messages.
 770  */
 771 void
 772 brw_create_constant_surface(struct brw_context *brw,
 773                             drm_intel_bo *bo,
 774                             int width,
 775                             uint32_t *out_offset)
 776 {
 777    struct intel_context *intel = &brw->intel;
 778    const GLint w = width - 1;
 779    uint32_t *surf;
 780
 781    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 782                           6 * 4, 32, out_offset);
 783
 784    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 785               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 786               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 787
 788    if (intel->gen >= 6)
 789       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 790
 791    surf[1] = bo->offset; /* reloc */
 792
 793    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 794               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 795
 796    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 797               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 798
 799    surf[4] = 0;
 800    surf[5] = 0;
 801
 802    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 803     * bspec ("Data Cache") says that the data cache does not exist as
 804     * a separate cache and is just the sampler cache.
 805     */
 806    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 807                            *out_offset + 4,
 808                            bo, 0,
 809                            I915_GEM_DOMAIN_SAMPLER, 0);
 810 }
 811
 812 /**
 813  * Set up a binding table entry for use by stream output logic (transform
 814  * feedback).
 815  *
 816  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 817  */
 818 void
 819 brw_update_sol_surface(struct brw_context *brw,
 820                        struct gl_buffer_object *buffer_obj,
 821                        uint32_t *out_offset, unsigned num_vector_components,
 822                        unsigned stride_dwords, unsigned offset_dwords)
 823 {
 824    struct intel_context *intel = &brw->intel;
 825    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 826    drm_intel_bo *bo =
 827       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 828    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 829                                     out_offset);
 830    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 831    uint32_t offset_bytes = 4 * offset_dwords;
 832    size_t size_dwords = buffer_obj->Size / 4;
 833    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 834
 835    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 836     * too big to map using a single binding table entry?
 837     */
 838    assert((size_dwords - offset_dwords) / stride_dwords
 839           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 840
 841    if (size_dwords > offset_dwords + num_vector_components) {
 842       /* There is room for at least 1 transform feedback output in the buffer.
 843        * Compute the number of additional transform feedback outputs the
 844        * buffer has room for.
 845        */
 846       buffer_size_minus_1 =
 847          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 848    } else {
 849       /* There isn't even room for a single transform feedback output in the
 850        * buffer.  We can't configure the binding table entry to prevent output
 851        * entirely; we'll have to rely on the geometry shader to detect
 852        * overflow.  But to minimize the damage in case of a bug, set up the
 853        * binding table entry to just allow a single output.
 854        */
 855       buffer_size_minus_1 = 0;
 856    }
 857    width = buffer_size_minus_1 & 0x7f;
 858    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 859    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 860
 861    switch (num_vector_components) {
 862    case 1:
 863       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 864       break;
 865    case 2:
 866       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 867       break;
 868    case 3:
 869       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 870       break;
 871    case 4:
 872       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 873       break;
 874    default:
 875       assert(!"Invalid vector size for transform feedback output");
 876       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 877       break;
 878    }
 879
 880    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 881       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 882       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 883       BRW_SURFACE_RC_READ_WRITE;
 884    surf[1] = bo->offset + offset_bytes; /* reloc */
 885    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 886               height << BRW_SURFACE_HEIGHT_SHIFT);
 887    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 888               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 889    surf[4] = 0;
 890    surf[5] = 0;
 891
 892    /* Emit relocation to surface contents. */
 893    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 894                            *out_offset + 4,
 895                            bo, offset_bytes,
 896                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 897 }
 898
 899 /* Creates a new WM constant buffer reflecting the current fragment program's
 900  * constants, if needed by the fragment program.
 901  *
 902  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 903  * state atom.
 904  */
 905 static void
 906 brw_upload_wm_pull_constants(struct brw_context *brw)
 907 {
 908    struct gl_context *ctx = &brw->intel.ctx;
 909    struct intel_context *intel = &brw->intel;
 910    /* BRW_NEW_FRAGMENT_PROGRAM */
 911    struct brw_fragment_program *fp =
 912       (struct brw_fragment_program *) brw->fragment_program;
 913    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 914    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 915    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 916    float *constants;
 917    unsigned int i;
 918
 919    _mesa_load_state_parameters(ctx, params);
 920
 921    /* CACHE_NEW_WM_PROG */
 922    if (brw->wm.prog_data->nr_pull_params == 0) {
 923       if (brw->wm.const_bo) {
 924          drm_intel_bo_unreference(brw->wm.const_bo);
 925          brw->wm.const_bo = NULL;
 926          brw->wm.surf_offset[surf_index] = 0;
 927          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 928       }
 929       return;
 930    }
 931
 932    drm_intel_bo_unreference(brw->wm.const_bo);
 933    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 934                                          size, 64);
 935
 936    /* _NEW_PROGRAM_CONSTANTS */
 937    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 938    constants = brw->wm.const_bo->virtual;
 939    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 940       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 941                                    brw->wm.prog_data->pull_param[i]);
 942    }
 943    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 944
 945    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 946                                        params->NumParameters,
 947                                        &brw->wm.surf_offset[surf_index]);
 948
 949    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 950 }
 951
 952 const struct brw_tracked_state brw_wm_pull_constants = {
 953    .dirty = {
 954       .mesa = (_NEW_PROGRAM_CONSTANTS),
 955       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 956       .cache = CACHE_NEW_WM_PROG,
 957    },
 958    .emit = brw_upload_wm_pull_constants,
 959 };
 960
 961 static void
 962 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 963 {
 964    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
 965     * Notes):
 966     *
 967     *     A null surface will be used in instances where an actual surface is
 968     *     not bound. When a write message is generated to a null surface, no
 969     *     actual surface is written to. When a read message (including any
 970     *     sampling engine message) is generated to a null surface, the result
 971     *     is all zeros. Note that a null surface type is allowed to be used
 972     *     with all messages, even if it is not specificially indicated as
 973     *     supported. All of the remaining fields in surface state are ignored
 974     *     for null surfaces, with the following exceptions:
 975     *
 976     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
 977     *       depth buffer’s corresponding state for all render target surfaces,
 978     *       including null.
 979     *
 980     *     - Surface Format must be R8G8B8A8_UNORM.
 981     */
 982    struct intel_context *intel = &brw->intel;
 983    struct gl_context *ctx = &intel->ctx;
 984    uint32_t *surf;
 985
 986    /* _NEW_BUFFERS */
 987    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 988
 989    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 990                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 991
 992    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 993               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 994    if (intel->gen < 6) {
 995       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 996                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 997                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 998                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 999    }
1000    surf[1] = 0;
1001    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1002               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1003
1004    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1005     * Notes):
1006     *
1007     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
1008     */
1009    surf[3] = BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
1010    surf[4] = 0;
1011    surf[5] = 0;
1012 }
1013
1014 /**
1015  * Sets up a surface state structure to point at the given region.
1016  * While it is only used for the front/back buffer currently, it should be
1017  * usable for further buffers when doing ARB_draw_buffer support.
1018  */
1019 static void
1020 brw_update_renderbuffer_surface(struct brw_context *brw,
1021                                 struct gl_renderbuffer *rb,
1022                                 unsigned int unit)
1023 {
1024    struct intel_context *intel = &brw->intel;
1025    struct gl_context *ctx = &intel->ctx;
1026    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1027    struct intel_mipmap_tree *mt = irb->mt;
1028    struct intel_region *region;
1029    uint32_t *surf;
1030    uint32_t tile_x, tile_y;
1031    uint32_t format = 0;
1032    gl_format rb_format = intel_rb_format(irb);
1033
1034    if (irb->tex_image && !brw->has_surface_tile_offset) {
1035       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1036
1037       if (tile_x != 0 || tile_y != 0) {
1038          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1039           * destination in a miptree unless you actually setup your renderbuffer
1040           * as a miptree and used the fragile lod/array_index/etc. controls to
1041           * select the image.  So, instead, we just make a new single-level
1042           * miptree and render into that.
1043           */
1044          struct intel_context *intel = intel_context(ctx);
1045          struct intel_texture_image *intel_image =
1046             intel_texture_image(irb->tex_image);
1047          struct intel_mipmap_tree *new_mt;
1048          int width, height, depth;
1049
1050          intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth);
1051
1052          new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target,
1053                                        intel_image->base.Base.TexFormat,
1054                                        intel_image->base.Base.Level,
1055                                        intel_image->base.Base.Level,
1056                                        width, height, depth,
1057                                        true,
1058                                        0 /* num_samples */,
1059                                        INTEL_MSAA_LAYOUT_NONE);
1060
1061          intel_miptree_copy_teximage(intel, intel_image, new_mt);
1062          intel_miptree_reference(&irb->mt, intel_image->mt);
1063          intel_renderbuffer_set_draw_offset(irb);
1064          intel_miptree_release(&new_mt);
1065
1066          mt = irb->mt;
1067       }
1068    }
1069
1070    region = irb->mt->region;
1071
1072    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1073                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1074
1075    switch (rb_format) {
1076    case MESA_FORMAT_SARGB8:
1077       /* _NEW_BUFFERS
1078        *
1079        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1080        * blend/update as sRGB.
1081        */
1082       if (ctx->Color.sRGBEnabled)
1083          format = brw_format_for_mesa_format(rb_format);
1084       else
1085          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1086       break;
1087    default:
1088       format = brw->render_target_format[rb_format];
1089       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1090          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1091                        __FUNCTION__, _mesa_get_format_name(rb_format));
1092       }
1093       break;
1094    }
1095
1096    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1097               format << BRW_SURFACE_FORMAT_SHIFT);
1098
1099    /* reloc */
1100    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1101               region->bo->offset);
1102
1103    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1104               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1105
1106    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1107               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
1108
1109    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1110
1111    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1112    /* Note that the low bits of these fields are missing, so
1113     * there's the possibility of getting in trouble.
1114     */
1115    assert(tile_x % 4 == 0);
1116    assert(tile_y % 2 == 0);
1117    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1118               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1119               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1120
1121    if (intel->gen < 6) {
1122       /* _NEW_COLOR */
1123       if (!ctx->Color.ColorLogicOpEnabled &&
1124           (ctx->Color.BlendEnabled & (1 << unit)))
1125          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1126
1127       if (!ctx->Color.ColorMask[unit][0])
1128          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1129       if (!ctx->Color.ColorMask[unit][1])
1130          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1131       if (!ctx->Color.ColorMask[unit][2])
1132          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1133
1134       /* As mentioned above, disable writes to the alpha component when the
1135        * renderbuffer is XRGB.
1136        */
1137       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1138           !ctx->Color.ColorMask[unit][3]) {
1139          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1140       }
1141    }
1142
1143    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1144                            brw->wm.surf_offset[unit] + 4,
1145                            region->bo,
1146                            surf[1] - region->bo->offset,
1147                            I915_GEM_DOMAIN_RENDER,
1148                            I915_GEM_DOMAIN_RENDER);
1149 }
1150
1151 /**
1152  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1153  */
1154 static void
1155 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1156 {
1157    struct intel_context *intel = &brw->intel;
1158    struct gl_context *ctx = &brw->intel.ctx;
1159    GLuint i;
1160
1161    /* _NEW_BUFFERS | _NEW_COLOR */
1162    /* Update surfaces for drawing buffers */
1163    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1164       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1165          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1166             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1167          } else {
1168             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1169          }
1170       }
1171    } else {
1172       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1173    }
1174    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1175 }
1176
1177 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1178    .dirty = {
1179       .mesa = (_NEW_COLOR |
1180                _NEW_BUFFERS),
1181       .brw = BRW_NEW_BATCH,
1182       .cache = 0
1183    },
1184    .emit = brw_update_renderbuffer_surfaces,
1185 };
1186
1187 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1188    .dirty = {
1189       .mesa = _NEW_BUFFERS,
1190       .brw = BRW_NEW_BATCH,
1191       .cache = 0
1192    },
1193    .emit = brw_update_renderbuffer_surfaces,
1194 };
1195
1196 /**
1197  * Construct SURFACE_STATE objects for enabled textures.
1198  */
1199 static void
1200 brw_update_texture_surfaces(struct brw_context *brw)
1201 {
1202    struct gl_context *ctx = &brw->intel.ctx;
1203
1204    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1205       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1206       const GLuint surf = SURF_INDEX_TEXTURE(i);
1207
1208       /* _NEW_TEXTURE */
1209       if (texUnit->_ReallyEnabled) {
1210          brw->intel.vtbl.update_texture_surface(ctx, i);
1211       } else {
1212          brw->wm.surf_offset[surf] = 0;
1213       }
1214
1215       /* For now, just mirror the texture setup to the VS slots. */
1216       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
1217          brw->wm.surf_offset[surf];
1218    }
1219
1220    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1221 }
1222
1223 const struct brw_tracked_state brw_texture_surfaces = {
1224    .dirty = {
1225       .mesa = _NEW_TEXTURE,
1226       .brw = BRW_NEW_BATCH,
1227       .cache = 0
1228    },
1229    .emit = brw_update_texture_surfaces,
1230 };
1231
1232 /**
1233  * Constructs the binding table for the WM surface state, which maps unit
1234  * numbers to surface state objects.
1235  */
1236 static void
1237 brw_upload_wm_binding_table(struct brw_context *brw)
1238 {
1239    uint32_t *bind;
1240    int i;
1241
1242    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1243     * space for the binding table.
1244     */
1245    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1246                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1247                           32, &brw->wm.bind_bo_offset);
1248
1249    /* BRW_NEW_SURFACES */
1250    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1251       bind[i] = brw->wm.surf_offset[i];
1252    }
1253
1254    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1255 }
1256
1257 const struct brw_tracked_state brw_wm_binding_table = {
1258    .dirty = {
1259       .mesa = 0,
1260       .brw = (BRW_NEW_BATCH |
1261               BRW_NEW_SURFACES),
1262       .cache = 0
1263    },
1264    .emit = brw_upload_wm_binding_table,
1265 };
1266
1267 void
1268 gen4_init_vtable_surface_functions(struct brw_context *brw)
1269 {
1270    struct intel_context *intel = &brw->intel;
1271
1272    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1273    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1274    intel->vtbl.update_null_renderbuffer_surface =
1275       brw_update_null_renderbuffer_surface;
1276    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1277 }