src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_RGBX8888] = 0,
 295       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 296       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 297       [MESA_FORMAT_XRGB8888_REV] = 0,
 298       [MESA_FORMAT_RGB888] = 0,
 299       [MESA_FORMAT_BGR888] = 0,
 300       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 301       [MESA_FORMAT_RGB565_REV] = 0,
 302       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 303       [MESA_FORMAT_ARGB4444_REV] = 0,
 304       [MESA_FORMAT_RGBA5551] = 0,
 305       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 306       [MESA_FORMAT_ARGB1555_REV] = 0,
 307       [MESA_FORMAT_AL44] = 0,
 308       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 309       [MESA_FORMAT_AL88_REV] = 0,
 310       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 311       [MESA_FORMAT_AL1616_REV] = 0,
 312       [MESA_FORMAT_RGB332] = 0,
 313       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 314       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 315       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 316       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 317       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 318       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 319       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 320       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 321       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 322       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 323       [MESA_FORMAT_RG88] = 0,
 324       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 325       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 326       [MESA_FORMAT_RG1616_REV] = 0,
 327       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 328       [MESA_FORMAT_Z24_S8] = 0,
 329       [MESA_FORMAT_S8_Z24] = 0,
 330       [MESA_FORMAT_Z16] = 0,
 331       [MESA_FORMAT_X8_Z24] = 0,
 332       [MESA_FORMAT_Z24_X8] = 0,
 333       [MESA_FORMAT_Z32] = 0,
 334       [MESA_FORMAT_S8] = 0,
 335
 336       [MESA_FORMAT_SRGB8] = 0,
 337       [MESA_FORMAT_SRGBA8] = 0,
 338       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 340       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 341       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 343       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 344       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 345
 346       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 347       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 348       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 349       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 350       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 351       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 352
 353       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 354       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 355       [MESA_FORMAT_RGB_FLOAT32] = 0,
 356       [MESA_FORMAT_RGB_FLOAT16] = 0,
 357       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 358       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 361       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 362       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 363       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 364       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 365       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 366       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 367       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 368       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 369
 370       [MESA_FORMAT_ALPHA_UINT8] = 0,
 371       [MESA_FORMAT_ALPHA_UINT16] = 0,
 372       [MESA_FORMAT_ALPHA_UINT32] = 0,
 373       [MESA_FORMAT_ALPHA_INT8] = 0,
 374       [MESA_FORMAT_ALPHA_INT16] = 0,
 375       [MESA_FORMAT_ALPHA_INT32] = 0,
 376
 377       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 378       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 379       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 380       [MESA_FORMAT_INTENSITY_INT8] = 0,
 381       [MESA_FORMAT_INTENSITY_INT16] = 0,
 382       [MESA_FORMAT_INTENSITY_INT32] = 0,
 383
 384       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 385       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 386       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 388       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 389       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 390
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 395       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 396       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 397
 398       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 399       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 400       [MESA_FORMAT_RGB_INT8] = 0,
 401       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 402       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 403       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 404       [MESA_FORMAT_RGB_INT16] = 0,
 405       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 406       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 407       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 408       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 409       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 410
 411       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 412       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 413       [MESA_FORMAT_RGB_UINT8] = 0,
 414       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 415       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 416       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 417       [MESA_FORMAT_RGB_UINT16] = 0,
 418       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 419       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 420       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 421       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 422       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 423
 424       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 426       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 427       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 428       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 429       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 430       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 431       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 432       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 433       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 434       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 435
 436       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 437       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 438       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 439       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 440
 441       [MESA_FORMAT_L_LATC1] = 0,
 442       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 443       [MESA_FORMAT_LA_LATC2] = 0,
 444       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 445
 446       [MESA_FORMAT_SIGNED_A8] = 0,
 447       [MESA_FORMAT_SIGNED_L8] = 0,
 448       [MESA_FORMAT_SIGNED_AL88] = 0,
 449       [MESA_FORMAT_SIGNED_I8] = 0,
 450       [MESA_FORMAT_SIGNED_A16] = 0,
 451       [MESA_FORMAT_SIGNED_L16] = 0,
 452       [MESA_FORMAT_SIGNED_AL1616] = 0,
 453       [MESA_FORMAT_SIGNED_I16] = 0,
 454
 455       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 456       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 457
 458       [MESA_FORMAT_Z32_FLOAT] = 0,
 459       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 460    };
 461    assert(mesa_format < MESA_FORMAT_COUNT);
 462    return table[mesa_format];
 463 }
 464
 465 void
 466 brw_init_surface_formats(struct brw_context *brw)
 467 {
 468    struct intel_context *intel = &brw->intel;
 469    struct gl_context *ctx = &intel->ctx;
 470    int gen;
 471    gl_format format;
 472
 473    gen = intel->gen * 10;
 474    if (intel->is_g4x)
 475       gen += 5;
 476
 477    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 478       uint32_t texture, render;
 479       const struct surface_format_info *rinfo, *tinfo;
 480       bool is_integer = _mesa_is_format_integer_color(format);
 481
 482       render = texture = brw_format_for_mesa_format(format);
 483       tinfo = &surface_formats[texture];
 484
 485       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 486        * it.
 487        */
 488       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 489          continue;
 490
 491       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 492          ctx->TextureFormatSupported[format] = true;
 493
 494       /* Re-map some render target formats to make them supported when they
 495        * wouldn't be using their format for texturing.
 496        */
 497       switch (render) {
 498          /* For these formats, we just need to read/write the first
 499           * channel into R, which is to say that we just treat them as
 500           * GL_RED.
 501           */
 502       case BRW_SURFACEFORMAT_I32_FLOAT:
 503       case BRW_SURFACEFORMAT_L32_FLOAT:
 504          render = BRW_SURFACEFORMAT_R32_FLOAT;
 505          break;
 506       case BRW_SURFACEFORMAT_I16_FLOAT:
 507       case BRW_SURFACEFORMAT_L16_FLOAT:
 508          render = BRW_SURFACEFORMAT_R16_FLOAT;
 509          break;
 510       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 511          /* XRGB is handled as ARGB because the chips in this family
 512           * cannot render to XRGB targets.  This means that we have to
 513           * mask writes to alpha (ala glColorMask) and reconfigure the
 514           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 515           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 516           * used.
 517           */
 518          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 519          break;
 520       }
 521
 522       rinfo = &surface_formats[render];
 523
 524       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 525        * integer, so we don't need hardware support for blending on it.  Other
 526        * than that, GL in general requires alpha blending for render targets,
 527        * even though we don't support it for some formats.
 528        */
 529       if (gen >= rinfo->render_target &&
 530           (gen >= rinfo->alpha_blend || is_integer)) {
 531          brw->render_target_format[format] = render;
 532          brw->format_supported_as_render_target[format] = true;
 533       }
 534    }
 535
 536    /* We will check this table for FBO completeness, but the surface format
 537     * table above only covered color rendering.
 538     */
 539    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 540    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 541    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 542    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 543    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 544    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 545
 546    /* We remap depth formats to a supported texturing format in
 547     * translate_tex_format().
 548     */
 549    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 550    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 551    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 552    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 553    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 554 }
 555
 556 bool
 557 brw_render_target_supported(struct intel_context *intel,
 558                             struct gl_renderbuffer *rb)
 559 {
 560    struct brw_context *brw = brw_context(&intel->ctx);
 561    gl_format format = rb->Format;
 562
 563    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 564     * we would consider them renderable even though we don't have surface
 565     * support for their alpha behavior and don't have the blending unit
 566     * available to fake it like we do for XRGB8888.  Force them to being
 567     * unsupported.
 568     */
 569    if ((rb->_BaseFormat != GL_RGBA &&
 570         rb->_BaseFormat != GL_RG &&
 571         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 572       return false;
 573
 574    /* Under some conditions, MSAA is not supported for formats whose width is
 575     * more than 64 bits.
 576     */
 577    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 578       /* Gen6: MSAA on >64 bit formats is unsupported. */
 579       if (intel->gen <= 6)
 580          return false;
 581
 582       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 583       if (rb->NumSamples >= 8)
 584          return false;
 585    }
 586
 587    return brw->format_supported_as_render_target[format];
 588 }
 589
 590 GLuint
 591 translate_tex_format(gl_format mesa_format,
 592                      GLenum internal_format,
 593                      GLenum depth_mode,
 594                      GLenum srgb_decode)
 595 {
 596    switch( mesa_format ) {
 597
 598    case MESA_FORMAT_Z16:
 599       return BRW_SURFACEFORMAT_I16_UNORM;
 600
 601    case MESA_FORMAT_S8_Z24:
 602    case MESA_FORMAT_X8_Z24:
 603       return BRW_SURFACEFORMAT_I24X8_UNORM;
 604
 605    case MESA_FORMAT_Z32_FLOAT:
 606       return BRW_SURFACEFORMAT_I32_FLOAT;
 607
 608    case MESA_FORMAT_Z32_FLOAT_X24S8:
 609       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 610
 611    case MESA_FORMAT_SARGB8:
 612    case MESA_FORMAT_SLA8:
 613    case MESA_FORMAT_SL8:
 614       if (srgb_decode == GL_DECODE_EXT)
 615          return brw_format_for_mesa_format(mesa_format);
 616       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 617          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 618
 619    case MESA_FORMAT_RGBA_FLOAT32:
 620       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 621        * assertion below.
 622        */
 623       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 624
 625    default:
 626       assert(brw_format_for_mesa_format(mesa_format) != 0);
 627       return brw_format_for_mesa_format(mesa_format);
 628    }
 629 }
 630
 631 uint32_t
 632 brw_get_surface_tiling_bits(uint32_t tiling)
 633 {
 634    switch (tiling) {
 635    case I915_TILING_X:
 636       return BRW_SURFACE_TILED;
 637    case I915_TILING_Y:
 638       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 639    default:
 640       return 0;
 641    }
 642 }
 643
 644
 645 uint32_t
 646 brw_get_surface_num_multisamples(unsigned num_samples)
 647 {
 648    if (num_samples > 0)
 649       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 650    else
 651       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 652 }
 653
 654
 655 static void
 656 brw_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit)
 657 {
 658    struct brw_context *brw = brw_context(ctx);
 659    struct intel_context *intel = &brw->intel;
 660    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 661    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 662    uint32_t *surf;
 663    struct intel_buffer_object *intel_obj =
 664       intel_buffer_object(tObj->BufferObject);
 665    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 666    gl_format format = tObj->_BufferObjectFormat;
 667    uint32_t brw_format = brw_format_for_mesa_format(format);
 668    int texel_size = _mesa_get_format_bytes(format);
 669
 670    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 671       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 672                     _mesa_get_format_name(format));
 673    }
 674
 675    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 676                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 677
 678    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 679               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 680
 681    if (intel->gen >= 6)
 682       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 683
 684    if (bo) {
 685       surf[1] = bo->offset; /* reloc */
 686
 687       /* Emit relocation to surface contents. */
 688       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 689                               brw->wm.surf_offset[surf_index] + 4,
 690                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 691
 692       int w = intel_obj->Base.Size / texel_size;
 693       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 694                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 695       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 696                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 697    } else {
 698       surf[1] = 0;
 699       surf[2] = 0;
 700       surf[3] = 0;
 701    }
 702
 703    surf[4] = 0;
 704    surf[5] = 0;
 705 }
 706
 707 static void
 708 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 709 {
 710    struct brw_context *brw = brw_context(ctx);
 711    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 712    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 713    struct intel_mipmap_tree *mt = intelObj->mt;
 714    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 715    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 716    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 717    uint32_t *surf;
 718    int width, height, depth;
 719
 720    if (tObj->Target == GL_TEXTURE_BUFFER) {
 721       brw_update_buffer_texture_surface(ctx, unit);
 722       return;
 723    }
 724
 725    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 726
 727    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 728                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 729
 730    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 731               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 732               BRW_SURFACE_CUBEFACE_ENABLES |
 733               (translate_tex_format(mt->format,
 734                                     firstImage->InternalFormat,
 735                                     sampler->DepthMode,
 736                                     sampler->sRGBDecode) <<
 737                BRW_SURFACE_FORMAT_SHIFT));
 738
 739    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 740
 741    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 742               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 743               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 744
 745    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 746               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 747               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 748               BRW_SURFACE_PITCH_SHIFT);
 749
 750    surf[4] = 0;
 751
 752    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 753
 754    /* Emit relocation to surface contents */
 755    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 756                            brw->wm.surf_offset[surf_index] + 4,
 757                            intelObj->mt->region->bo, 0,
 758                            I915_GEM_DOMAIN_SAMPLER, 0);
 759 }
 760
 761 /**
 762  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 763  * read from this buffer with Data Port Read instructions/messages.
 764  */
 765 void
 766 brw_create_constant_surface(struct brw_context *brw,
 767                             drm_intel_bo *bo,
 768                             int width,
 769                             uint32_t *out_offset)
 770 {
 771    struct intel_context *intel = &brw->intel;
 772    const GLint w = width - 1;
 773    uint32_t *surf;
 774
 775    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 776                           6 * 4, 32, out_offset);
 777
 778    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 779               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 780               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 781
 782    if (intel->gen >= 6)
 783       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 784
 785    surf[1] = bo->offset; /* reloc */
 786
 787    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 788               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 789
 790    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 791               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 792
 793    surf[4] = 0;
 794    surf[5] = 0;
 795
 796    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 797     * bspec ("Data Cache") says that the data cache does not exist as
 798     * a separate cache and is just the sampler cache.
 799     */
 800    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 801                            *out_offset + 4,
 802                            bo, 0,
 803                            I915_GEM_DOMAIN_SAMPLER, 0);
 804 }
 805
 806 /**
 807  * Set up a binding table entry for use by stream output logic (transform
 808  * feedback).
 809  *
 810  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 811  */
 812 void
 813 brw_update_sol_surface(struct brw_context *brw,
 814                        struct gl_buffer_object *buffer_obj,
 815                        uint32_t *out_offset, unsigned num_vector_components,
 816                        unsigned stride_dwords, unsigned offset_dwords)
 817 {
 818    struct intel_context *intel = &brw->intel;
 819    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 820    drm_intel_bo *bo =
 821       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 822    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 823                                     out_offset);
 824    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 825    uint32_t offset_bytes = 4 * offset_dwords;
 826    size_t size_dwords = buffer_obj->Size / 4;
 827    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 828
 829    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 830     * too big to map using a single binding table entry?
 831     */
 832    assert((size_dwords - offset_dwords) / stride_dwords
 833           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 834
 835    if (size_dwords > offset_dwords + num_vector_components) {
 836       /* There is room for at least 1 transform feedback output in the buffer.
 837        * Compute the number of additional transform feedback outputs the
 838        * buffer has room for.
 839        */
 840       buffer_size_minus_1 =
 841          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 842    } else {
 843       /* There isn't even room for a single transform feedback output in the
 844        * buffer.  We can't configure the binding table entry to prevent output
 845        * entirely; we'll have to rely on the geometry shader to detect
 846        * overflow.  But to minimize the damage in case of a bug, set up the
 847        * binding table entry to just allow a single output.
 848        */
 849       buffer_size_minus_1 = 0;
 850    }
 851    width = buffer_size_minus_1 & 0x7f;
 852    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 853    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 854
 855    switch (num_vector_components) {
 856    case 1:
 857       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 858       break;
 859    case 2:
 860       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 861       break;
 862    case 3:
 863       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 864       break;
 865    case 4:
 866       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 867       break;
 868    default:
 869       assert(!"Invalid vector size for transform feedback output");
 870       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 871       break;
 872    }
 873
 874    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 875       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 876       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 877       BRW_SURFACE_RC_READ_WRITE;
 878    surf[1] = bo->offset + offset_bytes; /* reloc */
 879    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 880               height << BRW_SURFACE_HEIGHT_SHIFT);
 881    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 882               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 883    surf[4] = 0;
 884    surf[5] = 0;
 885
 886    /* Emit relocation to surface contents. */
 887    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 888                            *out_offset + 4,
 889                            bo, offset_bytes,
 890                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 891 }
 892
 893 /* Creates a new WM constant buffer reflecting the current fragment program's
 894  * constants, if needed by the fragment program.
 895  *
 896  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 897  * state atom.
 898  */
 899 static void
 900 brw_upload_wm_pull_constants(struct brw_context *brw)
 901 {
 902    struct gl_context *ctx = &brw->intel.ctx;
 903    struct intel_context *intel = &brw->intel;
 904    /* BRW_NEW_FRAGMENT_PROGRAM */
 905    struct brw_fragment_program *fp =
 906       (struct brw_fragment_program *) brw->fragment_program;
 907    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 908    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 909    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 910    float *constants;
 911    unsigned int i;
 912
 913    _mesa_load_state_parameters(ctx, params);
 914
 915    /* CACHE_NEW_WM_PROG */
 916    if (brw->wm.prog_data->nr_pull_params == 0) {
 917       if (brw->wm.const_bo) {
 918          drm_intel_bo_unreference(brw->wm.const_bo);
 919          brw->wm.const_bo = NULL;
 920          brw->wm.surf_offset[surf_index] = 0;
 921          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 922       }
 923       return;
 924    }
 925
 926    drm_intel_bo_unreference(brw->wm.const_bo);
 927    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 928                                          size, 64);
 929
 930    /* _NEW_PROGRAM_CONSTANTS */
 931    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 932    constants = brw->wm.const_bo->virtual;
 933    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 934       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 935                                    brw->wm.prog_data->pull_param[i]);
 936    }
 937    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 938
 939    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 940                                        params->NumParameters,
 941                                        &brw->wm.surf_offset[surf_index]);
 942
 943    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 944 }
 945
 946 const struct brw_tracked_state brw_wm_pull_constants = {
 947    .dirty = {
 948       .mesa = (_NEW_PROGRAM_CONSTANTS),
 949       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 950       .cache = CACHE_NEW_WM_PROG,
 951    },
 952    .emit = brw_upload_wm_pull_constants,
 953 };
 954
 955 static void
 956 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 957 {
 958    struct intel_context *intel = &brw->intel;
 959    uint32_t *surf;
 960
 961    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 962                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 963
 964    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 965               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 966    if (intel->gen < 6) {
 967       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 968                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 969                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 970                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 971    }
 972    surf[1] = 0;
 973    surf[2] = 0;
 974    surf[3] = 0;
 975    surf[4] = 0;
 976    surf[5] = 0;
 977 }
 978
 979 /**
 980  * Sets up a surface state structure to point at the given region.
 981  * While it is only used for the front/back buffer currently, it should be
 982  * usable for further buffers when doing ARB_draw_buffer support.
 983  */
 984 static void
 985 brw_update_renderbuffer_surface(struct brw_context *brw,
 986                                 struct gl_renderbuffer *rb,
 987                                 unsigned int unit)
 988 {
 989    struct intel_context *intel = &brw->intel;
 990    struct gl_context *ctx = &intel->ctx;
 991    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 992    struct intel_mipmap_tree *mt = irb->mt;
 993    struct intel_region *region;
 994    uint32_t *surf;
 995    uint32_t tile_x, tile_y;
 996    uint32_t format = 0;
 997    gl_format rb_format = intel_rb_format(irb);
 998
 999    if (irb->tex_image && !brw->has_surface_tile_offset) {
1000       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1001
1002       if (tile_x != 0 || tile_y != 0) {
1003          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1004           * destination in a miptree unless you actually setup your renderbuffer
1005           * as a miptree and used the fragile lod/array_index/etc. controls to
1006           * select the image.  So, instead, we just make a new single-level
1007           * miptree and render into that.
1008           */
1009          struct intel_context *intel = intel_context(ctx);
1010          struct intel_texture_image *intel_image =
1011             intel_texture_image(irb->tex_image);
1012          struct intel_mipmap_tree *new_mt;
1013          int width, height, depth;
1014
1015          intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth);
1016
1017          new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target,
1018                                        intel_image->base.Base.TexFormat,
1019                                        intel_image->base.Base.Level,
1020                                        intel_image->base.Base.Level,
1021                                        width, height, depth,
1022                                        true,
1023                                        0 /* num_samples */,
1024                                        false /* msaa_is_interleaved */);
1025
1026          intel_miptree_copy_teximage(intel, intel_image, new_mt);
1027          intel_miptree_reference(&irb->mt, intel_image->mt);
1028          intel_renderbuffer_set_draw_offset(irb);
1029          intel_miptree_release(&new_mt);
1030
1031          mt = irb->mt;
1032       }
1033    }
1034
1035    region = irb->mt->region;
1036
1037    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1038                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1039
1040    switch (rb_format) {
1041    case MESA_FORMAT_SARGB8:
1042       /* _NEW_BUFFERS
1043        *
1044        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1045        * blend/update as sRGB.
1046        */
1047       if (ctx->Color.sRGBEnabled)
1048          format = brw_format_for_mesa_format(rb_format);
1049       else
1050          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1051       break;
1052    default:
1053       format = brw->render_target_format[rb_format];
1054       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1055          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1056                        __FUNCTION__, _mesa_get_format_name(rb_format));
1057       }
1058       break;
1059    }
1060
1061    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1062               format << BRW_SURFACE_FORMAT_SHIFT);
1063
1064    /* reloc */
1065    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1066               region->bo->offset);
1067
1068    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1069               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1070
1071    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1072               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
1073
1074    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1075
1076    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1077    /* Note that the low bits of these fields are missing, so
1078     * there's the possibility of getting in trouble.
1079     */
1080    assert(tile_x % 4 == 0);
1081    assert(tile_y % 2 == 0);
1082    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1083               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1084               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1085
1086    if (intel->gen < 6) {
1087       /* _NEW_COLOR */
1088       if (!ctx->Color.ColorLogicOpEnabled &&
1089           (ctx->Color.BlendEnabled & (1 << unit)))
1090          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1091
1092       if (!ctx->Color.ColorMask[unit][0])
1093          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1094       if (!ctx->Color.ColorMask[unit][1])
1095          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1096       if (!ctx->Color.ColorMask[unit][2])
1097          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1098
1099       /* As mentioned above, disable writes to the alpha component when the
1100        * renderbuffer is XRGB.
1101        */
1102       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1103           !ctx->Color.ColorMask[unit][3]) {
1104          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1105       }
1106    }
1107
1108    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1109                            brw->wm.surf_offset[unit] + 4,
1110                            region->bo,
1111                            surf[1] - region->bo->offset,
1112                            I915_GEM_DOMAIN_RENDER,
1113                            I915_GEM_DOMAIN_RENDER);
1114 }
1115
1116 /**
1117  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1118  */
1119 static void
1120 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1121 {
1122    struct intel_context *intel = &brw->intel;
1123    struct gl_context *ctx = &brw->intel.ctx;
1124    GLuint i;
1125
1126    /* _NEW_BUFFERS | _NEW_COLOR */
1127    /* Update surfaces for drawing buffers */
1128    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1129       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1130          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1131             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1132          } else {
1133             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1134          }
1135       }
1136    } else {
1137       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1138    }
1139    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1140 }
1141
1142 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1143    .dirty = {
1144       .mesa = (_NEW_COLOR |
1145                _NEW_BUFFERS),
1146       .brw = BRW_NEW_BATCH,
1147       .cache = 0
1148    },
1149    .emit = brw_update_renderbuffer_surfaces,
1150 };
1151
1152 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1153    .dirty = {
1154       .mesa = _NEW_BUFFERS,
1155       .brw = BRW_NEW_BATCH,
1156       .cache = 0
1157    },
1158    .emit = brw_update_renderbuffer_surfaces,
1159 };
1160
1161 /**
1162  * Construct SURFACE_STATE objects for enabled textures.
1163  */
1164 static void
1165 brw_update_texture_surfaces(struct brw_context *brw)
1166 {
1167    struct gl_context *ctx = &brw->intel.ctx;
1168
1169    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1170       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1171       const GLuint surf = SURF_INDEX_TEXTURE(i);
1172
1173       /* _NEW_TEXTURE */
1174       if (texUnit->_ReallyEnabled) {
1175          brw->intel.vtbl.update_texture_surface(ctx, i);
1176       } else {
1177          brw->wm.surf_offset[surf] = 0;
1178       }
1179
1180       /* For now, just mirror the texture setup to the VS slots. */
1181       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
1182          brw->wm.surf_offset[surf];
1183    }
1184
1185    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1186 }
1187
1188 const struct brw_tracked_state brw_texture_surfaces = {
1189    .dirty = {
1190       .mesa = _NEW_TEXTURE,
1191       .brw = BRW_NEW_BATCH,
1192       .cache = 0
1193    },
1194    .emit = brw_update_texture_surfaces,
1195 };
1196
1197 /**
1198  * Constructs the binding table for the WM surface state, which maps unit
1199  * numbers to surface state objects.
1200  */
1201 static void
1202 brw_upload_wm_binding_table(struct brw_context *brw)
1203 {
1204    uint32_t *bind;
1205    int i;
1206
1207    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1208     * space for the binding table.
1209     */
1210    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1211                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1212                           32, &brw->wm.bind_bo_offset);
1213
1214    /* BRW_NEW_SURFACES */
1215    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1216       bind[i] = brw->wm.surf_offset[i];
1217    }
1218
1219    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1220 }
1221
1222 const struct brw_tracked_state brw_wm_binding_table = {
1223    .dirty = {
1224       .mesa = 0,
1225       .brw = (BRW_NEW_BATCH |
1226               BRW_NEW_SURFACES),
1227       .cache = 0
1228    },
1229    .emit = brw_upload_wm_binding_table,
1230 };
1231
1232 void
1233 gen4_init_vtable_surface_functions(struct brw_context *brw)
1234 {
1235    struct intel_context *intel = &brw->intel;
1236
1237    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1238    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1239    intel->vtbl.update_null_renderbuffer_surface =
1240       brw_update_null_renderbuffer_surface;
1241    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1242 }