2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/mtypes.h"
34 #include "main/texstore.h"
35 #include "shader/prog_parameter.h"
37 #include "intel_mipmap_tree.h"
38 #include "intel_batchbuffer.h"
39 #include "intel_tex.h"
40 #include "intel_fbo.h"
42 #include "brw_context.h"
43 #include "brw_state.h"
44 #include "brw_defines.h"
47 static GLuint translate_tex_target( GLenum target )
51 return BRW_SURFACE_1D;
53 case GL_TEXTURE_RECTANGLE_NV:
54 return BRW_SURFACE_2D;
57 return BRW_SURFACE_2D;
60 return BRW_SURFACE_3D;
62 case GL_TEXTURE_CUBE_MAP:
63 return BRW_SURFACE_CUBE;
72 static GLuint translate_tex_format( gl_format mesa_format,
73 GLenum internal_format,
76 switch( mesa_format ) {
78 return BRW_SURFACEFORMAT_L8_UNORM;
81 return BRW_SURFACEFORMAT_I8_UNORM;
84 return BRW_SURFACEFORMAT_A8_UNORM;
86 case MESA_FORMAT_AL88:
87 return BRW_SURFACEFORMAT_L8A8_UNORM;
89 case MESA_FORMAT_AL1616:
90 return BRW_SURFACEFORMAT_L16A16_UNORM;
92 case MESA_FORMAT_RGB888:
93 assert(0); /* not supported for sampling */
94 return BRW_SURFACEFORMAT_R8G8B8_UNORM;
96 case MESA_FORMAT_ARGB8888:
97 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
99 case MESA_FORMAT_XRGB8888:
100 return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
102 case MESA_FORMAT_RGBA8888_REV:
103 _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
104 return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
106 case MESA_FORMAT_RGB565:
107 return BRW_SURFACEFORMAT_B5G6R5_UNORM;
109 case MESA_FORMAT_ARGB1555:
110 return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
112 case MESA_FORMAT_ARGB4444:
113 return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
115 case MESA_FORMAT_YCBCR_REV:
116 return BRW_SURFACEFORMAT_YCRCB_NORMAL;
118 case MESA_FORMAT_YCBCR:
119 return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
121 case MESA_FORMAT_RGB_FXT1:
122 case MESA_FORMAT_RGBA_FXT1:
123 return BRW_SURFACEFORMAT_FXT1;
125 case MESA_FORMAT_Z16:
126 if (depth_mode == GL_INTENSITY)
127 return BRW_SURFACEFORMAT_I16_UNORM;
128 else if (depth_mode == GL_ALPHA)
129 return BRW_SURFACEFORMAT_A16_UNORM;
131 return BRW_SURFACEFORMAT_L16_UNORM;
133 case MESA_FORMAT_RGB_DXT1:
134 return BRW_SURFACEFORMAT_DXT1_RGB;
136 case MESA_FORMAT_RGBA_DXT1:
137 return BRW_SURFACEFORMAT_BC1_UNORM;
139 case MESA_FORMAT_RGBA_DXT3:
140 return BRW_SURFACEFORMAT_BC2_UNORM;
142 case MESA_FORMAT_RGBA_DXT5:
143 return BRW_SURFACEFORMAT_BC3_UNORM;
145 case MESA_FORMAT_SARGB8:
146 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
148 case MESA_FORMAT_SLA8:
149 return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
151 case MESA_FORMAT_SL8:
152 return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
154 case MESA_FORMAT_SRGB_DXT1:
155 return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
157 case MESA_FORMAT_S8_Z24:
158 /* XXX: these different surface formats don't seem to
159 * make any difference for shadow sampler/compares.
161 if (depth_mode == GL_INTENSITY)
162 return BRW_SURFACEFORMAT_I24X8_UNORM;
163 else if (depth_mode == GL_ALPHA)
164 return BRW_SURFACEFORMAT_A24X8_UNORM;
166 return BRW_SURFACEFORMAT_L24X8_UNORM;
168 case MESA_FORMAT_DUDV8:
169 return BRW_SURFACEFORMAT_R8G8_SNORM;
171 case MESA_FORMAT_SIGNED_RGBA8888_REV:
172 return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
181 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
184 case I915_TILING_NONE:
185 surf->ss3.tiled_surface = 0;
186 surf->ss3.tile_walk = 0;
189 surf->ss3.tiled_surface = 1;
190 surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
193 surf->ss3.tiled_surface = 1;
194 surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
200 brw_create_texture_surface( struct brw_context *brw,
201 struct brw_surface_key *key )
203 struct brw_surface_state surf;
206 memset(&surf, 0, sizeof(surf));
208 surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
209 surf.ss0.surface_type = translate_tex_target(key->target);
211 surf.ss0.surface_format = translate_tex_format(key->format,
212 key->internal_format,
216 switch (key->depth) {
218 surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
222 surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
225 surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
230 /* This is ok for all textures with channel width 8bit or less:
232 /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
234 surf.ss1.base_addr = key->bo->offset; /* reloc */
236 surf.ss1.base_addr = key->offset;
238 surf.ss2.mip_count = key->last_level - key->first_level;
239 surf.ss2.width = key->width - 1;
240 surf.ss2.height = key->height - 1;
241 brw_set_surface_tiling(&surf, key->tiling);
242 surf.ss3.pitch = (key->pitch * key->cpp) - 1;
243 surf.ss3.depth = key->depth - 1;
245 surf.ss4.min_lod = 0;
247 if (key->target == GL_TEXTURE_CUBE_MAP) {
248 surf.ss0.cube_pos_x = 1;
249 surf.ss0.cube_pos_y = 1;
250 surf.ss0.cube_pos_z = 1;
251 surf.ss0.cube_neg_x = 1;
252 surf.ss0.cube_neg_y = 1;
253 surf.ss0.cube_neg_z = 1;
256 bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
258 &key->bo, key->bo ? 1 : 0,
259 &surf, sizeof(surf));
262 /* Emit relocation to surface contents */
263 dri_bo_emit_reloc(bo,
264 I915_GEM_DOMAIN_SAMPLER, 0,
266 offsetof(struct brw_surface_state, ss1),
273 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
275 struct brw_context *brw = brw_context(ctx);
276 struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
277 struct intel_texture_object *intelObj = intel_texture_object(tObj);
278 struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
279 struct brw_surface_key key;
280 const GLuint surf = SURF_INDEX_TEXTURE(unit);
282 memset(&key, 0, sizeof(key));
284 if (intelObj->imageOverride) {
285 key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
286 key.depth = intelObj->depthOverride;
288 key.offset = intelObj->textureOffset;
290 key.format = firstImage->TexFormat;
291 key.internal_format = firstImage->InternalFormat;
292 key.pitch = intelObj->mt->pitch;
293 key.depth = firstImage->Depth;
294 key.bo = intelObj->mt->region->buffer;
298 key.target = tObj->Target;
299 key.depthmode = tObj->DepthMode;
300 key.first_level = intelObj->firstLevel;
301 key.last_level = intelObj->lastLevel;
302 key.width = firstImage->Width;
303 key.height = firstImage->Height;
304 key.cpp = intelObj->mt->cpp;
305 key.tiling = intelObj->mt->region->tiling;
307 dri_bo_unreference(brw->wm.surf_bo[surf]);
308 brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
311 &key.bo, key.bo ? 1 : 0,
313 if (brw->wm.surf_bo[surf] == NULL) {
314 brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
321 * Create the constant buffer surface. Vertex/fragment shader constants will be
322 * read from this buffer with Data Port Read instructions/messages.
325 brw_create_constant_surface( struct brw_context *brw,
326 struct brw_surface_key *key )
328 const GLint w = key->width - 1;
329 struct brw_surface_state surf;
332 memset(&surf, 0, sizeof(surf));
334 surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
335 surf.ss0.surface_type = BRW_SURFACE_BUFFER;
336 surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
339 surf.ss1.base_addr = key->bo->offset; /* reloc */
341 surf.ss2.width = w & 0x7f; /* bits 6:0 of size or width */
342 surf.ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */
343 surf.ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */
344 surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
345 brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
347 bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
350 &surf, sizeof(surf));
352 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
353 * bspec ("Data Cache") says that the data cache does not exist as
354 * a separate cache and is just the sampler cache.
356 drm_intel_bo_emit_reloc(bo, offsetof(struct brw_surface_state, ss1),
358 I915_GEM_DOMAIN_SAMPLER, 0);
363 /* Creates a new WM constant buffer reflecting the current fragment program's
364 * constants, if needed by the fragment program.
366 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
369 static drm_intel_bo *
370 brw_wm_update_constant_buffer(struct brw_context *brw)
372 struct intel_context *intel = &brw->intel;
373 struct brw_fragment_program *fp =
374 (struct brw_fragment_program *) brw->fragment_program;
375 const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
376 const int size = params->NumParameters * 4 * sizeof(GLfloat);
377 drm_intel_bo *const_buffer;
379 /* BRW_NEW_FRAGMENT_PROGRAM */
380 if (!fp->use_const_buffer)
383 const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
386 /* _NEW_PROGRAM_CONSTANTS */
387 dri_bo_subdata(const_buffer, 0, size, params->ParameterValues);
393 * Update the surface state for a WM constant buffer.
394 * The constant buffer will be (re)allocated here if needed.
397 brw_update_wm_constant_surface( GLcontext *ctx,
400 struct brw_context *brw = brw_context(ctx);
401 struct brw_surface_key key;
402 struct brw_fragment_program *fp =
403 (struct brw_fragment_program *) brw->fragment_program;
404 const struct gl_program_parameter_list *params =
405 fp->program.Base.Parameters;
407 /* If we're in this state update atom, we need to update WM constants, so
408 * free the old buffer and create a new one for the new contents.
410 dri_bo_unreference(fp->const_buffer);
411 fp->const_buffer = brw_wm_update_constant_buffer(brw);
413 /* If there's no constant buffer, then no surface BO is needed to point at
416 if (fp->const_buffer == NULL) {
417 drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
418 brw->wm.surf_bo[surf] = NULL;
422 memset(&key, 0, sizeof(key));
424 key.format = MESA_FORMAT_RGBA_FLOAT32;
425 key.internal_format = GL_RGBA;
426 key.bo = fp->const_buffer;
427 key.depthmode = GL_NONE;
428 key.pitch = params->NumParameters;
429 key.width = params->NumParameters;
435 printf("%s:\n", __FUNCTION__);
436 printf(" width %d height %d depth %d cpp %d pitch %d\n",
437 key.width, key.height, key.depth, key.cpp, key.pitch);
440 dri_bo_unreference(brw->wm.surf_bo[surf]);
441 brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
446 if (brw->wm.surf_bo[surf] == NULL) {
447 brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
449 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
453 * Updates surface / buffer for fragment shader constant buffer, if
456 * This consumes the state updates for the constant buffer, and produces
457 * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
458 * inclusion in the binding table.
460 static void prepare_wm_constant_surface(struct brw_context *brw )
462 GLcontext *ctx = &brw->intel.ctx;
463 struct brw_fragment_program *fp =
464 (struct brw_fragment_program *) brw->fragment_program;
465 GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
467 drm_intel_bo_unreference(fp->const_buffer);
468 fp->const_buffer = brw_wm_update_constant_buffer(brw);
470 /* If there's no constant buffer, then no surface BO is needed to point at
473 if (fp->const_buffer == 0) {
474 if (brw->wm.surf_bo[surf] != NULL) {
475 drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
476 brw->wm.surf_bo[surf] = NULL;
477 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
482 brw_update_wm_constant_surface(ctx, surf);
485 const struct brw_tracked_state brw_wm_constant_surface = {
487 .mesa = (_NEW_PROGRAM_CONSTANTS),
488 .brw = (BRW_NEW_FRAGMENT_PROGRAM),
491 .prepare = prepare_wm_constant_surface,
496 * Sets up a surface state structure to point at the given region.
497 * While it is only used for the front/back buffer currently, it should be
498 * usable for further buffers when doing ARB_draw_buffer support.
501 brw_update_renderbuffer_surface(struct brw_context *brw,
502 struct gl_renderbuffer *rb,
505 struct intel_context *intel = &brw->intel;
506 GLcontext *ctx = &intel->ctx;
507 dri_bo *region_bo = NULL;
508 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
509 struct intel_region *region = irb ? irb->region : NULL;
511 unsigned int surface_type;
512 unsigned int surface_format;
513 unsigned int width, height, pitch, cpp;
514 GLubyte color_mask[4];
515 GLboolean color_blend;
521 memset(&key, 0, sizeof(key));
523 if (region != NULL) {
524 region_bo = region->buffer;
526 key.surface_type = BRW_SURFACE_2D;
527 switch (irb->Base.Format) {
528 /* XRGB and ARGB are treated the same here because the chips in this
529 * family cannot render to XRGB targets. This means that we have to
530 * mask writes to alpha (ala glColorMask) and reconfigure the alpha
531 * blending hardware to use GL_ONE (or GL_ZERO) for cases where
532 * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
534 case MESA_FORMAT_ARGB8888:
535 case MESA_FORMAT_XRGB8888:
536 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
538 case MESA_FORMAT_RGB565:
539 key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
541 case MESA_FORMAT_ARGB1555:
542 key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
544 case MESA_FORMAT_ARGB4444:
545 key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
548 _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
550 key.tiling = region->tiling;
551 if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
552 key.width = rb->Width;
553 key.height = rb->Height;
555 key.width = region->width;
556 key.height = region->height;
558 key.pitch = region->pitch;
559 key.cpp = region->cpp;
560 key.draw_x = region->draw_x;
561 key.draw_y = region->draw_y;
563 key.surface_type = BRW_SURFACE_NULL;
564 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
565 key.tiling = I915_TILING_X;
573 if (intel->gen < 6) {
575 memcpy(key.color_mask, ctx->Color.ColorMask[unit],
576 sizeof(key.color_mask));
578 /* As mentioned above, disable writes to the alpha component when the
579 * renderbuffer is XRGB.
581 if (ctx->DrawBuffer->Visual.alphaBits == 0)
582 key.color_mask[3] = GL_FALSE;
584 key.color_blend = (!ctx->Color._LogicOpEnabled &&
585 (ctx->Color.BlendEnabled & (1 << unit)));
588 dri_bo_unreference(brw->wm.surf_bo[unit]);
589 brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
595 if (brw->wm.surf_bo[unit] == NULL) {
596 struct brw_surface_state surf;
598 memset(&surf, 0, sizeof(surf));
600 surf.ss0.surface_format = key.surface_format;
601 surf.ss0.surface_type = key.surface_type;
602 if (key.tiling == I915_TILING_NONE) {
603 surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp;
605 uint32_t tile_base, tile_x, tile_y;
606 uint32_t pitch = key.pitch * key.cpp;
608 if (key.tiling == I915_TILING_X) {
609 tile_x = key.draw_x % (512 / key.cpp);
610 tile_y = key.draw_y % 8;
611 tile_base = ((key.draw_y / 8) * (8 * pitch));
612 tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096;
615 tile_x = key.draw_x % (128 / key.cpp);
616 tile_y = key.draw_y % 32;
617 tile_base = ((key.draw_y / 32) * (32 * pitch));
618 tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
620 assert(intel->is_g4x || (tile_x == 0 && tile_y == 0));
621 assert(tile_x % 4 == 0);
622 assert(tile_y % 2 == 0);
623 /* Note that the low bits of these fields are missing, so
624 * there's the possibility of getting in trouble.
626 surf.ss1.base_addr = tile_base;
627 surf.ss5.x_offset = tile_x / 4;
628 surf.ss5.y_offset = tile_y / 2;
630 if (region_bo != NULL)
631 surf.ss1.base_addr += region_bo->offset; /* reloc */
633 surf.ss2.width = key.width - 1;
634 surf.ss2.height = key.height - 1;
635 brw_set_surface_tiling(&surf, key.tiling);
636 surf.ss3.pitch = (key.pitch * key.cpp) - 1;
638 if (intel->gen < 6) {
640 surf.ss0.color_blend = key.color_blend;
641 surf.ss0.writedisable_red = !key.color_mask[0];
642 surf.ss0.writedisable_green = !key.color_mask[1];
643 surf.ss0.writedisable_blue = !key.color_mask[2];
644 surf.ss0.writedisable_alpha = !key.color_mask[3];
647 /* Key size will never match key size for textures, so we're safe. */
648 brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
652 &surf, sizeof(surf));
653 if (region_bo != NULL) {
654 /* We might sample from it, and we might render to it, so flag
655 * them both. We might be able to figure out from other state
656 * a more restrictive relocation to emit.
658 drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
659 offsetof(struct brw_surface_state, ss1),
661 surf.ss1.base_addr - region_bo->offset,
662 I915_GEM_DOMAIN_RENDER,
663 I915_GEM_DOMAIN_RENDER);
670 * Constructs the binding table for the WM surface state, which maps unit
671 * numbers to surface state objects.
674 brw_wm_get_binding_table(struct brw_context *brw)
678 assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF);
680 bind_bo = brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND,
682 brw->wm.surf_bo, brw->wm.nr_surfaces,
685 if (bind_bo == NULL) {
686 GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
687 uint32_t data[BRW_WM_MAX_SURF];
690 for (i = 0; i < brw->wm.nr_surfaces; i++)
691 if (brw->wm.surf_bo[i])
692 data[i] = brw->wm.surf_bo[i]->offset;
696 bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
698 brw->wm.surf_bo, brw->wm.nr_surfaces,
701 /* Emit binding table relocations to surface state */
702 for (i = 0; i < BRW_WM_MAX_SURF; i++) {
703 if (brw->wm.surf_bo[i] != NULL) {
704 dri_bo_emit_reloc(bind_bo,
705 I915_GEM_DOMAIN_INSTRUCTION, 0,
716 static void prepare_wm_surfaces(struct brw_context *brw )
718 GLcontext *ctx = &brw->intel.ctx;
722 /* _NEW_BUFFERS | _NEW_COLOR */
723 /* Update surfaces for drawing buffers */
724 if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
725 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
726 brw_update_renderbuffer_surface(brw,
727 ctx->DrawBuffer->_ColorDrawBuffers[i],
731 brw_update_renderbuffer_surface(brw, NULL, 0);
734 old_nr_surfaces = brw->wm.nr_surfaces;
735 brw->wm.nr_surfaces = BRW_MAX_DRAW_BUFFERS;
737 if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
738 brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
740 /* Update surfaces for textures */
741 for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
742 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
743 const GLuint surf = SURF_INDEX_TEXTURE(i);
745 /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
746 if (texUnit->_ReallyEnabled) {
747 brw_update_texture_surface(ctx, i);
748 brw->wm.nr_surfaces = surf + 1;
750 dri_bo_unreference(brw->wm.surf_bo[surf]);
751 brw->wm.surf_bo[surf] = NULL;
755 dri_bo_unreference(brw->wm.bind_bo);
756 brw->wm.bind_bo = brw_wm_get_binding_table(brw);
758 if (brw->wm.nr_surfaces != old_nr_surfaces)
759 brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
762 const struct brw_tracked_state brw_wm_surfaces = {
764 .mesa = (_NEW_COLOR |
767 .brw = (BRW_NEW_CONTEXT |
768 BRW_NEW_WM_SURFACES),
771 .prepare = prepare_wm_surfaces,