src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/context.h"
  34 #include "main/mtypes.h"
  35 #include "main/samplerobj.h"
  36 #include "program/prog_parameter.h"
  37
  38 #include "intel_mipmap_tree.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_fbo.h"
  42 #include "intel_buffer_objects.h"
  43
  44 #include "brw_context.h"
  45 #include "brw_state.h"
  46 #include "brw_defines.h"
  47 #include "brw_wm.h"
  48
  49 GLuint
  50 translate_tex_target(GLenum target)
  51 {
  52    switch (target) {
  53    case GL_TEXTURE_1D:
  54    case GL_TEXTURE_1D_ARRAY_EXT:
  55       return BRW_SURFACE_1D;
  56
  57    case GL_TEXTURE_RECTANGLE_NV:
  58       return BRW_SURFACE_2D;
  59
  60    case GL_TEXTURE_2D:
  61    case GL_TEXTURE_2D_ARRAY_EXT:
  62    case GL_TEXTURE_EXTERNAL_OES:
  63    case GL_TEXTURE_2D_MULTISAMPLE:
  64    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
  65       return BRW_SURFACE_2D;
  66
  67    case GL_TEXTURE_3D:
  68       return BRW_SURFACE_3D;
  69
  70    case GL_TEXTURE_CUBE_MAP:
  71    case GL_TEXTURE_CUBE_MAP_ARRAY:
  72       return BRW_SURFACE_CUBE;
  73
  74    default:
  75       assert(0);
  76       return 0;
  77    }
  78 }
  79
  80 struct surface_format_info {
  81    bool exists;
  82    int sampling;
  83    int filtering;
  84    int shadow_compare;
  85    int chroma_key;
  86    int render_target;
  87    int alpha_blend;
  88    int input_vb;
  89    int streamed_output_vb;
  90    int color_processing;
  91 };
  92
  93 /* This macro allows us to write the table almost as it appears in the PRM,
  94  * while restructuring it to turn it into the C code we want.
  95  */
  96 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  97    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  98
  99 #define Y 0
 100 #define x 999
 101 /**
 102  * This is the table of support for surface (texture, renderbuffer, and vertex
 103  * buffer, but not depthbuffer) formats across the various hardware generations.
 104  *
 105  * The table is formatted to match the documentation, except that the docs have
 106  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 107  * it in our table, here's the mapping:
 108  *
 109  * Y*: 45
 110  * Y+: 45 (g45/gm45)
 111  * Y~: 50 (gen5)
 112  * Y^: 60 (gen6)
 113  * Y#: 70 (gen7)
 114  *
 115  * The abbreviations in the header below are:
 116  * smpl  - Sampling Engine
 117  * filt  - Sampling Engine Filtering
 118  * shad  - Sampling Engine Shadow Map
 119  * CK    - Sampling Engine Chroma Key
 120  * RT    - Render Target
 121  * AB    - Alpha Blend Render Target
 122  * VB    - Input Vertex Buffer
 123  * SO    - Steamed Output Vertex Buffers (transform feedback)
 124  * color - Color Processing
 125  *
 126  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 127  */
 128 const struct surface_format_info surface_formats[] = {
 129 /* smpl filt shad CK  RT  AB  VB  SO  color */
 130    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 131    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 132    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 133    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 134    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 135    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 136    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 137    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 138    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 139    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 140    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 141    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 145    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 146    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 147    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 148    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 149    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 150    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 151    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 152    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 153    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 154    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 155    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 156    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 157    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 158    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 159    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 160    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 161    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 162    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 163    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 164    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 165    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 166    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 167    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 168    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 169    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 171 /* smpl filt shad CK  RT  AB  VB  SO  color */
 172    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 173    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 175    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 176    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 177    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 178    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 179    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 180    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 181    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 182    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 183    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 184    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 185    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 186    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 187    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 189    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 190    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 191    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 192    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 193    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 194    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 195    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 196    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 197    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 198    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 199    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 200    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 201    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 202    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 203    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 204    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 205    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 206    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 207    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 208    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 209    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 210 /* smpl filt shad CK  RT  AB  VB  SO  color */
 211    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 212    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 213    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 214    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 215    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 216    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 217    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 218    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 219    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 220    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 221    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 222    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 223    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 224    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 225    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 226    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 227    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 228    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 229    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 230    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 231    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 232    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 233    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 234    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 235    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 236    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 237    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 238    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 239    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 240    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 241    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 242    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 243    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 245    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 246 /* smpl filt shad CK  RT  AB  VB  SO  color */
 247    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 248    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 249    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 250    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 251    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 252    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 253    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 255    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 258    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 259    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 260    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 261    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 262    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 263    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 264    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 265    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 266    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 267    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 268    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 269    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 272    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 273    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 274    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 275    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 276    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 277 /* smpl filt shad CK  RT  AB  VB  SO  color */
 278    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 279    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 280    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 281    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 282    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 283    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 284    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 285    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 286    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 287    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 288    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 289    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 290    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 291 };
 292 #undef x
 293 #undef Y
 294
 295 uint32_t
 296 brw_format_for_mesa_format(gl_format mesa_format)
 297 {
 298    /* This table is ordered according to the enum ordering in formats.h.  We do
 299     * expect that enum to be extended without our explicit initialization
 300     * staying in sync, so we initialize to 0 even though
 301     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 302     */
 303    static const uint32_t table[MESA_FORMAT_COUNT] =
 304    {
 305       [MESA_FORMAT_RGBA8888] = 0,
 306       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 307       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 308       [MESA_FORMAT_ARGB8888_REV] = 0,
 309       [MESA_FORMAT_RGBX8888] = 0,
 310       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 311       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 312       [MESA_FORMAT_XRGB8888_REV] = 0,
 313       [MESA_FORMAT_RGB888] = 0,
 314       [MESA_FORMAT_BGR888] = 0,
 315       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 316       [MESA_FORMAT_RGB565_REV] = 0,
 317       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 318       [MESA_FORMAT_ARGB4444_REV] = 0,
 319       [MESA_FORMAT_RGBA5551] = 0,
 320       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 321       [MESA_FORMAT_ARGB1555_REV] = 0,
 322       [MESA_FORMAT_AL44] = 0,
 323       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 324       [MESA_FORMAT_AL88_REV] = 0,
 325       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 326       [MESA_FORMAT_AL1616_REV] = 0,
 327       [MESA_FORMAT_RGB332] = 0,
 328       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 329       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 330       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 331       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 332       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 333       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 334       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 335       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 336       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 337       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 338       [MESA_FORMAT_RG88] = 0,
 339       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 340       [MESA_FORMAT_GR1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 341       [MESA_FORMAT_RG1616] = 0,
 342       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 343       [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
 344       [MESA_FORMAT_Z24_S8] = 0,
 345       [MESA_FORMAT_S8_Z24] = 0,
 346       [MESA_FORMAT_Z16] = 0,
 347       [MESA_FORMAT_X8_Z24] = 0,
 348       [MESA_FORMAT_Z24_X8] = 0,
 349       [MESA_FORMAT_Z32] = 0,
 350       [MESA_FORMAT_S8] = 0,
 351
 352       [MESA_FORMAT_SRGB8] = 0,
 353       [MESA_FORMAT_SRGBA8] = 0,
 354       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 355       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 356       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 357       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 358       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 359       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 360       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 361
 362       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 363       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 364       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 365       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 366       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 367       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 368
 369       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 370       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 371       [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
 372       [MESA_FORMAT_RGB_FLOAT16] = 0,
 373       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 374       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 375       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 376       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 377       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 378       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 379       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 380       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 381       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 382       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 383       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 384       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 385
 386       [MESA_FORMAT_ALPHA_UINT8] = 0,
 387       [MESA_FORMAT_ALPHA_UINT16] = 0,
 388       [MESA_FORMAT_ALPHA_UINT32] = 0,
 389       [MESA_FORMAT_ALPHA_INT8] = 0,
 390       [MESA_FORMAT_ALPHA_INT16] = 0,
 391       [MESA_FORMAT_ALPHA_INT32] = 0,
 392
 393       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 394       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 395       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 396       [MESA_FORMAT_INTENSITY_INT8] = 0,
 397       [MESA_FORMAT_INTENSITY_INT16] = 0,
 398       [MESA_FORMAT_INTENSITY_INT32] = 0,
 399
 400       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 401       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 402       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 403       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 404       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 405       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 406
 407       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 408       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 409       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 410       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 411       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 412       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 413
 414       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 415       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 416       [MESA_FORMAT_RGB_INT8] = 0,
 417       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 418       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 419       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 420       [MESA_FORMAT_RGB_INT16] = 0,
 421       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 422       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 423       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 424       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 425       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 426
 427       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 428       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 429       [MESA_FORMAT_RGB_UINT8] = 0,
 430       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 431       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 432       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 433       [MESA_FORMAT_RGB_UINT16] = 0,
 434       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 435       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 436       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 437       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 438       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 439
 440       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 441       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 442       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 443       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 444       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 445       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 446       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 447       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 448       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 449       [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
 450       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 451
 452       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 453       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 454       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 455       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 456
 457       [MESA_FORMAT_L_LATC1] = 0,
 458       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 459       [MESA_FORMAT_LA_LATC2] = 0,
 460       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 461
 462       [MESA_FORMAT_SIGNED_A8] = 0,
 463       [MESA_FORMAT_SIGNED_L8] = 0,
 464       [MESA_FORMAT_SIGNED_AL88] = 0,
 465       [MESA_FORMAT_SIGNED_I8] = 0,
 466       [MESA_FORMAT_SIGNED_A16] = 0,
 467       [MESA_FORMAT_SIGNED_L16] = 0,
 468       [MESA_FORMAT_SIGNED_AL1616] = 0,
 469       [MESA_FORMAT_SIGNED_I16] = 0,
 470
 471       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 472       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 473
 474       [MESA_FORMAT_Z32_FLOAT] = 0,
 475       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 476    };
 477    assert(mesa_format < MESA_FORMAT_COUNT);
 478    return table[mesa_format];
 479 }
 480
 481 void
 482 brw_init_surface_formats(struct brw_context *brw)
 483 {
 484    struct intel_context *intel = &brw->intel;
 485    struct gl_context *ctx = &intel->ctx;
 486    int gen;
 487    gl_format format;
 488
 489    gen = intel->gen * 10;
 490    if (intel->is_g4x)
 491       gen += 5;
 492
 493    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 494       uint32_t texture, render;
 495       const struct surface_format_info *rinfo, *tinfo;
 496       bool is_integer = _mesa_is_format_integer_color(format);
 497
 498       render = texture = brw_format_for_mesa_format(format);
 499       tinfo = &surface_formats[texture];
 500
 501       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 502        * it.
 503        */
 504       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 505          continue;
 506
 507       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 508          ctx->TextureFormatSupported[format] = true;
 509
 510       /* Re-map some render target formats to make them supported when they
 511        * wouldn't be using their format for texturing.
 512        */
 513       switch (render) {
 514          /* For these formats, we just need to read/write the first
 515           * channel into R, which is to say that we just treat them as
 516           * GL_RED.
 517           */
 518       case BRW_SURFACEFORMAT_I32_FLOAT:
 519       case BRW_SURFACEFORMAT_L32_FLOAT:
 520          render = BRW_SURFACEFORMAT_R32_FLOAT;
 521          break;
 522       case BRW_SURFACEFORMAT_I16_FLOAT:
 523       case BRW_SURFACEFORMAT_L16_FLOAT:
 524          render = BRW_SURFACEFORMAT_R16_FLOAT;
 525          break;
 526       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 527          /* XRGB is handled as ARGB because the chips in this family
 528           * cannot render to XRGB targets.  This means that we have to
 529           * mask writes to alpha (ala glColorMask) and reconfigure the
 530           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 531           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 532           * used.
 533           */
 534          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 535          break;
 536       }
 537
 538       rinfo = &surface_formats[render];
 539
 540       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 541        * integer, so we don't need hardware support for blending on it.  Other
 542        * than that, GL in general requires alpha blending for render targets,
 543        * even though we don't support it for some formats.
 544        */
 545       if (gen >= rinfo->render_target &&
 546           (gen >= rinfo->alpha_blend || is_integer)) {
 547          brw->render_target_format[format] = render;
 548          brw->format_supported_as_render_target[format] = true;
 549       }
 550    }
 551
 552    /* We will check this table for FBO completeness, but the surface format
 553     * table above only covered color rendering.
 554     */
 555    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 556    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 557    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 558    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 559    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 560    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 561
 562    /* We remap depth formats to a supported texturing format in
 563     * translate_tex_format().
 564     */
 565    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 566    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 567    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 568    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 569    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 570
 571    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 572     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 573     */
 574    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 575
 576    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 577     * MESA_FORMAT during glCompressedTexImage2D().
 578     * See intel_mipmap_tree::wraps_etc2.
 579     */
 580    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 581    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 582    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 583    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 584    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 585    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 586    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 587    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 588    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 589    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 590 }
 591
 592 bool
 593 brw_render_target_supported(struct intel_context *intel,
 594                             struct gl_renderbuffer *rb)
 595 {
 596    struct brw_context *brw = brw_context(&intel->ctx);
 597    gl_format format = rb->Format;
 598
 599    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 600     * we would consider them renderable even though we don't have surface
 601     * support for their alpha behavior and don't have the blending unit
 602     * available to fake it like we do for XRGB8888.  Force them to being
 603     * unsupported.
 604     */
 605    if ((rb->_BaseFormat != GL_RGBA &&
 606         rb->_BaseFormat != GL_RG &&
 607         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 608       return false;
 609
 610    /* Under some conditions, MSAA is not supported for formats whose width is
 611     * more than 64 bits.
 612     */
 613    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 614       /* Gen6: MSAA on >64 bit formats is unsupported. */
 615       if (intel->gen <= 6)
 616          return false;
 617
 618       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 619       if (rb->NumSamples >= 8)
 620          return false;
 621    }
 622
 623    return brw->format_supported_as_render_target[format];
 624 }
 625
 626 GLuint
 627 translate_tex_format(struct intel_context *intel,
 628                      gl_format mesa_format,
 629                      GLenum internal_format,
 630                      GLenum depth_mode,
 631                      GLenum srgb_decode)
 632 {
 633    struct gl_context *ctx = &intel->ctx;
 634    if (srgb_decode == GL_SKIP_DECODE_EXT)
 635       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 636
 637    switch( mesa_format ) {
 638
 639    case MESA_FORMAT_Z16:
 640       return BRW_SURFACEFORMAT_I16_UNORM;
 641
 642    case MESA_FORMAT_S8_Z24:
 643    case MESA_FORMAT_X8_Z24:
 644       return BRW_SURFACEFORMAT_I24X8_UNORM;
 645
 646    case MESA_FORMAT_Z32_FLOAT:
 647       return BRW_SURFACEFORMAT_I32_FLOAT;
 648
 649    case MESA_FORMAT_Z32_FLOAT_X24S8:
 650       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 651
 652    case MESA_FORMAT_RGBA_FLOAT32:
 653       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 654        * assertion below.
 655        */
 656       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 657
 658    case MESA_FORMAT_SRGB_DXT1:
 659       if (intel->gen == 4 && !intel->is_g4x) {
 660          /* Work around missing SRGB DXT1 support on original gen4 by just
 661           * skipping SRGB decode.  It's not worth not supporting sRGB in
 662           * general to prevent this.
 663           */
 664          WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
 665          mesa_format = MESA_FORMAT_RGB_DXT1;
 666       }
 667       return brw_format_for_mesa_format(mesa_format);
 668
 669    default:
 670       assert(brw_format_for_mesa_format(mesa_format) != 0);
 671       return brw_format_for_mesa_format(mesa_format);
 672    }
 673 }
 674
 675 uint32_t
 676 brw_get_surface_tiling_bits(uint32_t tiling)
 677 {
 678    switch (tiling) {
 679    case I915_TILING_X:
 680       return BRW_SURFACE_TILED;
 681    case I915_TILING_Y:
 682       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 683    default:
 684       return 0;
 685    }
 686 }
 687
 688
 689 uint32_t
 690 brw_get_surface_num_multisamples(unsigned num_samples)
 691 {
 692    if (num_samples > 1)
 693       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 694    else
 695       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 696 }
 697
 698
 699 /**
 700  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
 701  * swizzling.
 702  */
 703 int
 704 brw_get_texture_swizzle(const struct gl_context *ctx,
 705                         const struct gl_texture_object *t)
 706 {
 707    const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 708
 709    int swizzles[SWIZZLE_NIL + 1] = {
 710       SWIZZLE_X,
 711       SWIZZLE_Y,
 712       SWIZZLE_Z,
 713       SWIZZLE_W,
 714       SWIZZLE_ZERO,
 715       SWIZZLE_ONE,
 716       SWIZZLE_NIL
 717    };
 718
 719    if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
 720        img->_BaseFormat == GL_DEPTH_STENCIL) {
 721       GLenum depth_mode = t->DepthMode;
 722
 723       /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
 724        * with depth component data specified with a sized internal format.
 725        * Otherwise, it's left at the old default, GL_LUMINANCE.
 726        */
 727       if (_mesa_is_gles3(ctx) &&
 728           img->InternalFormat != GL_DEPTH_COMPONENT &&
 729           img->InternalFormat != GL_DEPTH_STENCIL) {
 730          depth_mode = GL_RED;
 731       }
 732
 733       switch (depth_mode) {
 734       case GL_ALPHA:
 735          swizzles[0] = SWIZZLE_ZERO;
 736          swizzles[1] = SWIZZLE_ZERO;
 737          swizzles[2] = SWIZZLE_ZERO;
 738          swizzles[3] = SWIZZLE_X;
 739          break;
 740       case GL_LUMINANCE:
 741          swizzles[0] = SWIZZLE_X;
 742          swizzles[1] = SWIZZLE_X;
 743          swizzles[2] = SWIZZLE_X;
 744          swizzles[3] = SWIZZLE_ONE;
 745          break;
 746       case GL_INTENSITY:
 747          swizzles[0] = SWIZZLE_X;
 748          swizzles[1] = SWIZZLE_X;
 749          swizzles[2] = SWIZZLE_X;
 750          swizzles[3] = SWIZZLE_X;
 751          break;
 752       case GL_RED:
 753          swizzles[0] = SWIZZLE_X;
 754          swizzles[1] = SWIZZLE_ZERO;
 755          swizzles[2] = SWIZZLE_ZERO;
 756          swizzles[3] = SWIZZLE_ONE;
 757          break;
 758       }
 759    }
 760
 761    /* If the texture's format is alpha-only, force R, G, and B to
 762     * 0.0. Similarly, if the texture's format has no alpha channel,
 763     * force the alpha value read to 1.0. This allows for the
 764     * implementation to use an RGBA texture for any of these formats
 765     * without leaking any unexpected values.
 766     */
 767    switch (img->_BaseFormat) {
 768    case GL_ALPHA:
 769       swizzles[0] = SWIZZLE_ZERO;
 770       swizzles[1] = SWIZZLE_ZERO;
 771       swizzles[2] = SWIZZLE_ZERO;
 772       break;
 773    case GL_RED:
 774    case GL_RG:
 775    case GL_RGB:
 776       if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0)
 777          swizzles[3] = SWIZZLE_ONE;
 778       break;
 779    }
 780
 781    return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 782                         swizzles[GET_SWZ(t->_Swizzle, 1)],
 783                         swizzles[GET_SWZ(t->_Swizzle, 2)],
 784                         swizzles[GET_SWZ(t->_Swizzle, 3)]);
 785 }
 786
 787
 788 static void
 789 brw_update_buffer_texture_surface(struct gl_context *ctx,
 790                                   unsigned unit,
 791                                   uint32_t *binding_table,
 792                                   unsigned surf_index)
 793 {
 794    struct brw_context *brw = brw_context(ctx);
 795    struct intel_context *intel = &brw->intel;
 796    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 797    uint32_t *surf;
 798    struct intel_buffer_object *intel_obj =
 799       intel_buffer_object(tObj->BufferObject);
 800    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 801    gl_format format = tObj->_BufferObjectFormat;
 802    uint32_t brw_format = brw_format_for_mesa_format(format);
 803    int texel_size = _mesa_get_format_bytes(format);
 804
 805    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 806       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 807                     _mesa_get_format_name(format));
 808    }
 809
 810    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 811                           6 * 4, 32, &binding_table[surf_index]);
 812
 813    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 814               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 815
 816    if (intel->gen >= 6)
 817       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 818
 819    if (bo) {
 820       surf[1] = bo->offset; /* reloc */
 821
 822       /* Emit relocation to surface contents. */
 823       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 824                               binding_table[surf_index] + 4,
 825                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 826
 827       int w = intel_obj->Base.Size / texel_size;
 828       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 829                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 830       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 831                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 832    } else {
 833       surf[1] = 0;
 834       surf[2] = 0;
 835       surf[3] = 0;
 836    }
 837
 838    surf[4] = 0;
 839    surf[5] = 0;
 840 }
 841
 842 static void
 843 brw_update_texture_surface(struct gl_context *ctx,
 844                            unsigned unit,
 845                            uint32_t *binding_table,
 846                            unsigned surf_index)
 847 {
 848    struct intel_context *intel = intel_context(ctx);
 849    struct brw_context *brw = brw_context(ctx);
 850    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 851    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 852    struct intel_mipmap_tree *mt = intelObj->mt;
 853    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 854    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 855    uint32_t *surf;
 856    int width, height, depth;
 857    uint32_t tile_x, tile_y;
 858
 859    if (tObj->Target == GL_TEXTURE_BUFFER) {
 860       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 861       return;
 862    }
 863
 864    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 865
 866    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 867                           6 * 4, 32, &binding_table[surf_index]);
 868
 869    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 870               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 871               BRW_SURFACE_CUBEFACE_ENABLES |
 872               (translate_tex_format(intel,
 873                                     mt->format,
 874                                     firstImage->InternalFormat,
 875                                     tObj->DepthMode,
 876                                     sampler->sRGBDecode) <<
 877                BRW_SURFACE_FORMAT_SHIFT));
 878
 879    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 880
 881    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 882               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 883               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 884
 885    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 886               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 887               (intelObj->mt->region->pitch - 1) <<
 888               BRW_SURFACE_PITCH_SHIFT);
 889
 890    surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
 891
 892    intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 893                                   &tile_x, &tile_y);
 894    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 895    /* Note that the low bits of these fields are missing, so
 896     * there's the possibility of getting in trouble.
 897     */
 898    assert(tile_x % 4 == 0);
 899    assert(tile_y % 2 == 0);
 900    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 901               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 902               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 903
 904    /* Emit relocation to surface contents */
 905    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 906                            binding_table[surf_index] + 4,
 907                            intelObj->mt->region->bo,
 908                            intelObj->mt->offset,
 909                            I915_GEM_DOMAIN_SAMPLER, 0);
 910 }
 911
 912 /**
 913  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 914  * read from this buffer with Data Port Read instructions/messages.
 915  */
 916 void
 917 brw_create_constant_surface(struct brw_context *brw,
 918                             drm_intel_bo *bo,
 919                             uint32_t offset,
 920                             uint32_t size,
 921                             uint32_t *out_offset)
 922 {
 923    struct intel_context *intel = &brw->intel;
 924    uint32_t stride = 16;
 925    uint32_t elements = ALIGN(size, stride) / stride;
 926    const GLint w = elements - 1;
 927    uint32_t *surf;
 928
 929    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 930                           6 * 4, 32, out_offset);
 931
 932    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 933               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 934               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 935
 936    if (intel->gen >= 6)
 937       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 938
 939    surf[1] = bo->offset + offset; /* reloc */
 940
 941    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 942               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 943
 944    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 945               (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
 946
 947    surf[4] = 0;
 948    surf[5] = 0;
 949
 950    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 951     * bspec ("Data Cache") says that the data cache does not exist as
 952     * a separate cache and is just the sampler cache.
 953     */
 954    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 955                            *out_offset + 4,
 956                            bo, offset,
 957                            I915_GEM_DOMAIN_SAMPLER, 0);
 958 }
 959
 960 /**
 961  * Set up a binding table entry for use by stream output logic (transform
 962  * feedback).
 963  *
 964  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 965  */
 966 void
 967 brw_update_sol_surface(struct brw_context *brw,
 968                        struct gl_buffer_object *buffer_obj,
 969                        uint32_t *out_offset, unsigned num_vector_components,
 970                        unsigned stride_dwords, unsigned offset_dwords)
 971 {
 972    struct intel_context *intel = &brw->intel;
 973    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 974    drm_intel_bo *bo =
 975       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 976    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 977                                     out_offset);
 978    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 979    uint32_t offset_bytes = 4 * offset_dwords;
 980    size_t size_dwords = buffer_obj->Size / 4;
 981    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 982
 983    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 984     * too big to map using a single binding table entry?
 985     */
 986    assert((size_dwords - offset_dwords) / stride_dwords
 987           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 988
 989    if (size_dwords > offset_dwords + num_vector_components) {
 990       /* There is room for at least 1 transform feedback output in the buffer.
 991        * Compute the number of additional transform feedback outputs the
 992        * buffer has room for.
 993        */
 994       buffer_size_minus_1 =
 995          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 996    } else {
 997       /* There isn't even room for a single transform feedback output in the
 998        * buffer.  We can't configure the binding table entry to prevent output
 999        * entirely; we'll have to rely on the geometry shader to detect
1000        * overflow.  But to minimize the damage in case of a bug, set up the
1001        * binding table entry to just allow a single output.
1002        */
1003       buffer_size_minus_1 = 0;
1004    }
1005    width = buffer_size_minus_1 & 0x7f;
1006    height = (buffer_size_minus_1 & 0xfff80) >> 7;
1007    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
1008
1009    switch (num_vector_components) {
1010    case 1:
1011       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1012       break;
1013    case 2:
1014       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1015       break;
1016    case 3:
1017       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1018       break;
1019    case 4:
1020       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
1021       break;
1022    default:
1023       assert(!"Invalid vector size for transform feedback output");
1024       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1025       break;
1026    }
1027
1028    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1029       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1030       surface_format << BRW_SURFACE_FORMAT_SHIFT |
1031       BRW_SURFACE_RC_READ_WRITE;
1032    surf[1] = bo->offset + offset_bytes; /* reloc */
1033    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
1034               height << BRW_SURFACE_HEIGHT_SHIFT);
1035    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1036               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1037    surf[4] = 0;
1038    surf[5] = 0;
1039
1040    /* Emit relocation to surface contents. */
1041    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1042                            *out_offset + 4,
1043                            bo, offset_bytes,
1044                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1045 }
1046
1047 /* Creates a new WM constant buffer reflecting the current fragment program's
1048  * constants, if needed by the fragment program.
1049  *
1050  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
1051  * state atom.
1052  */
1053 static void
1054 brw_upload_wm_pull_constants(struct brw_context *brw)
1055 {
1056    struct gl_context *ctx = &brw->intel.ctx;
1057    struct intel_context *intel = &brw->intel;
1058    /* BRW_NEW_FRAGMENT_PROGRAM */
1059    struct brw_fragment_program *fp =
1060       (struct brw_fragment_program *) brw->fragment_program;
1061    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1062    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1063    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1064    float *constants;
1065    unsigned int i;
1066
1067    _mesa_load_state_parameters(ctx, params);
1068
1069    /* CACHE_NEW_WM_PROG */
1070    if (brw->wm.prog_data->nr_pull_params == 0) {
1071       if (brw->wm.const_bo) {
1072          drm_intel_bo_unreference(brw->wm.const_bo);
1073          brw->wm.const_bo = NULL;
1074          brw->wm.surf_offset[surf_index] = 0;
1075          brw->state.dirty.brw |= BRW_NEW_SURFACES;
1076       }
1077       return;
1078    }
1079
1080    drm_intel_bo_unreference(brw->wm.const_bo);
1081    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1082                                          size, 64);
1083
1084    /* _NEW_PROGRAM_CONSTANTS */
1085    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1086    constants = brw->wm.const_bo->virtual;
1087    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1088       constants[i] = *brw->wm.prog_data->pull_param[i];
1089    }
1090    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1091
1092    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0, size,
1093                                        &brw->wm.surf_offset[surf_index]);
1094
1095    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1096 }
1097
1098 const struct brw_tracked_state brw_wm_pull_constants = {
1099    .dirty = {
1100       .mesa = (_NEW_PROGRAM_CONSTANTS),
1101       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1102       .cache = CACHE_NEW_WM_PROG,
1103    },
1104    .emit = brw_upload_wm_pull_constants,
1105 };
1106
1107 static void
1108 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1109 {
1110    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1111     * Notes):
1112     *
1113     *     A null surface will be used in instances where an actual surface is
1114     *     not bound. When a write message is generated to a null surface, no
1115     *     actual surface is written to. When a read message (including any
1116     *     sampling engine message) is generated to a null surface, the result
1117     *     is all zeros. Note that a null surface type is allowed to be used
1118     *     with all messages, even if it is not specificially indicated as
1119     *     supported. All of the remaining fields in surface state are ignored
1120     *     for null surfaces, with the following exceptions:
1121     *
1122     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1123     *       depth buffer’s corresponding state for all render target surfaces,
1124     *       including null.
1125     *
1126     *     - Surface Format must be R8G8B8A8_UNORM.
1127     */
1128    struct intel_context *intel = &brw->intel;
1129    struct gl_context *ctx = &intel->ctx;
1130    uint32_t *surf;
1131    unsigned surface_type = BRW_SURFACE_NULL;
1132    drm_intel_bo *bo = NULL;
1133    unsigned pitch_minus_1 = 0;
1134    uint32_t multisampling_state = 0;
1135
1136    /* _NEW_BUFFERS */
1137    const struct gl_framebuffer *fb = ctx->DrawBuffer;
1138
1139    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1140                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1141
1142    if (fb->Visual.samples > 1) {
1143       /* On Gen6, null render targets seem to cause GPU hangs when
1144        * multisampling.  So work around this problem by rendering into dummy
1145        * color buffer.
1146        *
1147        * To decrease the amount of memory needed by the workaround buffer, we
1148        * set its pitch to 128 bytes (the width of a Y tile).  This means that
1149        * the amount of memory needed for the workaround buffer is
1150        * (width_in_tiles + height_in_tiles - 1) tiles.
1151        *
1152        * Note that since the workaround buffer will be interpreted by the
1153        * hardware as an interleaved multisampled buffer, we need to compute
1154        * width_in_tiles and height_in_tiles by dividing the width and height
1155        * by 16 rather than the normal Y-tile size of 32.
1156        */
1157       unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1158       unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1159       unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1160       brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1161                          size_needed);
1162       bo = brw->wm.multisampled_null_render_target_bo;
1163       surface_type = BRW_SURFACE_2D;
1164       pitch_minus_1 = 127;
1165       multisampling_state =
1166          brw_get_surface_num_multisamples(fb->Visual.samples);
1167    }
1168
1169    surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1170               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1171    if (intel->gen < 6) {
1172       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1173                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1174                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1175                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1176    }
1177    surf[1] = bo ? bo->offset : 0;
1178    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1179               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1180
1181    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1182     * Notes):
1183     *
1184     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
1185     */
1186    surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1187               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1188    surf[4] = multisampling_state;
1189    surf[5] = 0;
1190
1191    if (bo) {
1192       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1193                               brw->wm.surf_offset[unit] + 4,
1194                               bo, 0,
1195                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1196    }
1197 }
1198
1199 /**
1200  * Sets up a surface state structure to point at the given region.
1201  * While it is only used for the front/back buffer currently, it should be
1202  * usable for further buffers when doing ARB_draw_buffer support.
1203  */
1204 static void
1205 brw_update_renderbuffer_surface(struct brw_context *brw,
1206                                 struct gl_renderbuffer *rb,
1207                                 unsigned int unit)
1208 {
1209    struct intel_context *intel = &brw->intel;
1210    struct gl_context *ctx = &intel->ctx;
1211    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1212    struct intel_mipmap_tree *mt = irb->mt;
1213    struct intel_region *region;
1214    uint32_t *surf;
1215    uint32_t tile_x, tile_y;
1216    uint32_t format = 0;
1217    gl_format rb_format = intel_rb_format(irb);
1218
1219    if (irb->tex_image && !brw->has_surface_tile_offset) {
1220       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1221
1222       if (tile_x != 0 || tile_y != 0) {
1223          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1224           * destination in a miptree unless you actually setup your renderbuffer
1225           * as a miptree and used the fragile lod/array_index/etc. controls to
1226           * select the image.  So, instead, we just make a new single-level
1227           * miptree and render into that.
1228           */
1229          intel_renderbuffer_move_to_temp(intel, irb, false);
1230          mt = irb->mt;
1231       }
1232    }
1233
1234    region = irb->mt->region;
1235
1236    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1237                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1238
1239    switch (rb_format) {
1240    case MESA_FORMAT_SARGB8:
1241       /* _NEW_BUFFERS
1242        *
1243        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1244        * blend/update as sRGB.
1245        */
1246       if (ctx->Color.sRGBEnabled)
1247          format = brw_format_for_mesa_format(rb_format);
1248       else
1249          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1250       break;
1251    default:
1252       format = brw->render_target_format[rb_format];
1253       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1254          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1255                        __FUNCTION__, _mesa_get_format_name(rb_format));
1256       }
1257       break;
1258    }
1259
1260    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1261               format << BRW_SURFACE_FORMAT_SHIFT);
1262
1263    /* reloc */
1264    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1265               region->bo->offset);
1266
1267    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1268               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1269
1270    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1271               (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1272
1273    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1274
1275    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1276    /* Note that the low bits of these fields are missing, so
1277     * there's the possibility of getting in trouble.
1278     */
1279    assert(tile_x % 4 == 0);
1280    assert(tile_y % 2 == 0);
1281    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1282               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1283               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1284
1285    if (intel->gen < 6) {
1286       /* _NEW_COLOR */
1287       if (!ctx->Color.ColorLogicOpEnabled &&
1288           (ctx->Color.BlendEnabled & (1 << unit)))
1289          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1290
1291       if (!ctx->Color.ColorMask[unit][0])
1292          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1293       if (!ctx->Color.ColorMask[unit][1])
1294          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1295       if (!ctx->Color.ColorMask[unit][2])
1296          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1297
1298       /* As mentioned above, disable writes to the alpha component when the
1299        * renderbuffer is XRGB.
1300        */
1301       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1302           !ctx->Color.ColorMask[unit][3]) {
1303          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1304       }
1305    }
1306
1307    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1308                            brw->wm.surf_offset[unit] + 4,
1309                            region->bo,
1310                            surf[1] - region->bo->offset,
1311                            I915_GEM_DOMAIN_RENDER,
1312                            I915_GEM_DOMAIN_RENDER);
1313 }
1314
1315 /**
1316  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1317  */
1318 static void
1319 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1320 {
1321    struct intel_context *intel = &brw->intel;
1322    struct gl_context *ctx = &brw->intel.ctx;
1323    GLuint i;
1324
1325    /* _NEW_BUFFERS | _NEW_COLOR */
1326    /* Update surfaces for drawing buffers */
1327    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1328       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1329          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1330             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1331          } else {
1332             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1333          }
1334       }
1335    } else {
1336       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1337    }
1338    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1339 }
1340
1341 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1342    .dirty = {
1343       .mesa = (_NEW_COLOR |
1344                _NEW_BUFFERS),
1345       .brw = BRW_NEW_BATCH,
1346       .cache = 0
1347    },
1348    .emit = brw_update_renderbuffer_surfaces,
1349 };
1350
1351 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1352    .dirty = {
1353       .mesa = _NEW_BUFFERS,
1354       .brw = BRW_NEW_BATCH,
1355       .cache = 0
1356    },
1357    .emit = brw_update_renderbuffer_surfaces,
1358 };
1359
1360 /**
1361  * Construct SURFACE_STATE objects for enabled textures.
1362  */
1363 static void
1364 brw_update_texture_surfaces(struct brw_context *brw)
1365 {
1366    struct intel_context *intel = &brw->intel;
1367    struct gl_context *ctx = &intel->ctx;
1368
1369    /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1370     * Unfortunately, we're stuck using the gl_program structs until the
1371     * ARB_fragment_program front-end gets converted to GLSL IR.  These
1372     * have the downside that SamplerUnits is split and only contains the
1373     * mappings for samplers active in that stage.
1374     */
1375    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1376    struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1377
1378    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1379
1380    for (unsigned s = 0; s < num_samplers; s++) {
1381       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1382       brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1383
1384       if (vs->SamplersUsed & (1 << s)) {
1385          const unsigned unit = vs->SamplerUnits[s];
1386
1387          /* _NEW_TEXTURE */
1388          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1389             intel->vtbl.update_texture_surface(ctx, unit,
1390                                                brw->vs.surf_offset,
1391                                                SURF_INDEX_VS_TEXTURE(s));
1392          }
1393       }
1394
1395       if (fs->SamplersUsed & (1 << s)) {
1396          const unsigned unit = fs->SamplerUnits[s];
1397
1398          /* _NEW_TEXTURE */
1399          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1400             intel->vtbl.update_texture_surface(ctx, unit,
1401                                                brw->wm.surf_offset,
1402                                                SURF_INDEX_TEXTURE(s));
1403          }
1404       }
1405    }
1406
1407    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1408 }
1409
1410 const struct brw_tracked_state brw_texture_surfaces = {
1411    .dirty = {
1412       .mesa = _NEW_TEXTURE,
1413       .brw = BRW_NEW_BATCH |
1414              BRW_NEW_VERTEX_PROGRAM |
1415              BRW_NEW_FRAGMENT_PROGRAM,
1416       .cache = 0
1417    },
1418    .emit = brw_update_texture_surfaces,
1419 };
1420
1421 void
1422 brw_upload_ubo_surfaces(struct brw_context *brw,
1423                         struct gl_shader *shader,
1424                         uint32_t *surf_offsets)
1425 {
1426    struct gl_context *ctx = &brw->intel.ctx;
1427    struct intel_context *intel = &brw->intel;
1428
1429    if (!shader)
1430       return;
1431
1432    for (int i = 0; i < shader->NumUniformBlocks; i++) {
1433       struct gl_uniform_buffer_binding *binding;
1434       struct intel_buffer_object *intel_bo;
1435
1436       binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1437       intel_bo = intel_buffer_object(binding->BufferObject);
1438       drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1439
1440       /* Because behavior for referencing outside of the binding's size in the
1441        * glBindBufferRange case is undefined, we can just bind the whole buffer
1442        * glBindBufferBase wants and be a correct implementation.
1443        */
1444       intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1445                                           bo->size - binding->Offset,
1446                                           &surf_offsets[i]);
1447    }
1448
1449    if (shader->NumUniformBlocks)
1450       brw->state.dirty.brw |= BRW_NEW_SURFACES;
1451 }
1452
1453 static void
1454 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1455 {
1456    struct gl_context *ctx = &brw->intel.ctx;
1457    /* _NEW_PROGRAM */
1458    struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1459
1460    if (!prog)
1461       return;
1462
1463    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1464                            &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1465 }
1466
1467 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1468    .dirty = {
1469       .mesa = (_NEW_PROGRAM |
1470                _NEW_BUFFER_OBJECT),
1471       .brw = BRW_NEW_BATCH,
1472       .cache = 0,
1473    },
1474    .emit = brw_upload_wm_ubo_surfaces,
1475 };
1476
1477 /**
1478  * Constructs the binding table for the WM surface state, which maps unit
1479  * numbers to surface state objects.
1480  */
1481 static void
1482 brw_upload_wm_binding_table(struct brw_context *brw)
1483 {
1484    uint32_t *bind;
1485    int i;
1486
1487    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1488       gen7_create_shader_time_surface(brw, &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1489    }
1490
1491    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1492     * space for the binding table.
1493     */
1494    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1495                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1496                           32, &brw->wm.bind_bo_offset);
1497
1498    /* BRW_NEW_SURFACES */
1499    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1500       bind[i] = brw->wm.surf_offset[i];
1501    }
1502
1503    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1504 }
1505
1506 const struct brw_tracked_state brw_wm_binding_table = {
1507    .dirty = {
1508       .mesa = 0,
1509       .brw = (BRW_NEW_BATCH |
1510               BRW_NEW_SURFACES),
1511       .cache = 0
1512    },
1513    .emit = brw_upload_wm_binding_table,
1514 };
1515
1516 void
1517 gen4_init_vtable_surface_functions(struct brw_context *brw)
1518 {
1519    struct intel_context *intel = &brw->intel;
1520
1521    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1522    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1523    intel->vtbl.update_null_renderbuffer_surface =
1524       brw_update_null_renderbuffer_surface;
1525    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1526 }