src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68    case GL_TEXTURE_CUBE_MAP_ARRAY:
  69       return BRW_SURFACE_CUBE;
  70
  71    default:
  72       assert(0);
  73       return 0;
  74    }
  75 }
  76
  77 struct surface_format_info {
  78    bool exists;
  79    int sampling;
  80    int filtering;
  81    int shadow_compare;
  82    int chroma_key;
  83    int render_target;
  84    int alpha_blend;
  85    int input_vb;
  86    int streamed_output_vb;
  87    int color_processing;
  88 };
  89
  90 /* This macro allows us to write the table almost as it appears in the PRM,
  91  * while restructuring it to turn it into the C code we want.
  92  */
  93 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  94    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  95
  96 #define Y 0
  97 #define x 999
  98 /**
  99  * This is the table of support for surface (texture, renderbuffer, and vertex
 100  * buffer, but not depthbuffer) formats across the various hardware generations.
 101  *
 102  * The table is formatted to match the documentation, except that the docs have
 103  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 104  * it in our table, here's the mapping:
 105  *
 106  * Y*: 45
 107  * Y+: 45 (g45/gm45)
 108  * Y~: 50 (gen5)
 109  * Y^: 60 (gen6)
 110  * Y#: 70 (gen7)
 111  *
 112  * The abbreviations in the header below are:
 113  * smpl  - Sampling Engine
 114  * filt  - Sampling Engine Filtering
 115  * shad  - Sampling Engine Shadow Map
 116  * CK    - Sampling Engine Chroma Key
 117  * RT    - Render Target
 118  * AB    - Alpha Blend Render Target
 119  * VB    - Input Vertex Buffer
 120  * SO    - Steamed Output Vertex Buffers (transform feedback)
 121  * color - Color Processing
 122  *
 123  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 124  */
 125 const struct surface_format_info surface_formats[] = {
 126 /* smpl filt shad CK  RT  AB  VB  SO  color */
 127    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 128    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 129    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 131    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 132    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 133    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 134    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 135    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 136    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 137    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 138    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 139    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 140    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 141    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 143    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 144    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 145    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 146    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 147    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 148    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 149    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 150    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 151    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 152    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 153    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 154    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 155    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 156    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 157    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 159    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 160    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 161    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 162    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 163    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 164    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 165    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 166    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 167    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 168 /* smpl filt shad CK  RT  AB  VB  SO  color */
 169    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 170    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 171    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 172    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 174    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 175    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 176    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 177    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 178    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 179    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 180    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 181    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 182    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 183    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 184    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 185    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 186    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 187    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 188    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 189    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 190    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 192    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 193    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 194    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 195    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 196    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 197    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 198    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 199    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 200    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 201    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 202    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 203    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 204    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 205    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 206    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 207 /* smpl filt shad CK  RT  AB  VB  SO  color */
 208    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 209    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 210    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 211    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 212    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 213    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 214    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 215    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 216    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 217    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 218    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 219    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 220    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 221    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 222    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 223    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 224    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 225    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 226    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 227    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 228    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 229    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 230    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 231    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 232    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 233    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 234    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 235    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 236    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 237    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 238    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 239    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 240    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 241    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 242    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 243 /* smpl filt shad CK  RT  AB  VB  SO  color */
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 245    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 246    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 247    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 248    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 249    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 250    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 251    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 255    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 256    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 257    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 258    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 259    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 260    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 261    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 262    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 263    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 264    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 265    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 266    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 267    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 268    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 269    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 270    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 271    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 272    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 273    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 274 /* smpl filt shad CK  RT  AB  VB  SO  color */
 275    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 276    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 277    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 278    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 279    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 280    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 281    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 282    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 283    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 284    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 285    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 286    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 287    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 288 };
 289 #undef x
 290 #undef Y
 291
 292 uint32_t
 293 brw_format_for_mesa_format(gl_format mesa_format)
 294 {
 295    /* This table is ordered according to the enum ordering in formats.h.  We do
 296     * expect that enum to be extended without our explicit initialization
 297     * staying in sync, so we initialize to 0 even though
 298     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 299     */
 300    static const uint32_t table[MESA_FORMAT_COUNT] =
 301    {
 302       [MESA_FORMAT_RGBA8888] = 0,
 303       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 304       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 305       [MESA_FORMAT_ARGB8888_REV] = 0,
 306       [MESA_FORMAT_RGBX8888] = 0,
 307       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 308       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 309       [MESA_FORMAT_XRGB8888_REV] = 0,
 310       [MESA_FORMAT_RGB888] = 0,
 311       [MESA_FORMAT_BGR888] = 0,
 312       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 313       [MESA_FORMAT_RGB565_REV] = 0,
 314       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 315       [MESA_FORMAT_ARGB4444_REV] = 0,
 316       [MESA_FORMAT_RGBA5551] = 0,
 317       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 318       [MESA_FORMAT_ARGB1555_REV] = 0,
 319       [MESA_FORMAT_AL44] = 0,
 320       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 321       [MESA_FORMAT_AL88_REV] = 0,
 322       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 323       [MESA_FORMAT_AL1616_REV] = 0,
 324       [MESA_FORMAT_RGB332] = 0,
 325       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 326       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 327       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 328       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 329       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 330       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 331       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 332       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 333       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 334       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 335       [MESA_FORMAT_RG88] = 0,
 336       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 337       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 338       [MESA_FORMAT_RG1616_REV] = 0,
 339       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 340       [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
 341       [MESA_FORMAT_Z24_S8] = 0,
 342       [MESA_FORMAT_S8_Z24] = 0,
 343       [MESA_FORMAT_Z16] = 0,
 344       [MESA_FORMAT_X8_Z24] = 0,
 345       [MESA_FORMAT_Z24_X8] = 0,
 346       [MESA_FORMAT_Z32] = 0,
 347       [MESA_FORMAT_S8] = 0,
 348
 349       [MESA_FORMAT_SRGB8] = 0,
 350       [MESA_FORMAT_SRGBA8] = 0,
 351       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 352       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 353       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 354       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 355       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 356       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 357       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 358
 359       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 360       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 361       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 362       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 363       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 364       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 365
 366       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 367       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 368       [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
 369       [MESA_FORMAT_RGB_FLOAT16] = 0,
 370       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 371       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 372       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 373       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 374       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 375       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 376       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 377       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 378       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 379       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 380       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 381       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 382
 383       [MESA_FORMAT_ALPHA_UINT8] = 0,
 384       [MESA_FORMAT_ALPHA_UINT16] = 0,
 385       [MESA_FORMAT_ALPHA_UINT32] = 0,
 386       [MESA_FORMAT_ALPHA_INT8] = 0,
 387       [MESA_FORMAT_ALPHA_INT16] = 0,
 388       [MESA_FORMAT_ALPHA_INT32] = 0,
 389
 390       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 391       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 392       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 393       [MESA_FORMAT_INTENSITY_INT8] = 0,
 394       [MESA_FORMAT_INTENSITY_INT16] = 0,
 395       [MESA_FORMAT_INTENSITY_INT32] = 0,
 396
 397       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 398       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 399       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 400       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 401       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 402       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 403
 404       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 405       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 406       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 407       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 408       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 409       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 410
 411       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 412       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 413       [MESA_FORMAT_RGB_INT8] = 0,
 414       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 415       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 416       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 417       [MESA_FORMAT_RGB_INT16] = 0,
 418       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 419       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 420       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 421       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 422       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 423
 424       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 425       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 426       [MESA_FORMAT_RGB_UINT8] = 0,
 427       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 428       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 429       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 430       [MESA_FORMAT_RGB_UINT16] = 0,
 431       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 432       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 433       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 434       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 435       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 436
 437       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 438       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 439       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 440       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 441       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 442       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 443       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 444       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 445       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 446       [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
 447       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 448
 449       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 450       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 451       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 452       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 453
 454       [MESA_FORMAT_L_LATC1] = 0,
 455       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 456       [MESA_FORMAT_LA_LATC2] = 0,
 457       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 458
 459       [MESA_FORMAT_SIGNED_A8] = 0,
 460       [MESA_FORMAT_SIGNED_L8] = 0,
 461       [MESA_FORMAT_SIGNED_AL88] = 0,
 462       [MESA_FORMAT_SIGNED_I8] = 0,
 463       [MESA_FORMAT_SIGNED_A16] = 0,
 464       [MESA_FORMAT_SIGNED_L16] = 0,
 465       [MESA_FORMAT_SIGNED_AL1616] = 0,
 466       [MESA_FORMAT_SIGNED_I16] = 0,
 467
 468       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 469       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 470
 471       [MESA_FORMAT_Z32_FLOAT] = 0,
 472       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 473    };
 474    assert(mesa_format < MESA_FORMAT_COUNT);
 475    return table[mesa_format];
 476 }
 477
 478 void
 479 brw_init_surface_formats(struct brw_context *brw)
 480 {
 481    struct intel_context *intel = &brw->intel;
 482    struct gl_context *ctx = &intel->ctx;
 483    int gen;
 484    gl_format format;
 485
 486    gen = intel->gen * 10;
 487    if (intel->is_g4x)
 488       gen += 5;
 489
 490    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 491       uint32_t texture, render;
 492       const struct surface_format_info *rinfo, *tinfo;
 493       bool is_integer = _mesa_is_format_integer_color(format);
 494
 495       render = texture = brw_format_for_mesa_format(format);
 496       tinfo = &surface_formats[texture];
 497
 498       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 499        * it.
 500        */
 501       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 502          continue;
 503
 504       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 505          ctx->TextureFormatSupported[format] = true;
 506
 507       /* Re-map some render target formats to make them supported when they
 508        * wouldn't be using their format for texturing.
 509        */
 510       switch (render) {
 511          /* For these formats, we just need to read/write the first
 512           * channel into R, which is to say that we just treat them as
 513           * GL_RED.
 514           */
 515       case BRW_SURFACEFORMAT_I32_FLOAT:
 516       case BRW_SURFACEFORMAT_L32_FLOAT:
 517          render = BRW_SURFACEFORMAT_R32_FLOAT;
 518          break;
 519       case BRW_SURFACEFORMAT_I16_FLOAT:
 520       case BRW_SURFACEFORMAT_L16_FLOAT:
 521          render = BRW_SURFACEFORMAT_R16_FLOAT;
 522          break;
 523       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 524          /* XRGB is handled as ARGB because the chips in this family
 525           * cannot render to XRGB targets.  This means that we have to
 526           * mask writes to alpha (ala glColorMask) and reconfigure the
 527           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 528           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 529           * used.
 530           */
 531          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 532          break;
 533       }
 534
 535       rinfo = &surface_formats[render];
 536
 537       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 538        * integer, so we don't need hardware support for blending on it.  Other
 539        * than that, GL in general requires alpha blending for render targets,
 540        * even though we don't support it for some formats.
 541        */
 542       if (gen >= rinfo->render_target &&
 543           (gen >= rinfo->alpha_blend || is_integer)) {
 544          brw->render_target_format[format] = render;
 545          brw->format_supported_as_render_target[format] = true;
 546       }
 547    }
 548
 549    /* We will check this table for FBO completeness, but the surface format
 550     * table above only covered color rendering.
 551     */
 552    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 553    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 554    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 555    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 556    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 557    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 558
 559    /* We remap depth formats to a supported texturing format in
 560     * translate_tex_format().
 561     */
 562    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 563    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 564    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 565    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 566    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 567
 568    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 569     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 570     */
 571    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 572
 573    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 574     * MESA_FORMAT during glCompressedTexImage2D().
 575     * See intel_mipmap_tree::wraps_etc2.
 576     */
 577    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 578    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 579    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 580    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 581    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 582    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 583    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 584    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 585    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 586    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 587 }
 588
 589 bool
 590 brw_render_target_supported(struct intel_context *intel,
 591                             struct gl_renderbuffer *rb)
 592 {
 593    struct brw_context *brw = brw_context(&intel->ctx);
 594    gl_format format = rb->Format;
 595
 596    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 597     * we would consider them renderable even though we don't have surface
 598     * support for their alpha behavior and don't have the blending unit
 599     * available to fake it like we do for XRGB8888.  Force them to being
 600     * unsupported.
 601     */
 602    if ((rb->_BaseFormat != GL_RGBA &&
 603         rb->_BaseFormat != GL_RG &&
 604         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 605       return false;
 606
 607    /* Under some conditions, MSAA is not supported for formats whose width is
 608     * more than 64 bits.
 609     */
 610    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 611       /* Gen6: MSAA on >64 bit formats is unsupported. */
 612       if (intel->gen <= 6)
 613          return false;
 614
 615       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 616       if (rb->NumSamples >= 8)
 617          return false;
 618    }
 619
 620    return brw->format_supported_as_render_target[format];
 621 }
 622
 623 GLuint
 624 translate_tex_format(gl_format mesa_format,
 625                      GLenum internal_format,
 626                      GLenum depth_mode,
 627                      GLenum srgb_decode)
 628 {
 629    if (srgb_decode == GL_SKIP_DECODE_EXT)
 630       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 631
 632    switch( mesa_format ) {
 633
 634    case MESA_FORMAT_Z16:
 635       return BRW_SURFACEFORMAT_I16_UNORM;
 636
 637    case MESA_FORMAT_S8_Z24:
 638    case MESA_FORMAT_X8_Z24:
 639       return BRW_SURFACEFORMAT_I24X8_UNORM;
 640
 641    case MESA_FORMAT_Z32_FLOAT:
 642       return BRW_SURFACEFORMAT_I32_FLOAT;
 643
 644    case MESA_FORMAT_Z32_FLOAT_X24S8:
 645       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 646
 647    case MESA_FORMAT_RGBA_FLOAT32:
 648       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 649        * assertion below.
 650        */
 651       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 652
 653    default:
 654       assert(brw_format_for_mesa_format(mesa_format) != 0);
 655       return brw_format_for_mesa_format(mesa_format);
 656    }
 657 }
 658
 659 uint32_t
 660 brw_get_surface_tiling_bits(uint32_t tiling)
 661 {
 662    switch (tiling) {
 663    case I915_TILING_X:
 664       return BRW_SURFACE_TILED;
 665    case I915_TILING_Y:
 666       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 667    default:
 668       return 0;
 669    }
 670 }
 671
 672
 673 uint32_t
 674 brw_get_surface_num_multisamples(unsigned num_samples)
 675 {
 676    if (num_samples > 1)
 677       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 678    else
 679       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 680 }
 681
 682
 683 /**
 684  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
 685  * swizzling.
 686  */
 687 int
 688 brw_get_texture_swizzle(const struct gl_texture_object *t)
 689 {
 690    const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 691
 692    int swizzles[SWIZZLE_NIL + 1] = {
 693       SWIZZLE_X,
 694       SWIZZLE_Y,
 695       SWIZZLE_Z,
 696       SWIZZLE_W,
 697       SWIZZLE_ZERO,
 698       SWIZZLE_ONE,
 699       SWIZZLE_NIL
 700    };
 701
 702    if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
 703        img->_BaseFormat == GL_DEPTH_STENCIL) {
 704       switch (t->DepthMode) {
 705       case GL_ALPHA:
 706          swizzles[0] = SWIZZLE_ZERO;
 707          swizzles[1] = SWIZZLE_ZERO;
 708          swizzles[2] = SWIZZLE_ZERO;
 709          swizzles[3] = SWIZZLE_X;
 710          break;
 711       case GL_LUMINANCE:
 712          swizzles[0] = SWIZZLE_X;
 713          swizzles[1] = SWIZZLE_X;
 714          swizzles[2] = SWIZZLE_X;
 715          swizzles[3] = SWIZZLE_ONE;
 716          break;
 717       case GL_INTENSITY:
 718          swizzles[0] = SWIZZLE_X;
 719          swizzles[1] = SWIZZLE_X;
 720          swizzles[2] = SWIZZLE_X;
 721          swizzles[3] = SWIZZLE_X;
 722          break;
 723       case GL_RED:
 724          swizzles[0] = SWIZZLE_X;
 725          swizzles[1] = SWIZZLE_ZERO;
 726          swizzles[2] = SWIZZLE_ZERO;
 727          swizzles[3] = SWIZZLE_ONE;
 728          break;
 729       }
 730    }
 731
 732    /* For a format with no alpha channel, force the alpha result to
 733     * 1.0. (This allows for an RGBA texture to be used for an RGB
 734     * format, for example).
 735     */
 736    switch (img->_BaseFormat) {
 737    case GL_RED:
 738    case GL_RG:
 739    case GL_RGB:
 740       swizzles[3] = SWIZZLE_ONE;
 741       break;
 742    }
 743
 744    return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 745                         swizzles[GET_SWZ(t->_Swizzle, 1)],
 746                         swizzles[GET_SWZ(t->_Swizzle, 2)],
 747                         swizzles[GET_SWZ(t->_Swizzle, 3)]);
 748 }
 749
 750
 751 static void
 752 brw_update_buffer_texture_surface(struct gl_context *ctx,
 753                                   unsigned unit,
 754                                   uint32_t *binding_table,
 755                                   unsigned surf_index)
 756 {
 757    struct brw_context *brw = brw_context(ctx);
 758    struct intel_context *intel = &brw->intel;
 759    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 760    uint32_t *surf;
 761    struct intel_buffer_object *intel_obj =
 762       intel_buffer_object(tObj->BufferObject);
 763    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 764    gl_format format = tObj->_BufferObjectFormat;
 765    uint32_t brw_format = brw_format_for_mesa_format(format);
 766    int texel_size = _mesa_get_format_bytes(format);
 767
 768    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 769       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 770                     _mesa_get_format_name(format));
 771    }
 772
 773    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 774                           6 * 4, 32, &binding_table[surf_index]);
 775
 776    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 777               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 778
 779    if (intel->gen >= 6)
 780       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 781
 782    if (bo) {
 783       surf[1] = bo->offset; /* reloc */
 784
 785       /* Emit relocation to surface contents. */
 786       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 787                               binding_table[surf_index] + 4,
 788                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 789
 790       int w = intel_obj->Base.Size / texel_size;
 791       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 792                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 793       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 794                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 795    } else {
 796       surf[1] = 0;
 797       surf[2] = 0;
 798       surf[3] = 0;
 799    }
 800
 801    surf[4] = 0;
 802    surf[5] = 0;
 803 }
 804
 805 static void
 806 brw_update_texture_surface(struct gl_context *ctx,
 807                            unsigned unit,
 808                            uint32_t *binding_table,
 809                            unsigned surf_index)
 810 {
 811    struct brw_context *brw = brw_context(ctx);
 812    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 813    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 814    struct intel_mipmap_tree *mt = intelObj->mt;
 815    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 816    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 817    uint32_t *surf;
 818    int width, height, depth;
 819
 820    if (tObj->Target == GL_TEXTURE_BUFFER) {
 821       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 822       return;
 823    }
 824
 825    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 826
 827    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 828                           6 * 4, 32, &binding_table[surf_index]);
 829
 830    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 831               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 832               BRW_SURFACE_CUBEFACE_ENABLES |
 833               (translate_tex_format(mt->format,
 834                                     firstImage->InternalFormat,
 835                                     tObj->DepthMode,
 836                                     sampler->sRGBDecode) <<
 837                BRW_SURFACE_FORMAT_SHIFT));
 838
 839    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 840
 841    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 842               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 843               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 844
 845    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 846               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 847               (intelObj->mt->region->pitch - 1) <<
 848               BRW_SURFACE_PITCH_SHIFT);
 849
 850    surf[4] = 0;
 851
 852    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 853
 854    /* Emit relocation to surface contents */
 855    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 856                            binding_table[surf_index] + 4,
 857                            intelObj->mt->region->bo,
 858                            intelObj->mt->offset,
 859                            I915_GEM_DOMAIN_SAMPLER, 0);
 860 }
 861
 862 /**
 863  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 864  * read from this buffer with Data Port Read instructions/messages.
 865  */
 866 void
 867 brw_create_constant_surface(struct brw_context *brw,
 868                             drm_intel_bo *bo,
 869                             uint32_t offset,
 870                             int width,
 871                             uint32_t *out_offset)
 872 {
 873    struct intel_context *intel = &brw->intel;
 874    const GLint w = width - 1;
 875    uint32_t *surf;
 876
 877    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 878                           6 * 4, 32, out_offset);
 879
 880    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 881               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 882               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 883
 884    if (intel->gen >= 6)
 885       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 886
 887    surf[1] = bo->offset + offset; /* reloc */
 888
 889    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 890               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 891
 892    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 893               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 894
 895    surf[4] = 0;
 896    surf[5] = 0;
 897
 898    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 899     * bspec ("Data Cache") says that the data cache does not exist as
 900     * a separate cache and is just the sampler cache.
 901     */
 902    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 903                            *out_offset + 4,
 904                            bo, offset,
 905                            I915_GEM_DOMAIN_SAMPLER, 0);
 906 }
 907
 908 /**
 909  * Set up a binding table entry for use by stream output logic (transform
 910  * feedback).
 911  *
 912  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 913  */
 914 void
 915 brw_update_sol_surface(struct brw_context *brw,
 916                        struct gl_buffer_object *buffer_obj,
 917                        uint32_t *out_offset, unsigned num_vector_components,
 918                        unsigned stride_dwords, unsigned offset_dwords)
 919 {
 920    struct intel_context *intel = &brw->intel;
 921    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 922    drm_intel_bo *bo =
 923       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 924    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 925                                     out_offset);
 926    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 927    uint32_t offset_bytes = 4 * offset_dwords;
 928    size_t size_dwords = buffer_obj->Size / 4;
 929    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 930
 931    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 932     * too big to map using a single binding table entry?
 933     */
 934    assert((size_dwords - offset_dwords) / stride_dwords
 935           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 936
 937    if (size_dwords > offset_dwords + num_vector_components) {
 938       /* There is room for at least 1 transform feedback output in the buffer.
 939        * Compute the number of additional transform feedback outputs the
 940        * buffer has room for.
 941        */
 942       buffer_size_minus_1 =
 943          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 944    } else {
 945       /* There isn't even room for a single transform feedback output in the
 946        * buffer.  We can't configure the binding table entry to prevent output
 947        * entirely; we'll have to rely on the geometry shader to detect
 948        * overflow.  But to minimize the damage in case of a bug, set up the
 949        * binding table entry to just allow a single output.
 950        */
 951       buffer_size_minus_1 = 0;
 952    }
 953    width = buffer_size_minus_1 & 0x7f;
 954    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 955    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 956
 957    switch (num_vector_components) {
 958    case 1:
 959       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 960       break;
 961    case 2:
 962       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 963       break;
 964    case 3:
 965       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 966       break;
 967    case 4:
 968       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 969       break;
 970    default:
 971       assert(!"Invalid vector size for transform feedback output");
 972       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 973       break;
 974    }
 975
 976    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 977       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 978       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 979       BRW_SURFACE_RC_READ_WRITE;
 980    surf[1] = bo->offset + offset_bytes; /* reloc */
 981    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 982               height << BRW_SURFACE_HEIGHT_SHIFT);
 983    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 984               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 985    surf[4] = 0;
 986    surf[5] = 0;
 987
 988    /* Emit relocation to surface contents. */
 989    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 990                            *out_offset + 4,
 991                            bo, offset_bytes,
 992                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 993 }
 994
 995 /* Creates a new WM constant buffer reflecting the current fragment program's
 996  * constants, if needed by the fragment program.
 997  *
 998  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 999  * state atom.
1000  */
1001 static void
1002 brw_upload_wm_pull_constants(struct brw_context *brw)
1003 {
1004    struct gl_context *ctx = &brw->intel.ctx;
1005    struct intel_context *intel = &brw->intel;
1006    /* BRW_NEW_FRAGMENT_PROGRAM */
1007    struct brw_fragment_program *fp =
1008       (struct brw_fragment_program *) brw->fragment_program;
1009    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1010    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1011    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1012    float *constants;
1013    unsigned int i;
1014
1015    _mesa_load_state_parameters(ctx, params);
1016
1017    /* CACHE_NEW_WM_PROG */
1018    if (brw->wm.prog_data->nr_pull_params == 0) {
1019       if (brw->wm.const_bo) {
1020          drm_intel_bo_unreference(brw->wm.const_bo);
1021          brw->wm.const_bo = NULL;
1022          brw->wm.surf_offset[surf_index] = 0;
1023          brw->state.dirty.brw |= BRW_NEW_SURFACES;
1024       }
1025       return;
1026    }
1027
1028    drm_intel_bo_unreference(brw->wm.const_bo);
1029    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1030                                          size, 64);
1031
1032    /* _NEW_PROGRAM_CONSTANTS */
1033    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1034    constants = brw->wm.const_bo->virtual;
1035    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1036       constants[i] = *brw->wm.prog_data->pull_param[i];
1037    }
1038    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1039
1040    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1041                                        ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4,
1042                                        &brw->wm.surf_offset[surf_index]);
1043
1044    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1045 }
1046
1047 const struct brw_tracked_state brw_wm_pull_constants = {
1048    .dirty = {
1049       .mesa = (_NEW_PROGRAM_CONSTANTS),
1050       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1051       .cache = CACHE_NEW_WM_PROG,
1052    },
1053    .emit = brw_upload_wm_pull_constants,
1054 };
1055
1056 static void
1057 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1058 {
1059    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1060     * Notes):
1061     *
1062     *     A null surface will be used in instances where an actual surface is
1063     *     not bound. When a write message is generated to a null surface, no
1064     *     actual surface is written to. When a read message (including any
1065     *     sampling engine message) is generated to a null surface, the result
1066     *     is all zeros. Note that a null surface type is allowed to be used
1067     *     with all messages, even if it is not specificially indicated as
1068     *     supported. All of the remaining fields in surface state are ignored
1069     *     for null surfaces, with the following exceptions:
1070     *
1071     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1072     *       depth buffer’s corresponding state for all render target surfaces,
1073     *       including null.
1074     *
1075     *     - Surface Format must be R8G8B8A8_UNORM.
1076     */
1077    struct intel_context *intel = &brw->intel;
1078    struct gl_context *ctx = &intel->ctx;
1079    uint32_t *surf;
1080    unsigned surface_type = BRW_SURFACE_NULL;
1081    drm_intel_bo *bo = NULL;
1082    unsigned pitch_minus_1 = 0;
1083    uint32_t multisampling_state = 0;
1084
1085    /* _NEW_BUFFERS */
1086    const struct gl_framebuffer *fb = ctx->DrawBuffer;
1087
1088    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1089                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1090
1091    if (fb->Visual.samples > 1) {
1092       /* On Gen6, null render targets seem to cause GPU hangs when
1093        * multisampling.  So work around this problem by rendering into dummy
1094        * color buffer.
1095        *
1096        * To decrease the amount of memory needed by the workaround buffer, we
1097        * set its pitch to 128 bytes (the width of a Y tile).  This means that
1098        * the amount of memory needed for the workaround buffer is
1099        * (width_in_tiles + height_in_tiles - 1) tiles.
1100        *
1101        * Note that since the workaround buffer will be interpreted by the
1102        * hardware as an interleaved multisampled buffer, we need to compute
1103        * width_in_tiles and height_in_tiles by dividing the width and height
1104        * by 16 rather than the normal Y-tile size of 32.
1105        */
1106       unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1107       unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1108       unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1109       brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1110                          size_needed);
1111       bo = brw->wm.multisampled_null_render_target_bo;
1112       surface_type = BRW_SURFACE_2D;
1113       pitch_minus_1 = 127;
1114       multisampling_state =
1115          brw_get_surface_num_multisamples(fb->Visual.samples);
1116    }
1117
1118    surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1119               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1120    if (intel->gen < 6) {
1121       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1122                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1123                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1124                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1125    }
1126    surf[1] = bo ? bo->offset : 0;
1127    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1128               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1129
1130    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1131     * Notes):
1132     *
1133     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
1134     */
1135    surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1136               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1137    surf[4] = multisampling_state;
1138    surf[5] = 0;
1139
1140    if (bo) {
1141       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1142                               brw->wm.surf_offset[unit] + 4,
1143                               bo, 0,
1144                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1145    }
1146 }
1147
1148 /**
1149  * Sets up a surface state structure to point at the given region.
1150  * While it is only used for the front/back buffer currently, it should be
1151  * usable for further buffers when doing ARB_draw_buffer support.
1152  */
1153 static void
1154 brw_update_renderbuffer_surface(struct brw_context *brw,
1155                                 struct gl_renderbuffer *rb,
1156                                 unsigned int unit)
1157 {
1158    struct intel_context *intel = &brw->intel;
1159    struct gl_context *ctx = &intel->ctx;
1160    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1161    struct intel_mipmap_tree *mt = irb->mt;
1162    struct intel_region *region;
1163    uint32_t *surf;
1164    uint32_t tile_x, tile_y;
1165    uint32_t format = 0;
1166    gl_format rb_format = intel_rb_format(irb);
1167
1168    if (irb->tex_image && !brw->has_surface_tile_offset) {
1169       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1170
1171       if (tile_x != 0 || tile_y != 0) {
1172          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1173           * destination in a miptree unless you actually setup your renderbuffer
1174           * as a miptree and used the fragile lod/array_index/etc. controls to
1175           * select the image.  So, instead, we just make a new single-level
1176           * miptree and render into that.
1177           */
1178          intel_renderbuffer_move_to_temp(intel, irb);
1179          mt = irb->mt;
1180       }
1181    }
1182
1183    region = irb->mt->region;
1184
1185    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1186                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1187
1188    switch (rb_format) {
1189    case MESA_FORMAT_SARGB8:
1190       /* _NEW_BUFFERS
1191        *
1192        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1193        * blend/update as sRGB.
1194        */
1195       if (ctx->Color.sRGBEnabled)
1196          format = brw_format_for_mesa_format(rb_format);
1197       else
1198          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1199       break;
1200    default:
1201       format = brw->render_target_format[rb_format];
1202       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1203          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1204                        __FUNCTION__, _mesa_get_format_name(rb_format));
1205       }
1206       break;
1207    }
1208
1209    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1210               format << BRW_SURFACE_FORMAT_SHIFT);
1211
1212    /* reloc */
1213    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1214               region->bo->offset);
1215
1216    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1217               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1218
1219    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1220               (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1221
1222    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1223
1224    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1225    /* Note that the low bits of these fields are missing, so
1226     * there's the possibility of getting in trouble.
1227     */
1228    assert(tile_x % 4 == 0);
1229    assert(tile_y % 2 == 0);
1230    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1231               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1232               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1233
1234    if (intel->gen < 6) {
1235       /* _NEW_COLOR */
1236       if (!ctx->Color.ColorLogicOpEnabled &&
1237           (ctx->Color.BlendEnabled & (1 << unit)))
1238          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1239
1240       if (!ctx->Color.ColorMask[unit][0])
1241          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1242       if (!ctx->Color.ColorMask[unit][1])
1243          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1244       if (!ctx->Color.ColorMask[unit][2])
1245          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1246
1247       /* As mentioned above, disable writes to the alpha component when the
1248        * renderbuffer is XRGB.
1249        */
1250       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1251           !ctx->Color.ColorMask[unit][3]) {
1252          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1253       }
1254    }
1255
1256    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1257                            brw->wm.surf_offset[unit] + 4,
1258                            region->bo,
1259                            surf[1] - region->bo->offset,
1260                            I915_GEM_DOMAIN_RENDER,
1261                            I915_GEM_DOMAIN_RENDER);
1262 }
1263
1264 /**
1265  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1266  */
1267 static void
1268 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1269 {
1270    struct intel_context *intel = &brw->intel;
1271    struct gl_context *ctx = &brw->intel.ctx;
1272    GLuint i;
1273
1274    /* _NEW_BUFFERS | _NEW_COLOR */
1275    /* Update surfaces for drawing buffers */
1276    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1277       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1278          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1279             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1280          } else {
1281             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1282          }
1283       }
1284    } else {
1285       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1286    }
1287    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1288 }
1289
1290 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1291    .dirty = {
1292       .mesa = (_NEW_COLOR |
1293                _NEW_BUFFERS),
1294       .brw = BRW_NEW_BATCH,
1295       .cache = 0
1296    },
1297    .emit = brw_update_renderbuffer_surfaces,
1298 };
1299
1300 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1301    .dirty = {
1302       .mesa = _NEW_BUFFERS,
1303       .brw = BRW_NEW_BATCH,
1304       .cache = 0
1305    },
1306    .emit = brw_update_renderbuffer_surfaces,
1307 };
1308
1309 /**
1310  * Construct SURFACE_STATE objects for enabled textures.
1311  */
1312 static void
1313 brw_update_texture_surfaces(struct brw_context *brw)
1314 {
1315    struct intel_context *intel = &brw->intel;
1316    struct gl_context *ctx = &intel->ctx;
1317
1318    /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1319     * Unfortunately, we're stuck using the gl_program structs until the
1320     * ARB_fragment_program front-end gets converted to GLSL IR.  These
1321     * have the downside that SamplerUnits is split and only contains the
1322     * mappings for samplers active in that stage.
1323     */
1324    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1325    struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1326
1327    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1328
1329    for (unsigned s = 0; s < num_samplers; s++) {
1330       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1331       brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1332
1333       if (vs->SamplersUsed & (1 << s)) {
1334          const unsigned unit = vs->SamplerUnits[s];
1335
1336          /* _NEW_TEXTURE */
1337          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1338             intel->vtbl.update_texture_surface(ctx, unit,
1339                                                brw->vs.surf_offset,
1340                                                SURF_INDEX_VS_TEXTURE(s));
1341          }
1342       }
1343
1344       if (fs->SamplersUsed & (1 << s)) {
1345          const unsigned unit = fs->SamplerUnits[s];
1346
1347          /* _NEW_TEXTURE */
1348          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1349             intel->vtbl.update_texture_surface(ctx, unit,
1350                                                brw->wm.surf_offset,
1351                                                SURF_INDEX_TEXTURE(s));
1352          }
1353       }
1354    }
1355
1356    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1357 }
1358
1359 const struct brw_tracked_state brw_texture_surfaces = {
1360    .dirty = {
1361       .mesa = _NEW_TEXTURE,
1362       .brw = BRW_NEW_BATCH |
1363              BRW_NEW_VERTEX_PROGRAM |
1364              BRW_NEW_FRAGMENT_PROGRAM,
1365       .cache = 0
1366    },
1367    .emit = brw_update_texture_surfaces,
1368 };
1369
1370 void
1371 brw_upload_ubo_surfaces(struct brw_context *brw,
1372                         struct gl_shader *shader,
1373                         uint32_t *surf_offsets)
1374 {
1375    struct gl_context *ctx = &brw->intel.ctx;
1376    struct intel_context *intel = &brw->intel;
1377
1378    if (!shader)
1379       return;
1380
1381    for (int i = 0; i < shader->NumUniformBlocks; i++) {
1382       struct gl_uniform_buffer_binding *binding;
1383       struct intel_buffer_object *intel_bo;
1384
1385       binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1386       intel_bo = intel_buffer_object(binding->BufferObject);
1387       drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1388
1389       /* Because behavior for referencing outside of the binding's size in the
1390        * glBindBufferRange case is undefined, we can just bind the whole buffer
1391        * glBindBufferBase wants and be a correct implementation.
1392        */
1393       int size = bo->size - binding->Offset;
1394       size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1395
1396       intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1397                                           size,
1398                                           &surf_offsets[i]);
1399    }
1400
1401    if (shader->NumUniformBlocks)
1402       brw->state.dirty.brw |= BRW_NEW_SURFACES;
1403 }
1404
1405 static void
1406 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1407 {
1408    struct gl_context *ctx = &brw->intel.ctx;
1409    /* _NEW_PROGRAM */
1410    struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1411
1412    if (!prog)
1413       return;
1414
1415    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1416                            &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1417 }
1418
1419 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1420    .dirty = {
1421       .mesa = (_NEW_PROGRAM |
1422                _NEW_BUFFER_OBJECT),
1423       .brw = BRW_NEW_BATCH,
1424       .cache = 0,
1425    },
1426    .emit = brw_upload_wm_ubo_surfaces,
1427 };
1428
1429 /**
1430  * Constructs the binding table for the WM surface state, which maps unit
1431  * numbers to surface state objects.
1432  */
1433 static void
1434 brw_upload_wm_binding_table(struct brw_context *brw)
1435 {
1436    struct intel_context *intel = &brw->intel;
1437    uint32_t *bind;
1438    int i;
1439
1440    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1441       intel->vtbl.create_constant_surface(brw, brw->shader_time.bo, 0,
1442                                           brw->shader_time.bo->size,
1443                                           &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1444    }
1445
1446    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1447     * space for the binding table.
1448     */
1449    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1450                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1451                           32, &brw->wm.bind_bo_offset);
1452
1453    /* BRW_NEW_SURFACES */
1454    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1455       bind[i] = brw->wm.surf_offset[i];
1456    }
1457
1458    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1459 }
1460
1461 const struct brw_tracked_state brw_wm_binding_table = {
1462    .dirty = {
1463       .mesa = 0,
1464       .brw = (BRW_NEW_BATCH |
1465               BRW_NEW_SURFACES),
1466       .cache = 0
1467    },
1468    .emit = brw_upload_wm_binding_table,
1469 };
1470
1471 void
1472 gen4_init_vtable_surface_functions(struct brw_context *brw)
1473 {
1474    struct intel_context *intel = &brw->intel;
1475
1476    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1477    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1478    intel->vtbl.update_null_renderbuffer_surface =
1479       brw_update_null_renderbuffer_surface;
1480    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1481 }