src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68    case GL_TEXTURE_CUBE_MAP_ARRAY:
  69       return BRW_SURFACE_CUBE;
  70
  71    default:
  72       assert(0);
  73       return 0;
  74    }
  75 }
  76
  77 struct surface_format_info {
  78    bool exists;
  79    int sampling;
  80    int filtering;
  81    int shadow_compare;
  82    int chroma_key;
  83    int render_target;
  84    int alpha_blend;
  85    int input_vb;
  86    int streamed_output_vb;
  87    int color_processing;
  88 };
  89
  90 /* This macro allows us to write the table almost as it appears in the PRM,
  91  * while restructuring it to turn it into the C code we want.
  92  */
  93 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  94    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  95
  96 #define Y 0
  97 #define x 999
  98 /**
  99  * This is the table of support for surface (texture, renderbuffer, and vertex
 100  * buffer, but not depthbuffer) formats across the various hardware generations.
 101  *
 102  * The table is formatted to match the documentation, except that the docs have
 103  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 104  * it in our table, here's the mapping:
 105  *
 106  * Y*: 45
 107  * Y+: 45 (g45/gm45)
 108  * Y~: 50 (gen5)
 109  * Y^: 60 (gen6)
 110  * Y#: 70 (gen7)
 111  *
 112  * The abbreviations in the header below are:
 113  * smpl  - Sampling Engine
 114  * filt  - Sampling Engine Filtering
 115  * shad  - Sampling Engine Shadow Map
 116  * CK    - Sampling Engine Chroma Key
 117  * RT    - Render Target
 118  * AB    - Alpha Blend Render Target
 119  * VB    - Input Vertex Buffer
 120  * SO    - Steamed Output Vertex Buffers (transform feedback)
 121  * color - Color Processing
 122  *
 123  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 124  */
 125 const struct surface_format_info surface_formats[] = {
 126 /* smpl filt shad CK  RT  AB  VB  SO  color */
 127    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 128    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 129    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 131    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 132    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 133    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 134    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 135    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 136    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 137    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 138    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 139    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 140    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 141    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 143    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 144    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 145    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 146    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 147    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 148    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 149    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 150    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 151    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 152    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 153    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 154    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 155    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 156    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 157    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 159    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 160    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 161    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 162    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 163    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 164    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 165    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 166    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 167    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 168 /* smpl filt shad CK  RT  AB  VB  SO  color */
 169    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 170    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 171    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 172    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 174    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 175    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 176    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 177    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 178    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 179    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 180    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 181    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 182    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 183    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 184    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 185    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 186    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 187    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 188    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 189    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 190    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 192    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 193    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 194    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 195    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 196    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 197    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 198    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 199    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 200    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 201    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 202    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 203    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 204    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 205    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 206    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 207 /* smpl filt shad CK  RT  AB  VB  SO  color */
 208    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 209    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 210    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 211    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 212    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 213    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 214    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 215    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 216    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 217    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 218    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 219    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 220    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 221    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 222    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 223    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 224    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 225    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 226    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 227    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 228    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 229    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 230    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 231    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 232    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 233    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 234    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 235    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 236    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 237    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 238    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 239    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 240    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 241    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 242    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 243 /* smpl filt shad CK  RT  AB  VB  SO  color */
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 245    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 246    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 247    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 248    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 249    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 250    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 251    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 255    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 256    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 257    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 258    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 259    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 260    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 261    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 262    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 263    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 264    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 265    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 266    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 267    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 268    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 269    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 270    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 271    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 272    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 273    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 274 /* smpl filt shad CK  RT  AB  VB  SO  color */
 275    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 276    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 277    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 278    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 279    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 280    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 281    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 282    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 283    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 284    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 285    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 286    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 287    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 288 };
 289 #undef x
 290 #undef Y
 291
 292 uint32_t
 293 brw_format_for_mesa_format(gl_format mesa_format)
 294 {
 295    /* This table is ordered according to the enum ordering in formats.h.  We do
 296     * expect that enum to be extended without our explicit initialization
 297     * staying in sync, so we initialize to 0 even though
 298     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 299     */
 300    static const uint32_t table[MESA_FORMAT_COUNT] =
 301    {
 302       [MESA_FORMAT_RGBA8888] = 0,
 303       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 304       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 305       [MESA_FORMAT_ARGB8888_REV] = 0,
 306       [MESA_FORMAT_RGBX8888] = 0,
 307       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 308       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 309       [MESA_FORMAT_XRGB8888_REV] = 0,
 310       [MESA_FORMAT_RGB888] = 0,
 311       [MESA_FORMAT_BGR888] = 0,
 312       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 313       [MESA_FORMAT_RGB565_REV] = 0,
 314       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 315       [MESA_FORMAT_ARGB4444_REV] = 0,
 316       [MESA_FORMAT_RGBA5551] = 0,
 317       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 318       [MESA_FORMAT_ARGB1555_REV] = 0,
 319       [MESA_FORMAT_AL44] = 0,
 320       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 321       [MESA_FORMAT_AL88_REV] = 0,
 322       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 323       [MESA_FORMAT_AL1616_REV] = 0,
 324       [MESA_FORMAT_RGB332] = 0,
 325       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 326       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 327       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 328       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 329       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 330       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 331       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 332       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 333       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 334       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 335       [MESA_FORMAT_RG88] = 0,
 336       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 337       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 338       [MESA_FORMAT_RG1616_REV] = 0,
 339       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 340       [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
 341       [MESA_FORMAT_Z24_S8] = 0,
 342       [MESA_FORMAT_S8_Z24] = 0,
 343       [MESA_FORMAT_Z16] = 0,
 344       [MESA_FORMAT_X8_Z24] = 0,
 345       [MESA_FORMAT_Z24_X8] = 0,
 346       [MESA_FORMAT_Z32] = 0,
 347       [MESA_FORMAT_S8] = 0,
 348
 349       [MESA_FORMAT_SRGB8] = 0,
 350       [MESA_FORMAT_SRGBA8] = 0,
 351       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 352       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 353       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 354       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 355       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 356       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 357       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 358
 359       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 360       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 361       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 362       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 363       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 364       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 365
 366       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 367       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 368       [MESA_FORMAT_RGB_FLOAT32] = 0,
 369       [MESA_FORMAT_RGB_FLOAT16] = 0,
 370       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 371       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 372       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 373       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 374       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 375       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 376       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 377       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 378       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 379       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 380       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 381       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 382
 383       [MESA_FORMAT_ALPHA_UINT8] = 0,
 384       [MESA_FORMAT_ALPHA_UINT16] = 0,
 385       [MESA_FORMAT_ALPHA_UINT32] = 0,
 386       [MESA_FORMAT_ALPHA_INT8] = 0,
 387       [MESA_FORMAT_ALPHA_INT16] = 0,
 388       [MESA_FORMAT_ALPHA_INT32] = 0,
 389
 390       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 391       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 392       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 393       [MESA_FORMAT_INTENSITY_INT8] = 0,
 394       [MESA_FORMAT_INTENSITY_INT16] = 0,
 395       [MESA_FORMAT_INTENSITY_INT32] = 0,
 396
 397       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 398       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 399       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 400       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 401       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 402       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 403
 404       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 405       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 406       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 407       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 408       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 409       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 410
 411       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 412       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 413       [MESA_FORMAT_RGB_INT8] = 0,
 414       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 415       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 416       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 417       [MESA_FORMAT_RGB_INT16] = 0,
 418       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 419       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 420       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 421       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 422       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 423
 424       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 425       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 426       [MESA_FORMAT_RGB_UINT8] = 0,
 427       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 428       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 429       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 430       [MESA_FORMAT_RGB_UINT16] = 0,
 431       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 432       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 433       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 434       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 435       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 436
 437       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 438       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 439       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 440       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 441       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 442       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 443       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 444       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 445       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 446       [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
 447       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 448
 449       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 450       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 451       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 452       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 453
 454       [MESA_FORMAT_L_LATC1] = 0,
 455       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 456       [MESA_FORMAT_LA_LATC2] = 0,
 457       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 458
 459       [MESA_FORMAT_SIGNED_A8] = 0,
 460       [MESA_FORMAT_SIGNED_L8] = 0,
 461       [MESA_FORMAT_SIGNED_AL88] = 0,
 462       [MESA_FORMAT_SIGNED_I8] = 0,
 463       [MESA_FORMAT_SIGNED_A16] = 0,
 464       [MESA_FORMAT_SIGNED_L16] = 0,
 465       [MESA_FORMAT_SIGNED_AL1616] = 0,
 466       [MESA_FORMAT_SIGNED_I16] = 0,
 467
 468       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 469       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 470
 471       [MESA_FORMAT_Z32_FLOAT] = 0,
 472       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 473    };
 474    assert(mesa_format < MESA_FORMAT_COUNT);
 475    return table[mesa_format];
 476 }
 477
 478 void
 479 brw_init_surface_formats(struct brw_context *brw)
 480 {
 481    struct intel_context *intel = &brw->intel;
 482    struct gl_context *ctx = &intel->ctx;
 483    int gen;
 484    gl_format format;
 485
 486    gen = intel->gen * 10;
 487    if (intel->is_g4x)
 488       gen += 5;
 489
 490    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 491       uint32_t texture, render;
 492       const struct surface_format_info *rinfo, *tinfo;
 493       bool is_integer = _mesa_is_format_integer_color(format);
 494
 495       render = texture = brw_format_for_mesa_format(format);
 496       tinfo = &surface_formats[texture];
 497
 498       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 499        * it.
 500        */
 501       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 502          continue;
 503
 504       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 505          ctx->TextureFormatSupported[format] = true;
 506
 507       /* Re-map some render target formats to make them supported when they
 508        * wouldn't be using their format for texturing.
 509        */
 510       switch (render) {
 511          /* For these formats, we just need to read/write the first
 512           * channel into R, which is to say that we just treat them as
 513           * GL_RED.
 514           */
 515       case BRW_SURFACEFORMAT_I32_FLOAT:
 516       case BRW_SURFACEFORMAT_L32_FLOAT:
 517          render = BRW_SURFACEFORMAT_R32_FLOAT;
 518          break;
 519       case BRW_SURFACEFORMAT_I16_FLOAT:
 520       case BRW_SURFACEFORMAT_L16_FLOAT:
 521          render = BRW_SURFACEFORMAT_R16_FLOAT;
 522          break;
 523       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 524          /* XRGB is handled as ARGB because the chips in this family
 525           * cannot render to XRGB targets.  This means that we have to
 526           * mask writes to alpha (ala glColorMask) and reconfigure the
 527           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 528           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 529           * used.
 530           */
 531          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 532          break;
 533       }
 534
 535       rinfo = &surface_formats[render];
 536
 537       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 538        * integer, so we don't need hardware support for blending on it.  Other
 539        * than that, GL in general requires alpha blending for render targets,
 540        * even though we don't support it for some formats.
 541        */
 542       if (gen >= rinfo->render_target &&
 543           (gen >= rinfo->alpha_blend || is_integer)) {
 544          brw->render_target_format[format] = render;
 545          brw->format_supported_as_render_target[format] = true;
 546       }
 547    }
 548
 549    /* We will check this table for FBO completeness, but the surface format
 550     * table above only covered color rendering.
 551     */
 552    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 553    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 554    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 555    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 556    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 557    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 558
 559    /* We remap depth formats to a supported texturing format in
 560     * translate_tex_format().
 561     */
 562    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 563    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 564    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 565    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 566    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 567
 568    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 569     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 570     */
 571    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 572
 573    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 574     * MESA_FORMAT during glCompressedTexImage2D().
 575     * See intel_mipmap_tree::wraps_etc2.
 576     */
 577    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 578    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 579    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 580    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 581    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 582    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 583    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 584    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 585    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 586    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 587 }
 588
 589 bool
 590 brw_render_target_supported(struct intel_context *intel,
 591                             struct gl_renderbuffer *rb)
 592 {
 593    struct brw_context *brw = brw_context(&intel->ctx);
 594    gl_format format = rb->Format;
 595
 596    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 597     * we would consider them renderable even though we don't have surface
 598     * support for their alpha behavior and don't have the blending unit
 599     * available to fake it like we do for XRGB8888.  Force them to being
 600     * unsupported.
 601     */
 602    if ((rb->_BaseFormat != GL_RGBA &&
 603         rb->_BaseFormat != GL_RG &&
 604         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 605       return false;
 606
 607    /* Under some conditions, MSAA is not supported for formats whose width is
 608     * more than 64 bits.
 609     */
 610    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 611       /* Gen6: MSAA on >64 bit formats is unsupported. */
 612       if (intel->gen <= 6)
 613          return false;
 614
 615       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 616       if (rb->NumSamples >= 8)
 617          return false;
 618    }
 619
 620    return brw->format_supported_as_render_target[format];
 621 }
 622
 623 GLuint
 624 translate_tex_format(gl_format mesa_format,
 625                      GLenum internal_format,
 626                      GLenum depth_mode,
 627                      GLenum srgb_decode)
 628 {
 629    if (srgb_decode == GL_SKIP_DECODE_EXT)
 630       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 631
 632    switch( mesa_format ) {
 633
 634    case MESA_FORMAT_Z16:
 635       return BRW_SURFACEFORMAT_I16_UNORM;
 636
 637    case MESA_FORMAT_S8_Z24:
 638    case MESA_FORMAT_X8_Z24:
 639       return BRW_SURFACEFORMAT_I24X8_UNORM;
 640
 641    case MESA_FORMAT_Z32_FLOAT:
 642       return BRW_SURFACEFORMAT_I32_FLOAT;
 643
 644    case MESA_FORMAT_Z32_FLOAT_X24S8:
 645       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 646
 647    case MESA_FORMAT_RGBA_FLOAT32:
 648       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 649        * assertion below.
 650        */
 651       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 652
 653    default:
 654       assert(brw_format_for_mesa_format(mesa_format) != 0);
 655       return brw_format_for_mesa_format(mesa_format);
 656    }
 657 }
 658
 659 uint32_t
 660 brw_get_surface_tiling_bits(uint32_t tiling)
 661 {
 662    switch (tiling) {
 663    case I915_TILING_X:
 664       return BRW_SURFACE_TILED;
 665    case I915_TILING_Y:
 666       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 667    default:
 668       return 0;
 669    }
 670 }
 671
 672
 673 uint32_t
 674 brw_get_surface_num_multisamples(unsigned num_samples)
 675 {
 676    if (num_samples > 1)
 677       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 678    else
 679       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 680 }
 681
 682
 683 /**
 684  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
 685  * swizzling.
 686  */
 687 int
 688 brw_get_texture_swizzle(const struct gl_texture_object *t)
 689 {
 690    const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 691
 692    int swizzles[SWIZZLE_NIL + 1] = {
 693       SWIZZLE_X,
 694       SWIZZLE_Y,
 695       SWIZZLE_Z,
 696       SWIZZLE_W,
 697       SWIZZLE_ZERO,
 698       SWIZZLE_ONE,
 699       SWIZZLE_NIL
 700    };
 701
 702    if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
 703        img->_BaseFormat == GL_DEPTH_STENCIL) {
 704       switch (t->DepthMode) {
 705       case GL_ALPHA:
 706          swizzles[0] = SWIZZLE_ZERO;
 707          swizzles[1] = SWIZZLE_ZERO;
 708          swizzles[2] = SWIZZLE_ZERO;
 709          swizzles[3] = SWIZZLE_X;
 710          break;
 711       case GL_LUMINANCE:
 712          swizzles[0] = SWIZZLE_X;
 713          swizzles[1] = SWIZZLE_X;
 714          swizzles[2] = SWIZZLE_X;
 715          swizzles[3] = SWIZZLE_ONE;
 716          break;
 717       case GL_INTENSITY:
 718          swizzles[0] = SWIZZLE_X;
 719          swizzles[1] = SWIZZLE_X;
 720          swizzles[2] = SWIZZLE_X;
 721          swizzles[3] = SWIZZLE_X;
 722          break;
 723       case GL_RED:
 724          swizzles[0] = SWIZZLE_X;
 725          swizzles[1] = SWIZZLE_ZERO;
 726          swizzles[2] = SWIZZLE_ZERO;
 727          swizzles[3] = SWIZZLE_ONE;
 728          break;
 729       }
 730    }
 731
 732    return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 733                         swizzles[GET_SWZ(t->_Swizzle, 1)],
 734                         swizzles[GET_SWZ(t->_Swizzle, 2)],
 735                         swizzles[GET_SWZ(t->_Swizzle, 3)]);
 736 }
 737
 738
 739 static void
 740 brw_update_buffer_texture_surface(struct gl_context *ctx,
 741                                   unsigned unit,
 742                                   uint32_t *binding_table,
 743                                   unsigned surf_index)
 744 {
 745    struct brw_context *brw = brw_context(ctx);
 746    struct intel_context *intel = &brw->intel;
 747    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 748    uint32_t *surf;
 749    struct intel_buffer_object *intel_obj =
 750       intel_buffer_object(tObj->BufferObject);
 751    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 752    gl_format format = tObj->_BufferObjectFormat;
 753    uint32_t brw_format = brw_format_for_mesa_format(format);
 754    int texel_size = _mesa_get_format_bytes(format);
 755
 756    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 757       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 758                     _mesa_get_format_name(format));
 759    }
 760
 761    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 762                           6 * 4, 32, &binding_table[surf_index]);
 763
 764    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 765               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 766
 767    if (intel->gen >= 6)
 768       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 769
 770    if (bo) {
 771       surf[1] = bo->offset; /* reloc */
 772
 773       /* Emit relocation to surface contents. */
 774       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 775                               binding_table[surf_index] + 4,
 776                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 777
 778       int w = intel_obj->Base.Size / texel_size;
 779       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 780                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 781       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 782                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 783    } else {
 784       surf[1] = 0;
 785       surf[2] = 0;
 786       surf[3] = 0;
 787    }
 788
 789    surf[4] = 0;
 790    surf[5] = 0;
 791 }
 792
 793 static void
 794 brw_update_texture_surface(struct gl_context *ctx,
 795                            unsigned unit,
 796                            uint32_t *binding_table,
 797                            unsigned surf_index)
 798 {
 799    struct brw_context *brw = brw_context(ctx);
 800    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 801    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 802    struct intel_mipmap_tree *mt = intelObj->mt;
 803    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 804    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 805    uint32_t *surf;
 806    int width, height, depth;
 807
 808    if (tObj->Target == GL_TEXTURE_BUFFER) {
 809       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 810       return;
 811    }
 812
 813    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 814
 815    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 816                           6 * 4, 32, &binding_table[surf_index]);
 817
 818    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 819               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 820               BRW_SURFACE_CUBEFACE_ENABLES |
 821               (translate_tex_format(mt->format,
 822                                     firstImage->InternalFormat,
 823                                     tObj->DepthMode,
 824                                     sampler->sRGBDecode) <<
 825                BRW_SURFACE_FORMAT_SHIFT));
 826
 827    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 828
 829    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 830               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 831               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 832
 833    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 834               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 835               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 836               BRW_SURFACE_PITCH_SHIFT);
 837
 838    surf[4] = 0;
 839
 840    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 841
 842    /* Emit relocation to surface contents */
 843    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 844                            binding_table[surf_index] + 4,
 845                            intelObj->mt->region->bo,
 846                            intelObj->mt->offset,
 847                            I915_GEM_DOMAIN_SAMPLER, 0);
 848 }
 849
 850 /**
 851  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 852  * read from this buffer with Data Port Read instructions/messages.
 853  */
 854 void
 855 brw_create_constant_surface(struct brw_context *brw,
 856                             drm_intel_bo *bo,
 857                             uint32_t offset,
 858                             int width,
 859                             uint32_t *out_offset)
 860 {
 861    struct intel_context *intel = &brw->intel;
 862    const GLint w = width - 1;
 863    uint32_t *surf;
 864
 865    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 866                           6 * 4, 32, out_offset);
 867
 868    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 869               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 870               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 871
 872    if (intel->gen >= 6)
 873       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 874
 875    surf[1] = bo->offset + offset; /* reloc */
 876
 877    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 878               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 879
 880    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 881               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 882
 883    surf[4] = 0;
 884    surf[5] = 0;
 885
 886    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 887     * bspec ("Data Cache") says that the data cache does not exist as
 888     * a separate cache and is just the sampler cache.
 889     */
 890    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 891                            *out_offset + 4,
 892                            bo, offset,
 893                            I915_GEM_DOMAIN_SAMPLER, 0);
 894 }
 895
 896 /**
 897  * Set up a binding table entry for use by stream output logic (transform
 898  * feedback).
 899  *
 900  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 901  */
 902 void
 903 brw_update_sol_surface(struct brw_context *brw,
 904                        struct gl_buffer_object *buffer_obj,
 905                        uint32_t *out_offset, unsigned num_vector_components,
 906                        unsigned stride_dwords, unsigned offset_dwords)
 907 {
 908    struct intel_context *intel = &brw->intel;
 909    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 910    drm_intel_bo *bo =
 911       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 912    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 913                                     out_offset);
 914    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 915    uint32_t offset_bytes = 4 * offset_dwords;
 916    size_t size_dwords = buffer_obj->Size / 4;
 917    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 918
 919    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 920     * too big to map using a single binding table entry?
 921     */
 922    assert((size_dwords - offset_dwords) / stride_dwords
 923           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 924
 925    if (size_dwords > offset_dwords + num_vector_components) {
 926       /* There is room for at least 1 transform feedback output in the buffer.
 927        * Compute the number of additional transform feedback outputs the
 928        * buffer has room for.
 929        */
 930       buffer_size_minus_1 =
 931          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 932    } else {
 933       /* There isn't even room for a single transform feedback output in the
 934        * buffer.  We can't configure the binding table entry to prevent output
 935        * entirely; we'll have to rely on the geometry shader to detect
 936        * overflow.  But to minimize the damage in case of a bug, set up the
 937        * binding table entry to just allow a single output.
 938        */
 939       buffer_size_minus_1 = 0;
 940    }
 941    width = buffer_size_minus_1 & 0x7f;
 942    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 943    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 944
 945    switch (num_vector_components) {
 946    case 1:
 947       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 948       break;
 949    case 2:
 950       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 951       break;
 952    case 3:
 953       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 954       break;
 955    case 4:
 956       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 957       break;
 958    default:
 959       assert(!"Invalid vector size for transform feedback output");
 960       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 961       break;
 962    }
 963
 964    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 965       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 966       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 967       BRW_SURFACE_RC_READ_WRITE;
 968    surf[1] = bo->offset + offset_bytes; /* reloc */
 969    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 970               height << BRW_SURFACE_HEIGHT_SHIFT);
 971    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 972               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 973    surf[4] = 0;
 974    surf[5] = 0;
 975
 976    /* Emit relocation to surface contents. */
 977    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 978                            *out_offset + 4,
 979                            bo, offset_bytes,
 980                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 981 }
 982
 983 /* Creates a new WM constant buffer reflecting the current fragment program's
 984  * constants, if needed by the fragment program.
 985  *
 986  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 987  * state atom.
 988  */
 989 static void
 990 brw_upload_wm_pull_constants(struct brw_context *brw)
 991 {
 992    struct gl_context *ctx = &brw->intel.ctx;
 993    struct intel_context *intel = &brw->intel;
 994    /* BRW_NEW_FRAGMENT_PROGRAM */
 995    struct brw_fragment_program *fp =
 996       (struct brw_fragment_program *) brw->fragment_program;
 997    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 998    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 999    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1000    float *constants;
1001    unsigned int i;
1002
1003    _mesa_load_state_parameters(ctx, params);
1004
1005    /* CACHE_NEW_WM_PROG */
1006    if (brw->wm.prog_data->nr_pull_params == 0) {
1007       if (brw->wm.const_bo) {
1008          drm_intel_bo_unreference(brw->wm.const_bo);
1009          brw->wm.const_bo = NULL;
1010          brw->wm.surf_offset[surf_index] = 0;
1011          brw->state.dirty.brw |= BRW_NEW_SURFACES;
1012       }
1013       return;
1014    }
1015
1016    drm_intel_bo_unreference(brw->wm.const_bo);
1017    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1018                                          size, 64);
1019
1020    /* _NEW_PROGRAM_CONSTANTS */
1021    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1022    constants = brw->wm.const_bo->virtual;
1023    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1024       constants[i] = *brw->wm.prog_data->pull_param[i];
1025    }
1026    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1027
1028    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1029                                        ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4,
1030                                        &brw->wm.surf_offset[surf_index]);
1031
1032    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1033 }
1034
1035 const struct brw_tracked_state brw_wm_pull_constants = {
1036    .dirty = {
1037       .mesa = (_NEW_PROGRAM_CONSTANTS),
1038       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1039       .cache = CACHE_NEW_WM_PROG,
1040    },
1041    .emit = brw_upload_wm_pull_constants,
1042 };
1043
1044 static void
1045 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1046 {
1047    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1048     * Notes):
1049     *
1050     *     A null surface will be used in instances where an actual surface is
1051     *     not bound. When a write message is generated to a null surface, no
1052     *     actual surface is written to. When a read message (including any
1053     *     sampling engine message) is generated to a null surface, the result
1054     *     is all zeros. Note that a null surface type is allowed to be used
1055     *     with all messages, even if it is not specificially indicated as
1056     *     supported. All of the remaining fields in surface state are ignored
1057     *     for null surfaces, with the following exceptions:
1058     *
1059     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1060     *       depth buffer’s corresponding state for all render target surfaces,
1061     *       including null.
1062     *
1063     *     - Surface Format must be R8G8B8A8_UNORM.
1064     */
1065    struct intel_context *intel = &brw->intel;
1066    struct gl_context *ctx = &intel->ctx;
1067    uint32_t *surf;
1068    unsigned surface_type = BRW_SURFACE_NULL;
1069    drm_intel_bo *bo = NULL;
1070    unsigned pitch_minus_1 = 0;
1071    uint32_t multisampling_state = 0;
1072
1073    /* _NEW_BUFFERS */
1074    const struct gl_framebuffer *fb = ctx->DrawBuffer;
1075
1076    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1077                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1078
1079    if (fb->Visual.samples > 1) {
1080       /* On Gen6, null render targets seem to cause GPU hangs when
1081        * multisampling.  So work around this problem by rendering into dummy
1082        * color buffer.
1083        *
1084        * To decrease the amount of memory needed by the workaround buffer, we
1085        * set its pitch to 128 bytes (the width of a Y tile).  This means that
1086        * the amount of memory needed for the workaround buffer is
1087        * (width_in_tiles + height_in_tiles - 1) tiles.
1088        *
1089        * Note that since the workaround buffer will be interpreted by the
1090        * hardware as an interleaved multisampled buffer, we need to compute
1091        * width_in_tiles and height_in_tiles by dividing the width and height
1092        * by 16 rather than the normal Y-tile size of 32.
1093        */
1094       unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1095       unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1096       unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1097       brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1098                          size_needed);
1099       bo = brw->wm.multisampled_null_render_target_bo;
1100       surface_type = BRW_SURFACE_2D;
1101       pitch_minus_1 = 127;
1102       multisampling_state =
1103          brw_get_surface_num_multisamples(fb->Visual.samples);
1104    }
1105
1106    surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1107               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1108    if (intel->gen < 6) {
1109       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1110                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1111                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1112                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1113    }
1114    surf[1] = bo ? bo->offset : 0;
1115    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1116               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1117
1118    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1119     * Notes):
1120     *
1121     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
1122     */
1123    surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1124               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1125    surf[4] = multisampling_state;
1126    surf[5] = 0;
1127
1128    if (bo) {
1129       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1130                               brw->wm.surf_offset[unit] + 4,
1131                               bo, 0,
1132                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1133    }
1134 }
1135
1136 /**
1137  * Sets up a surface state structure to point at the given region.
1138  * While it is only used for the front/back buffer currently, it should be
1139  * usable for further buffers when doing ARB_draw_buffer support.
1140  */
1141 static void
1142 brw_update_renderbuffer_surface(struct brw_context *brw,
1143                                 struct gl_renderbuffer *rb,
1144                                 unsigned int unit)
1145 {
1146    struct intel_context *intel = &brw->intel;
1147    struct gl_context *ctx = &intel->ctx;
1148    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1149    struct intel_mipmap_tree *mt = irb->mt;
1150    struct intel_region *region;
1151    uint32_t *surf;
1152    uint32_t tile_x, tile_y;
1153    uint32_t format = 0;
1154    gl_format rb_format = intel_rb_format(irb);
1155
1156    if (irb->tex_image && !brw->has_surface_tile_offset) {
1157       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1158
1159       if (tile_x != 0 || tile_y != 0) {
1160          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1161           * destination in a miptree unless you actually setup your renderbuffer
1162           * as a miptree and used the fragile lod/array_index/etc. controls to
1163           * select the image.  So, instead, we just make a new single-level
1164           * miptree and render into that.
1165           */
1166          intel_renderbuffer_move_to_temp(intel, irb);
1167          mt = irb->mt;
1168       }
1169    }
1170
1171    region = irb->mt->region;
1172
1173    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1174                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1175
1176    switch (rb_format) {
1177    case MESA_FORMAT_SARGB8:
1178       /* _NEW_BUFFERS
1179        *
1180        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1181        * blend/update as sRGB.
1182        */
1183       if (ctx->Color.sRGBEnabled)
1184          format = brw_format_for_mesa_format(rb_format);
1185       else
1186          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1187       break;
1188    default:
1189       format = brw->render_target_format[rb_format];
1190       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1191          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1192                        __FUNCTION__, _mesa_get_format_name(rb_format));
1193       }
1194       break;
1195    }
1196
1197    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1198               format << BRW_SURFACE_FORMAT_SHIFT);
1199
1200    /* reloc */
1201    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1202               region->bo->offset);
1203
1204    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1205               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1206
1207    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1208               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
1209
1210    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1211
1212    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1213    /* Note that the low bits of these fields are missing, so
1214     * there's the possibility of getting in trouble.
1215     */
1216    assert(tile_x % 4 == 0);
1217    assert(tile_y % 2 == 0);
1218    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1219               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1220               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1221
1222    if (intel->gen < 6) {
1223       /* _NEW_COLOR */
1224       if (!ctx->Color.ColorLogicOpEnabled &&
1225           (ctx->Color.BlendEnabled & (1 << unit)))
1226          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1227
1228       if (!ctx->Color.ColorMask[unit][0])
1229          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1230       if (!ctx->Color.ColorMask[unit][1])
1231          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1232       if (!ctx->Color.ColorMask[unit][2])
1233          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1234
1235       /* As mentioned above, disable writes to the alpha component when the
1236        * renderbuffer is XRGB.
1237        */
1238       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1239           !ctx->Color.ColorMask[unit][3]) {
1240          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1241       }
1242    }
1243
1244    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1245                            brw->wm.surf_offset[unit] + 4,
1246                            region->bo,
1247                            surf[1] - region->bo->offset,
1248                            I915_GEM_DOMAIN_RENDER,
1249                            I915_GEM_DOMAIN_RENDER);
1250 }
1251
1252 /**
1253  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1254  */
1255 static void
1256 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1257 {
1258    struct intel_context *intel = &brw->intel;
1259    struct gl_context *ctx = &brw->intel.ctx;
1260    GLuint i;
1261
1262    /* _NEW_BUFFERS | _NEW_COLOR */
1263    /* Update surfaces for drawing buffers */
1264    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1265       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1266          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1267             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1268          } else {
1269             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1270          }
1271       }
1272    } else {
1273       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1274    }
1275    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1276 }
1277
1278 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1279    .dirty = {
1280       .mesa = (_NEW_COLOR |
1281                _NEW_BUFFERS),
1282       .brw = BRW_NEW_BATCH,
1283       .cache = 0
1284    },
1285    .emit = brw_update_renderbuffer_surfaces,
1286 };
1287
1288 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1289    .dirty = {
1290       .mesa = _NEW_BUFFERS,
1291       .brw = BRW_NEW_BATCH,
1292       .cache = 0
1293    },
1294    .emit = brw_update_renderbuffer_surfaces,
1295 };
1296
1297 /**
1298  * Construct SURFACE_STATE objects for enabled textures.
1299  */
1300 static void
1301 brw_update_texture_surfaces(struct brw_context *brw)
1302 {
1303    struct intel_context *intel = &brw->intel;
1304    struct gl_context *ctx = &intel->ctx;
1305
1306    /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1307     * Unfortunately, we're stuck using the gl_program structs until the
1308     * ARB_fragment_program front-end gets converted to GLSL IR.  These
1309     * have the downside that SamplerUnits is split and only contains the
1310     * mappings for samplers active in that stage.
1311     */
1312    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1313    struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1314
1315    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1316
1317    for (unsigned s = 0; s < num_samplers; s++) {
1318       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1319       brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1320
1321       if (vs->SamplersUsed & (1 << s)) {
1322          const unsigned unit = vs->SamplerUnits[s];
1323
1324          /* _NEW_TEXTURE */
1325          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1326             intel->vtbl.update_texture_surface(ctx, unit,
1327                                                brw->vs.surf_offset,
1328                                                SURF_INDEX_VS_TEXTURE(s));
1329          }
1330       }
1331
1332       if (fs->SamplersUsed & (1 << s)) {
1333          const unsigned unit = fs->SamplerUnits[s];
1334
1335          /* _NEW_TEXTURE */
1336          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1337             intel->vtbl.update_texture_surface(ctx, unit,
1338                                                brw->wm.surf_offset,
1339                                                SURF_INDEX_TEXTURE(s));
1340          }
1341       }
1342    }
1343
1344    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1345 }
1346
1347 const struct brw_tracked_state brw_texture_surfaces = {
1348    .dirty = {
1349       .mesa = _NEW_TEXTURE,
1350       .brw = BRW_NEW_BATCH |
1351              BRW_NEW_VERTEX_PROGRAM |
1352              BRW_NEW_FRAGMENT_PROGRAM,
1353       .cache = 0
1354    },
1355    .emit = brw_update_texture_surfaces,
1356 };
1357
1358 void
1359 brw_upload_ubo_surfaces(struct brw_context *brw,
1360                         struct gl_shader *shader,
1361                         uint32_t *surf_offsets)
1362 {
1363    struct gl_context *ctx = &brw->intel.ctx;
1364    struct intel_context *intel = &brw->intel;
1365
1366    if (!shader)
1367       return;
1368
1369    for (int i = 0; i < shader->NumUniformBlocks; i++) {
1370       struct gl_uniform_buffer_binding *binding;
1371       struct intel_buffer_object *intel_bo;
1372
1373       binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1374       intel_bo = intel_buffer_object(binding->BufferObject);
1375       drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1376
1377       /* Because behavior for referencing outside of the binding's size in the
1378        * glBindBufferRange case is undefined, we can just bind the whole buffer
1379        * glBindBufferBase wants and be a correct implementation.
1380        */
1381       int size = bo->size - binding->Offset;
1382       size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1383
1384       intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1385                                           size,
1386                                           &surf_offsets[i]);
1387    }
1388
1389    if (shader->NumUniformBlocks)
1390       brw->state.dirty.brw |= BRW_NEW_SURFACES;
1391 }
1392
1393 static void
1394 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1395 {
1396    struct gl_context *ctx = &brw->intel.ctx;
1397    /* _NEW_PROGRAM */
1398    struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1399
1400    if (!prog)
1401       return;
1402
1403    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1404                            &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1405 }
1406
1407 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1408    .dirty = {
1409       .mesa = (_NEW_PROGRAM |
1410                _NEW_BUFFER_OBJECT),
1411       .brw = BRW_NEW_BATCH,
1412       .cache = 0,
1413    },
1414    .emit = brw_upload_wm_ubo_surfaces,
1415 };
1416
1417 /**
1418  * Constructs the binding table for the WM surface state, which maps unit
1419  * numbers to surface state objects.
1420  */
1421 static void
1422 brw_upload_wm_binding_table(struct brw_context *brw)
1423 {
1424    struct intel_context *intel = &brw->intel;
1425    uint32_t *bind;
1426    int i;
1427
1428    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1429       intel->vtbl.create_constant_surface(brw, brw->shader_time.bo, 0,
1430                                           brw->shader_time.bo->size,
1431                                           &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1432    }
1433
1434    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1435     * space for the binding table.
1436     */
1437    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1438                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1439                           32, &brw->wm.bind_bo_offset);
1440
1441    /* BRW_NEW_SURFACES */
1442    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1443       bind[i] = brw->wm.surf_offset[i];
1444    }
1445
1446    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1447 }
1448
1449 const struct brw_tracked_state brw_wm_binding_table = {
1450    .dirty = {
1451       .mesa = 0,
1452       .brw = (BRW_NEW_BATCH |
1453               BRW_NEW_SURFACES),
1454       .cache = 0
1455    },
1456    .emit = brw_upload_wm_binding_table,
1457 };
1458
1459 void
1460 gen4_init_vtable_surface_functions(struct brw_context *brw)
1461 {
1462    struct intel_context *intel = &brw->intel;
1463
1464    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1465    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1466    intel->vtbl.update_null_renderbuffer_surface =
1467       brw_update_null_renderbuffer_surface;
1468    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1469 }