src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = 0,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 295       [MESA_FORMAT_XRGB8888_REV] = 0,
 296       [MESA_FORMAT_RGB888] = 0,
 297       [MESA_FORMAT_BGR888] = 0,
 298       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 299       [MESA_FORMAT_RGB565_REV] = 0,
 300       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 301       [MESA_FORMAT_ARGB4444_REV] = 0,
 302       [MESA_FORMAT_RGBA5551] = 0,
 303       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 304       [MESA_FORMAT_ARGB1555_REV] = 0,
 305       [MESA_FORMAT_AL44] = 0,
 306       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 307       [MESA_FORMAT_AL88_REV] = 0,
 308       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 309       [MESA_FORMAT_AL1616_REV] = 0,
 310       [MESA_FORMAT_RGB332] = 0,
 311       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 312       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 313       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 314       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 315       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 316       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 317       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 318       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 319       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 320       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 321       [MESA_FORMAT_RG88] = 0,
 322       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 323       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 324       [MESA_FORMAT_RG1616_REV] = 0,
 325       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 326       [MESA_FORMAT_Z24_S8] = 0,
 327       [MESA_FORMAT_S8_Z24] = 0,
 328       [MESA_FORMAT_Z16] = 0,
 329       [MESA_FORMAT_X8_Z24] = 0,
 330       [MESA_FORMAT_Z24_S8] = 0,
 331       [MESA_FORMAT_Z32] = 0,
 332       [MESA_FORMAT_S8] = 0,
 333
 334       [MESA_FORMAT_SRGB8] = 0,
 335       [MESA_FORMAT_SRGBA8] = 0,
 336       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 337       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 338       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 340       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 341       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 343
 344       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 345       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 346       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 347       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 348       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 349       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 350
 351       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 352       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 353       [MESA_FORMAT_RGB_FLOAT32] = 0,
 354       [MESA_FORMAT_RGB_FLOAT16] = 0,
 355       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 356       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 357       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 358       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 361       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 362       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 363       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 364       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 365       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 366       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 367
 368       [MESA_FORMAT_ALPHA_UINT8] = 0,
 369       [MESA_FORMAT_ALPHA_UINT16] = 0,
 370       [MESA_FORMAT_ALPHA_UINT32] = 0,
 371       [MESA_FORMAT_ALPHA_INT8] = 0,
 372       [MESA_FORMAT_ALPHA_INT16] = 0,
 373       [MESA_FORMAT_ALPHA_INT32] = 0,
 374
 375       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 376       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 377       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 378       [MESA_FORMAT_INTENSITY_INT8] = 0,
 379       [MESA_FORMAT_INTENSITY_INT16] = 0,
 380       [MESA_FORMAT_INTENSITY_INT32] = 0,
 381
 382       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 383       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 384       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 385       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 386       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 388
 389       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 390       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 395
 396       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 397       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 398       [MESA_FORMAT_RGB_INT8] = 0,
 399       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 400       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 401       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 402       [MESA_FORMAT_RGB_INT16] = 0,
 403       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 404       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 405       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 406       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 407       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 408
 409       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 410       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 411       [MESA_FORMAT_RGB_UINT8] = 0,
 412       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 413       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 414       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 415       [MESA_FORMAT_RGB_UINT16] = 0,
 416       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 417       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 418       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 419       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 420       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 421
 422       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 423       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 424       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 426       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 427       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 428       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 429       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 430       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 431       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 432       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 433
 434       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 435       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 436       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 437       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 438
 439       [MESA_FORMAT_L_LATC1] = 0,
 440       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 441       [MESA_FORMAT_LA_LATC2] = 0,
 442       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 443
 444       [MESA_FORMAT_SIGNED_A8] = 0,
 445       [MESA_FORMAT_SIGNED_L8] = 0,
 446       [MESA_FORMAT_SIGNED_AL88] = 0,
 447       [MESA_FORMAT_SIGNED_I8] = 0,
 448       [MESA_FORMAT_SIGNED_A16] = 0,
 449       [MESA_FORMAT_SIGNED_L16] = 0,
 450       [MESA_FORMAT_SIGNED_AL1616] = 0,
 451       [MESA_FORMAT_SIGNED_I16] = 0,
 452
 453       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 454       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 455
 456       [MESA_FORMAT_Z32_FLOAT] = 0,
 457       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 458    };
 459    assert(mesa_format < MESA_FORMAT_COUNT);
 460    return table[mesa_format];
 461 }
 462
 463 void
 464 brw_init_surface_formats(struct brw_context *brw)
 465 {
 466    struct intel_context *intel = &brw->intel;
 467    struct gl_context *ctx = &intel->ctx;
 468    int gen;
 469    gl_format format;
 470
 471    gen = intel->gen * 10;
 472    if (intel->is_g4x)
 473       gen += 5;
 474
 475    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 476       uint32_t texture, render;
 477       const struct surface_format_info *rinfo, *tinfo;
 478       bool is_integer = _mesa_is_format_integer_color(format);
 479
 480       render = texture = brw_format_for_mesa_format(format);
 481       tinfo = &surface_formats[texture];
 482
 483       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 484        * it.
 485        */
 486       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 487          continue;
 488
 489       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 490          ctx->TextureFormatSupported[format] = true;
 491
 492       /* Re-map some render target formats to make them supported when they
 493        * wouldn't be using their format for texturing.
 494        */
 495       switch (render) {
 496          /* For these formats, we just need to read/write the first
 497           * channel into R, which is to say that we just treat them as
 498           * GL_RED.
 499           */
 500       case BRW_SURFACEFORMAT_I32_FLOAT:
 501       case BRW_SURFACEFORMAT_L32_FLOAT:
 502          render = BRW_SURFACEFORMAT_R32_FLOAT;
 503          break;
 504       case BRW_SURFACEFORMAT_I16_FLOAT:
 505       case BRW_SURFACEFORMAT_L16_FLOAT:
 506          render = BRW_SURFACEFORMAT_R16_FLOAT;
 507          break;
 508       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 509          /* XRGB is handled as ARGB because the chips in this family
 510           * cannot render to XRGB targets.  This means that we have to
 511           * mask writes to alpha (ala glColorMask) and reconfigure the
 512           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 513           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 514           * used.
 515           */
 516          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 517          break;
 518       }
 519
 520       rinfo = &surface_formats[render];
 521
 522       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 523        * integer, so we don't need hardware support for blending on it.  Other
 524        * than that, GL in general requires alpha blending for render targets,
 525        * even though we don't support it for some formats.
 526        *
 527        * We don't currently support rendering to SNORM textures because some of
 528        * the ARB_color_buffer_float clamping is broken for it
 529        * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
 530        */
 531       if (gen >= rinfo->render_target &&
 532           (gen >= rinfo->alpha_blend || is_integer) &&
 533           _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
 534          brw->render_target_format[format] = render;
 535          brw->format_supported_as_render_target[format] = true;
 536       }
 537    }
 538
 539    /* We will check this table for FBO completeness, but the surface format
 540     * table above only covered color rendering.
 541     */
 542    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 543    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 544    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 545    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 546    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 547    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 548
 549    /* We remap depth formats to a supported texturing format in
 550     * translate_tex_format().
 551     */
 552    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 553    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 554    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 555    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 556    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 557 }
 558
 559 bool
 560 brw_render_target_supported(struct intel_context *intel, gl_format format)
 561 {
 562    struct brw_context *brw = brw_context(&intel->ctx);
 563    /* Not exactly true, as some of those formats are not renderable.
 564     * But at least we know how to translate them.
 565     */
 566    return brw->format_supported_as_render_target[format];
 567 }
 568
 569 GLuint
 570 translate_tex_format(gl_format mesa_format,
 571                      GLenum internal_format,
 572                      GLenum depth_mode,
 573                      GLenum srgb_decode)
 574 {
 575    switch( mesa_format ) {
 576
 577    case MESA_FORMAT_Z16:
 578       return BRW_SURFACEFORMAT_I16_UNORM;
 579
 580    case MESA_FORMAT_S8_Z24:
 581    case MESA_FORMAT_X8_Z24:
 582       return BRW_SURFACEFORMAT_I24X8_UNORM;
 583
 584    case MESA_FORMAT_Z32_FLOAT:
 585       return BRW_SURFACEFORMAT_I32_FLOAT;
 586
 587    case MESA_FORMAT_Z32_FLOAT_X24S8:
 588       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 589
 590    case MESA_FORMAT_SARGB8:
 591    case MESA_FORMAT_SLA8:
 592    case MESA_FORMAT_SL8:
 593       if (srgb_decode == GL_DECODE_EXT)
 594          return brw_format_for_mesa_format(mesa_format);
 595       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 596          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 597
 598    case MESA_FORMAT_RGBA8888_REV:
 599       /* This format is not renderable? */
 600       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 601
 602    case MESA_FORMAT_RGBA_FLOAT32:
 603       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 604        * assertion below.
 605        */
 606       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 607
 608    default:
 609       assert(brw_format_for_mesa_format(mesa_format) != 0);
 610       return brw_format_for_mesa_format(mesa_format);
 611    }
 612 }
 613
 614 static uint32_t
 615 brw_get_surface_tiling_bits(uint32_t tiling)
 616 {
 617    switch (tiling) {
 618    case I915_TILING_X:
 619       return BRW_SURFACE_TILED;
 620    case I915_TILING_Y:
 621       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 622    default:
 623       return 0;
 624    }
 625 }
 626
 627 static void
 628 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 629 {
 630    struct brw_context *brw = brw_context(ctx);
 631    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 632    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 633    struct intel_mipmap_tree *mt = intelObj->mt;
 634    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 635    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 636    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 637    uint32_t *surf;
 638    int width, height, depth;
 639
 640    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 641
 642    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 643                           6 * 4, 32, &brw->bind.surf_offset[surf_index]);
 644
 645    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 646               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 647               BRW_SURFACE_CUBEFACE_ENABLES |
 648               (translate_tex_format(mt->format,
 649                                     firstImage->InternalFormat,
 650                                     sampler->DepthMode,
 651                                     sampler->sRGBDecode) <<
 652                BRW_SURFACE_FORMAT_SHIFT));
 653
 654    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 655
 656    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 657               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 658               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 659
 660    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 661               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 662               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 663               BRW_SURFACE_PITCH_SHIFT);
 664
 665    surf[4] = 0;
 666
 667    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 668
 669    /* Emit relocation to surface contents */
 670    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 671                            brw->bind.surf_offset[surf_index] + 4,
 672                            intelObj->mt->region->bo, 0,
 673                            I915_GEM_DOMAIN_SAMPLER, 0);
 674 }
 675
 676 /**
 677  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 678  * read from this buffer with Data Port Read instructions/messages.
 679  */
 680 void
 681 brw_create_constant_surface(struct brw_context *brw,
 682                             drm_intel_bo *bo,
 683                             int width,
 684                             uint32_t *out_offset)
 685 {
 686    struct intel_context *intel = &brw->intel;
 687    const GLint w = width - 1;
 688    uint32_t *surf;
 689
 690    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 691                           6 * 4, 32, out_offset);
 692
 693    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 694               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 695               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 696
 697    if (intel->gen >= 6)
 698       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 699
 700    surf[1] = bo->offset; /* reloc */
 701
 702    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 703               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 704
 705    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 706               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 707
 708    surf[4] = 0;
 709    surf[5] = 0;
 710
 711    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 712     * bspec ("Data Cache") says that the data cache does not exist as
 713     * a separate cache and is just the sampler cache.
 714     */
 715    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 716                            *out_offset + 4,
 717                            bo, 0,
 718                            I915_GEM_DOMAIN_SAMPLER, 0);
 719 }
 720
 721 /**
 722  * Set up a binding table entry for use by stream output logic (transform
 723  * feedback).
 724  *
 725  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 726  */
 727 void
 728 brw_update_sol_surface(struct brw_context *brw,
 729                        struct gl_buffer_object *buffer_obj,
 730                        uint32_t *out_offset, unsigned num_vector_components,
 731                        unsigned stride_dwords, unsigned offset_dwords)
 732 {
 733    drm_intel_bo *bo = intel_buffer_object(buffer_obj)->buffer;
 734    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 735                                     out_offset);
 736    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 737    uint32_t offset_bytes = 4 * offset_dwords;
 738    size_t size_dwords = buffer_obj->Size / 4;
 739    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 740
 741    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 742     * too big to map using a single binding table entry?
 743     */
 744    assert((size_dwords - offset_dwords) / stride_dwords
 745           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 746
 747    if (size_dwords > offset_dwords + num_vector_components) {
 748       /* There is room for at least 1 transform feedback output in the buffer.
 749        * Compute the number of additional transform feedback outputs the
 750        * buffer has room for.
 751        */
 752       buffer_size_minus_1 =
 753          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 754    } else {
 755       /* There isn't even room for a single transform feedback output in the
 756        * buffer.  We can't configure the binding table entry to prevent output
 757        * entirely; we'll have to rely on the geometry shader to detect
 758        * overflow.  But to minimize the damage in case of a bug, set up the
 759        * binding table entry to just allow a single output.
 760        */
 761       buffer_size_minus_1 = 0;
 762    }
 763    width = buffer_size_minus_1 & 0x7f;
 764    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 765    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 766
 767    switch (num_vector_components) {
 768    case 1:
 769       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 770       break;
 771    case 2:
 772       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 773       break;
 774    case 3:
 775       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 776       break;
 777    case 4:
 778       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 779       break;
 780    default:
 781       assert(!"Invalid vector size for transform feedback output");
 782       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 783       break;
 784    }
 785
 786    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 787       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 788       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 789       BRW_SURFACE_RC_READ_WRITE;
 790    surf[1] = bo->offset + offset_bytes; /* reloc */
 791    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 792               height << BRW_SURFACE_HEIGHT_SHIFT);
 793    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 794               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 795    surf[4] = 0;
 796    surf[5] = 0;
 797
 798    /* Emit relocation to surface contents. */
 799    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 800                            *out_offset + 4,
 801                            bo, offset_bytes,
 802                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 803 }
 804
 805 /* Creates a new WM constant buffer reflecting the current fragment program's
 806  * constants, if needed by the fragment program.
 807  *
 808  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 809  * state atom.
 810  */
 811 static void
 812 brw_upload_wm_pull_constants(struct brw_context *brw)
 813 {
 814    struct gl_context *ctx = &brw->intel.ctx;
 815    struct intel_context *intel = &brw->intel;
 816    /* BRW_NEW_FRAGMENT_PROGRAM */
 817    struct brw_fragment_program *fp =
 818       (struct brw_fragment_program *) brw->fragment_program;
 819    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 820    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 821    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 822    float *constants;
 823    unsigned int i;
 824
 825    _mesa_load_state_parameters(ctx, params);
 826
 827    /* CACHE_NEW_WM_PROG */
 828    if (brw->wm.prog_data->nr_pull_params == 0) {
 829       if (brw->wm.const_bo) {
 830          drm_intel_bo_unreference(brw->wm.const_bo);
 831          brw->wm.const_bo = NULL;
 832          brw->bind.surf_offset[surf_index] = 0;
 833          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 834       }
 835       return;
 836    }
 837
 838    drm_intel_bo_unreference(brw->wm.const_bo);
 839    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 840                                          size, 64);
 841
 842    /* _NEW_PROGRAM_CONSTANTS */
 843    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 844    constants = brw->wm.const_bo->virtual;
 845    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 846       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 847                                    brw->wm.prog_data->pull_param[i]);
 848    }
 849    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 850
 851    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 852                                        params->NumParameters,
 853                                        &brw->bind.surf_offset[surf_index]);
 854
 855    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 856 }
 857
 858 const struct brw_tracked_state brw_wm_pull_constants = {
 859    .dirty = {
 860       .mesa = (_NEW_PROGRAM_CONSTANTS),
 861       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 862       .cache = CACHE_NEW_WM_PROG,
 863    },
 864    .emit = brw_upload_wm_pull_constants,
 865 };
 866
 867 static void
 868 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 869 {
 870    struct intel_context *intel = &brw->intel;
 871    uint32_t *surf;
 872
 873    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 874                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 875
 876    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 877               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 878    if (intel->gen < 6) {
 879       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 880                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 881                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 882                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 883    }
 884    surf[1] = 0;
 885    surf[2] = 0;
 886    surf[3] = 0;
 887    surf[4] = 0;
 888    surf[5] = 0;
 889 }
 890
 891 /**
 892  * Sets up a surface state structure to point at the given region.
 893  * While it is only used for the front/back buffer currently, it should be
 894  * usable for further buffers when doing ARB_draw_buffer support.
 895  */
 896 static void
 897 brw_update_renderbuffer_surface(struct brw_context *brw,
 898                                 struct gl_renderbuffer *rb,
 899                                 unsigned int unit)
 900 {
 901    struct intel_context *intel = &brw->intel;
 902    struct gl_context *ctx = &intel->ctx;
 903    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 904    struct intel_mipmap_tree *mt = irb->mt;
 905    struct intel_region *region = irb->mt->region;
 906    uint32_t *surf;
 907    uint32_t tile_x, tile_y;
 908    uint32_t format = 0;
 909    gl_format rb_format = intel_rb_format(irb);
 910
 911    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 912                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 913
 914    switch (rb_format) {
 915    case MESA_FORMAT_SARGB8:
 916       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 917          surfaces to the blend/update as sRGB */
 918       if (ctx->Color.sRGBEnabled)
 919          format = brw_format_for_mesa_format(rb_format);
 920       else
 921          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 922       break;
 923    default:
 924       format = brw->render_target_format[rb_format];
 925       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 926          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 927                        __FUNCTION__, _mesa_get_format_name(rb_format));
 928       }
 929       break;
 930    }
 931
 932    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 933               format << BRW_SURFACE_FORMAT_SHIFT);
 934
 935    /* reloc */
 936    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 937               region->bo->offset);
 938
 939    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 940               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 941
 942    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 943               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 944
 945    surf[4] = 0;
 946
 947    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 948    /* Note that the low bits of these fields are missing, so
 949     * there's the possibility of getting in trouble.
 950     */
 951    assert(tile_x % 4 == 0);
 952    assert(tile_y % 2 == 0);
 953    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 954               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 955               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 956
 957    if (intel->gen < 6) {
 958       /* _NEW_COLOR */
 959       if (!ctx->Color.ColorLogicOpEnabled &&
 960           (ctx->Color.BlendEnabled & (1 << unit)))
 961          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 962
 963       if (!ctx->Color.ColorMask[unit][0])
 964          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 965       if (!ctx->Color.ColorMask[unit][1])
 966          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 967       if (!ctx->Color.ColorMask[unit][2])
 968          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 969
 970       /* As mentioned above, disable writes to the alpha component when the
 971        * renderbuffer is XRGB.
 972        */
 973       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 974           !ctx->Color.ColorMask[unit][3]) {
 975          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 976       }
 977    }
 978
 979    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 980                            brw->bind.surf_offset[unit] + 4,
 981                            region->bo,
 982                            surf[1] - region->bo->offset,
 983                            I915_GEM_DOMAIN_RENDER,
 984                            I915_GEM_DOMAIN_RENDER);
 985 }
 986
 987 /**
 988  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
 989  */
 990 static void
 991 brw_update_renderbuffer_surfaces(struct brw_context *brw)
 992 {
 993    struct intel_context *intel = &brw->intel;
 994    struct gl_context *ctx = &brw->intel.ctx;
 995    GLuint i;
 996
 997    /* _NEW_BUFFERS | _NEW_COLOR */
 998    /* Update surfaces for drawing buffers */
 999    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1000       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1001          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1002             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1003          } else {
1004             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1005          }
1006       }
1007    } else {
1008       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1009    }
1010    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1011 }
1012
1013 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1014    .dirty = {
1015       .mesa = (_NEW_COLOR |
1016                _NEW_BUFFERS),
1017       .brw = BRW_NEW_BATCH,
1018       .cache = 0
1019    },
1020    .emit = brw_update_renderbuffer_surfaces,
1021 };
1022
1023 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1024    .dirty = {
1025       .mesa = _NEW_BUFFERS,
1026       .brw = BRW_NEW_BATCH,
1027       .cache = 0
1028    },
1029    .emit = brw_update_renderbuffer_surfaces,
1030 };
1031
1032 /**
1033  * Construct SURFACE_STATE objects for enabled textures.
1034  */
1035 static void
1036 brw_update_texture_surfaces(struct brw_context *brw)
1037 {
1038    struct gl_context *ctx = &brw->intel.ctx;
1039
1040    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1041       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1042       const GLuint surf = SURF_INDEX_TEXTURE(i);
1043
1044       /* _NEW_TEXTURE */
1045       if (texUnit->_ReallyEnabled) {
1046          brw->intel.vtbl.update_texture_surface(ctx, i);
1047       } else {
1048          brw->bind.surf_offset[surf] = 0;
1049       }
1050    }
1051
1052    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1053 }
1054
1055 const struct brw_tracked_state brw_texture_surfaces = {
1056    .dirty = {
1057       .mesa = _NEW_TEXTURE,
1058       .brw = BRW_NEW_BATCH,
1059       .cache = 0
1060    },
1061    .emit = brw_update_texture_surfaces,
1062 };
1063
1064 /**
1065  * Constructs the binding table for the WM surface state, which maps unit
1066  * numbers to surface state objects.
1067  */
1068 static void
1069 brw_upload_binding_table(struct brw_context *brw)
1070 {
1071    uint32_t *bind;
1072    int i;
1073
1074    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1075     * space for the binding table.
1076     */
1077    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1078                           sizeof(uint32_t) * BRW_MAX_SURFACES,
1079                           32, &brw->bind.bo_offset);
1080
1081    /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */
1082    for (i = 0; i < BRW_MAX_SURFACES; i++) {
1083       bind[i] = brw->bind.surf_offset[i];
1084    }
1085
1086    brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
1087    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1088 }
1089
1090 const struct brw_tracked_state brw_binding_table = {
1091    .dirty = {
1092       .mesa = 0,
1093       .brw = (BRW_NEW_BATCH |
1094               BRW_NEW_VS_CONSTBUF |
1095               BRW_NEW_SURFACES),
1096       .cache = 0
1097    },
1098    .emit = brw_upload_binding_table,
1099 };
1100
1101 void
1102 gen4_init_vtable_surface_functions(struct brw_context *brw)
1103 {
1104    struct intel_context *intel = &brw->intel;
1105
1106    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1107    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1108    intel->vtbl.update_null_renderbuffer_surface =
1109       brw_update_null_renderbuffer_surface;
1110    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1111 }