src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 295       [MESA_FORMAT_XRGB8888_REV] = 0,
 296       [MESA_FORMAT_RGB888] = 0,
 297       [MESA_FORMAT_BGR888] = 0,
 298       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 299       [MESA_FORMAT_RGB565_REV] = 0,
 300       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 301       [MESA_FORMAT_ARGB4444_REV] = 0,
 302       [MESA_FORMAT_RGBA5551] = 0,
 303       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 304       [MESA_FORMAT_ARGB1555_REV] = 0,
 305       [MESA_FORMAT_AL44] = 0,
 306       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 307       [MESA_FORMAT_AL88_REV] = 0,
 308       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 309       [MESA_FORMAT_AL1616_REV] = 0,
 310       [MESA_FORMAT_RGB332] = 0,
 311       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 312       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 313       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 314       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 315       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 316       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 317       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 318       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 319       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 320       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 321       [MESA_FORMAT_RG88] = 0,
 322       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 323       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 324       [MESA_FORMAT_RG1616_REV] = 0,
 325       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 326       [MESA_FORMAT_Z24_S8] = 0,
 327       [MESA_FORMAT_S8_Z24] = 0,
 328       [MESA_FORMAT_Z16] = 0,
 329       [MESA_FORMAT_X8_Z24] = 0,
 330       [MESA_FORMAT_Z24_X8] = 0,
 331       [MESA_FORMAT_Z32] = 0,
 332       [MESA_FORMAT_S8] = 0,
 333
 334       [MESA_FORMAT_SRGB8] = 0,
 335       [MESA_FORMAT_SRGBA8] = 0,
 336       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 337       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 338       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 340       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 341       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 343
 344       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 345       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 346       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 347       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 348       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 349       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 350
 351       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 352       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 353       [MESA_FORMAT_RGB_FLOAT32] = 0,
 354       [MESA_FORMAT_RGB_FLOAT16] = 0,
 355       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 356       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 357       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 358       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 361       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 362       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 363       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 364       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 365       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 366       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 367
 368       [MESA_FORMAT_ALPHA_UINT8] = 0,
 369       [MESA_FORMAT_ALPHA_UINT16] = 0,
 370       [MESA_FORMAT_ALPHA_UINT32] = 0,
 371       [MESA_FORMAT_ALPHA_INT8] = 0,
 372       [MESA_FORMAT_ALPHA_INT16] = 0,
 373       [MESA_FORMAT_ALPHA_INT32] = 0,
 374
 375       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 376       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 377       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 378       [MESA_FORMAT_INTENSITY_INT8] = 0,
 379       [MESA_FORMAT_INTENSITY_INT16] = 0,
 380       [MESA_FORMAT_INTENSITY_INT32] = 0,
 381
 382       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 383       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 384       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 385       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 386       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 388
 389       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 390       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 395
 396       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 397       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 398       [MESA_FORMAT_RGB_INT8] = 0,
 399       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 400       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 401       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 402       [MESA_FORMAT_RGB_INT16] = 0,
 403       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 404       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 405       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 406       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 407       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 408
 409       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 410       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 411       [MESA_FORMAT_RGB_UINT8] = 0,
 412       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 413       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 414       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 415       [MESA_FORMAT_RGB_UINT16] = 0,
 416       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 417       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 418       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 419       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 420       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 421
 422       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 423       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 424       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 426       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 427       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 428       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 429       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 430       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 431       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 432       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 433
 434       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 435       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 436       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 437       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 438
 439       [MESA_FORMAT_L_LATC1] = 0,
 440       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 441       [MESA_FORMAT_LA_LATC2] = 0,
 442       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 443
 444       [MESA_FORMAT_SIGNED_A8] = 0,
 445       [MESA_FORMAT_SIGNED_L8] = 0,
 446       [MESA_FORMAT_SIGNED_AL88] = 0,
 447       [MESA_FORMAT_SIGNED_I8] = 0,
 448       [MESA_FORMAT_SIGNED_A16] = 0,
 449       [MESA_FORMAT_SIGNED_L16] = 0,
 450       [MESA_FORMAT_SIGNED_AL1616] = 0,
 451       [MESA_FORMAT_SIGNED_I16] = 0,
 452
 453       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 454       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 455
 456       [MESA_FORMAT_Z32_FLOAT] = 0,
 457       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 458    };
 459    assert(mesa_format < MESA_FORMAT_COUNT);
 460    return table[mesa_format];
 461 }
 462
 463 void
 464 brw_init_surface_formats(struct brw_context *brw)
 465 {
 466    struct intel_context *intel = &brw->intel;
 467    struct gl_context *ctx = &intel->ctx;
 468    int gen;
 469    gl_format format;
 470
 471    gen = intel->gen * 10;
 472    if (intel->is_g4x)
 473       gen += 5;
 474
 475    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 476       uint32_t texture, render;
 477       const struct surface_format_info *rinfo, *tinfo;
 478       bool is_integer = _mesa_is_format_integer_color(format);
 479
 480       render = texture = brw_format_for_mesa_format(format);
 481       tinfo = &surface_formats[texture];
 482
 483       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 484        * it.
 485        */
 486       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 487          continue;
 488
 489       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 490          ctx->TextureFormatSupported[format] = true;
 491
 492       /* Re-map some render target formats to make them supported when they
 493        * wouldn't be using their format for texturing.
 494        */
 495       switch (render) {
 496          /* For these formats, we just need to read/write the first
 497           * channel into R, which is to say that we just treat them as
 498           * GL_RED.
 499           */
 500       case BRW_SURFACEFORMAT_I32_FLOAT:
 501       case BRW_SURFACEFORMAT_L32_FLOAT:
 502          render = BRW_SURFACEFORMAT_R32_FLOAT;
 503          break;
 504       case BRW_SURFACEFORMAT_I16_FLOAT:
 505       case BRW_SURFACEFORMAT_L16_FLOAT:
 506          render = BRW_SURFACEFORMAT_R16_FLOAT;
 507          break;
 508       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 509          /* XRGB is handled as ARGB because the chips in this family
 510           * cannot render to XRGB targets.  This means that we have to
 511           * mask writes to alpha (ala glColorMask) and reconfigure the
 512           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 513           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 514           * used.
 515           */
 516          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 517          break;
 518       }
 519
 520       rinfo = &surface_formats[render];
 521
 522       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 523        * integer, so we don't need hardware support for blending on it.  Other
 524        * than that, GL in general requires alpha blending for render targets,
 525        * even though we don't support it for some formats.
 526        *
 527        * We don't currently support rendering to SNORM textures because some of
 528        * the ARB_color_buffer_float clamping is broken for it
 529        * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
 530        */
 531       if (gen >= rinfo->render_target &&
 532           (gen >= rinfo->alpha_blend || is_integer) &&
 533           _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
 534          brw->render_target_format[format] = render;
 535          brw->format_supported_as_render_target[format] = true;
 536       }
 537    }
 538
 539    /* We will check this table for FBO completeness, but the surface format
 540     * table above only covered color rendering.
 541     */
 542    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 543    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 544    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 545    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 546    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 547    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 548
 549    /* We remap depth formats to a supported texturing format in
 550     * translate_tex_format().
 551     */
 552    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 553    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 554    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 555    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 556    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 557 }
 558
 559 bool
 560 brw_render_target_supported(struct intel_context *intel,
 561                             struct gl_renderbuffer *rb)
 562 {
 563    struct brw_context *brw = brw_context(&intel->ctx);
 564    gl_format format = rb->Format;
 565
 566    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 567     * we would consider them renderable even though we don't have surface
 568     * support for their alpha behavior and don't have the blending unit
 569     * available to fake it like we do for XRGB8888.  Force them to being
 570     * unsupported.
 571     */
 572    if ((rb->_BaseFormat != GL_RGBA &&
 573         rb->_BaseFormat != GL_RG &&
 574         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 575       return false;
 576
 577    return brw->format_supported_as_render_target[format];
 578 }
 579
 580 GLuint
 581 translate_tex_format(gl_format mesa_format,
 582                      GLenum internal_format,
 583                      GLenum depth_mode,
 584                      GLenum srgb_decode)
 585 {
 586    switch( mesa_format ) {
 587
 588    case MESA_FORMAT_Z16:
 589       return BRW_SURFACEFORMAT_I16_UNORM;
 590
 591    case MESA_FORMAT_S8_Z24:
 592    case MESA_FORMAT_X8_Z24:
 593       return BRW_SURFACEFORMAT_I24X8_UNORM;
 594
 595    case MESA_FORMAT_Z32_FLOAT:
 596       return BRW_SURFACEFORMAT_I32_FLOAT;
 597
 598    case MESA_FORMAT_Z32_FLOAT_X24S8:
 599       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 600
 601    case MESA_FORMAT_SARGB8:
 602    case MESA_FORMAT_SLA8:
 603    case MESA_FORMAT_SL8:
 604       if (srgb_decode == GL_DECODE_EXT)
 605          return brw_format_for_mesa_format(mesa_format);
 606       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 607          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 608
 609    case MESA_FORMAT_RGBA_FLOAT32:
 610       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 611        * assertion below.
 612        */
 613       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 614
 615    default:
 616       assert(brw_format_for_mesa_format(mesa_format) != 0);
 617       return brw_format_for_mesa_format(mesa_format);
 618    }
 619 }
 620
 621 static uint32_t
 622 brw_get_surface_tiling_bits(uint32_t tiling)
 623 {
 624    switch (tiling) {
 625    case I915_TILING_X:
 626       return BRW_SURFACE_TILED;
 627    case I915_TILING_Y:
 628       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 629    default:
 630       return 0;
 631    }
 632 }
 633
 634 static void
 635 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 636 {
 637    struct brw_context *brw = brw_context(ctx);
 638    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 639    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 640    struct intel_mipmap_tree *mt = intelObj->mt;
 641    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 642    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 643    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 644    uint32_t *surf;
 645    int width, height, depth;
 646
 647    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 648
 649    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 650                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 651
 652    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 653               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 654               BRW_SURFACE_CUBEFACE_ENABLES |
 655               (translate_tex_format(mt->format,
 656                                     firstImage->InternalFormat,
 657                                     sampler->DepthMode,
 658                                     sampler->sRGBDecode) <<
 659                BRW_SURFACE_FORMAT_SHIFT));
 660
 661    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 662
 663    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 664               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 665               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 666
 667    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 668               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 669               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 670               BRW_SURFACE_PITCH_SHIFT);
 671
 672    surf[4] = 0;
 673
 674    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 675
 676    /* Emit relocation to surface contents */
 677    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 678                            brw->wm.surf_offset[surf_index] + 4,
 679                            intelObj->mt->region->bo, 0,
 680                            I915_GEM_DOMAIN_SAMPLER, 0);
 681 }
 682
 683 /**
 684  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 685  * read from this buffer with Data Port Read instructions/messages.
 686  */
 687 void
 688 brw_create_constant_surface(struct brw_context *brw,
 689                             drm_intel_bo *bo,
 690                             int width,
 691                             uint32_t *out_offset)
 692 {
 693    struct intel_context *intel = &brw->intel;
 694    const GLint w = width - 1;
 695    uint32_t *surf;
 696
 697    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 698                           6 * 4, 32, out_offset);
 699
 700    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 701               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 702               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 703
 704    if (intel->gen >= 6)
 705       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 706
 707    surf[1] = bo->offset; /* reloc */
 708
 709    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 710               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 711
 712    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 713               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 714
 715    surf[4] = 0;
 716    surf[5] = 0;
 717
 718    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 719     * bspec ("Data Cache") says that the data cache does not exist as
 720     * a separate cache and is just the sampler cache.
 721     */
 722    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 723                            *out_offset + 4,
 724                            bo, 0,
 725                            I915_GEM_DOMAIN_SAMPLER, 0);
 726 }
 727
 728 /**
 729  * Set up a binding table entry for use by stream output logic (transform
 730  * feedback).
 731  *
 732  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 733  */
 734 void
 735 brw_update_sol_surface(struct brw_context *brw,
 736                        struct gl_buffer_object *buffer_obj,
 737                        uint32_t *out_offset, unsigned num_vector_components,
 738                        unsigned stride_dwords, unsigned offset_dwords)
 739 {
 740    struct intel_context *intel = &brw->intel;
 741    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 742    drm_intel_bo *bo =
 743       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 744    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 745                                     out_offset);
 746    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 747    uint32_t offset_bytes = 4 * offset_dwords;
 748    size_t size_dwords = buffer_obj->Size / 4;
 749    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 750
 751    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 752     * too big to map using a single binding table entry?
 753     */
 754    assert((size_dwords - offset_dwords) / stride_dwords
 755           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 756
 757    if (size_dwords > offset_dwords + num_vector_components) {
 758       /* There is room for at least 1 transform feedback output in the buffer.
 759        * Compute the number of additional transform feedback outputs the
 760        * buffer has room for.
 761        */
 762       buffer_size_minus_1 =
 763          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 764    } else {
 765       /* There isn't even room for a single transform feedback output in the
 766        * buffer.  We can't configure the binding table entry to prevent output
 767        * entirely; we'll have to rely on the geometry shader to detect
 768        * overflow.  But to minimize the damage in case of a bug, set up the
 769        * binding table entry to just allow a single output.
 770        */
 771       buffer_size_minus_1 = 0;
 772    }
 773    width = buffer_size_minus_1 & 0x7f;
 774    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 775    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 776
 777    switch (num_vector_components) {
 778    case 1:
 779       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 780       break;
 781    case 2:
 782       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 783       break;
 784    case 3:
 785       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 786       break;
 787    case 4:
 788       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 789       break;
 790    default:
 791       assert(!"Invalid vector size for transform feedback output");
 792       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 793       break;
 794    }
 795
 796    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 797       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 798       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 799       BRW_SURFACE_RC_READ_WRITE;
 800    surf[1] = bo->offset + offset_bytes; /* reloc */
 801    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 802               height << BRW_SURFACE_HEIGHT_SHIFT);
 803    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 804               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 805    surf[4] = 0;
 806    surf[5] = 0;
 807
 808    /* Emit relocation to surface contents. */
 809    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 810                            *out_offset + 4,
 811                            bo, offset_bytes,
 812                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 813 }
 814
 815 /* Creates a new WM constant buffer reflecting the current fragment program's
 816  * constants, if needed by the fragment program.
 817  *
 818  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 819  * state atom.
 820  */
 821 static void
 822 brw_upload_wm_pull_constants(struct brw_context *brw)
 823 {
 824    struct gl_context *ctx = &brw->intel.ctx;
 825    struct intel_context *intel = &brw->intel;
 826    /* BRW_NEW_FRAGMENT_PROGRAM */
 827    struct brw_fragment_program *fp =
 828       (struct brw_fragment_program *) brw->fragment_program;
 829    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 830    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 831    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 832    float *constants;
 833    unsigned int i;
 834
 835    _mesa_load_state_parameters(ctx, params);
 836
 837    /* CACHE_NEW_WM_PROG */
 838    if (brw->wm.prog_data->nr_pull_params == 0) {
 839       if (brw->wm.const_bo) {
 840          drm_intel_bo_unreference(brw->wm.const_bo);
 841          brw->wm.const_bo = NULL;
 842          brw->wm.surf_offset[surf_index] = 0;
 843          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 844       }
 845       return;
 846    }
 847
 848    drm_intel_bo_unreference(brw->wm.const_bo);
 849    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 850                                          size, 64);
 851
 852    /* _NEW_PROGRAM_CONSTANTS */
 853    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 854    constants = brw->wm.const_bo->virtual;
 855    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 856       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 857                                    brw->wm.prog_data->pull_param[i]);
 858    }
 859    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 860
 861    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 862                                        params->NumParameters,
 863                                        &brw->wm.surf_offset[surf_index]);
 864
 865    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 866 }
 867
 868 const struct brw_tracked_state brw_wm_pull_constants = {
 869    .dirty = {
 870       .mesa = (_NEW_PROGRAM_CONSTANTS),
 871       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 872       .cache = CACHE_NEW_WM_PROG,
 873    },
 874    .emit = brw_upload_wm_pull_constants,
 875 };
 876
 877 static void
 878 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 879 {
 880    struct intel_context *intel = &brw->intel;
 881    uint32_t *surf;
 882
 883    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 884                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 885
 886    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 887               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 888    if (intel->gen < 6) {
 889       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 890                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 891                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 892                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 893    }
 894    surf[1] = 0;
 895    surf[2] = 0;
 896    surf[3] = 0;
 897    surf[4] = 0;
 898    surf[5] = 0;
 899 }
 900
 901 /**
 902  * Sets up a surface state structure to point at the given region.
 903  * While it is only used for the front/back buffer currently, it should be
 904  * usable for further buffers when doing ARB_draw_buffer support.
 905  */
 906 static void
 907 brw_update_renderbuffer_surface(struct brw_context *brw,
 908                                 struct gl_renderbuffer *rb,
 909                                 unsigned int unit)
 910 {
 911    struct intel_context *intel = &brw->intel;
 912    struct gl_context *ctx = &intel->ctx;
 913    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 914    struct intel_mipmap_tree *mt = irb->mt;
 915    struct intel_region *region;
 916    uint32_t *surf;
 917    uint32_t tile_x, tile_y;
 918    uint32_t format = 0;
 919    gl_format rb_format = intel_rb_format(irb);
 920
 921    if (irb->tex_image && !brw->has_surface_tile_offset) {
 922       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 923
 924       if (tile_x != 0 || tile_y != 0) {
 925          /* Original gen4 hardware couldn't draw to a non-tile-aligned
 926           * destination in a miptree unless you actually setup your renderbuffer
 927           * as a miptree and used the fragile lod/array_index/etc. controls to
 928           * select the image.  So, instead, we just make a new single-level
 929           * miptree and render into that.
 930           */
 931          struct intel_context *intel = intel_context(ctx);
 932          struct intel_texture_image *intel_image =
 933             intel_texture_image(irb->tex_image);
 934          struct intel_mipmap_tree *new_mt;
 935          int width, height, depth;
 936
 937          intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth);
 938
 939          new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target,
 940                                        intel_image->base.Base.TexFormat,
 941                                        intel_image->base.Base.Level,
 942                                        intel_image->base.Base.Level,
 943                                        width, height, depth,
 944                                        true);
 945
 946          intel_miptree_copy_teximage(intel, intel_image, new_mt);
 947          intel_miptree_reference(&irb->mt, intel_image->mt);
 948          intel_renderbuffer_set_draw_offset(irb);
 949          intel_miptree_release(&new_mt);
 950
 951          mt = irb->mt;
 952       }
 953    }
 954
 955    region = irb->mt->region;
 956
 957    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 958                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 959
 960    switch (rb_format) {
 961    case MESA_FORMAT_SARGB8:
 962       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 963          surfaces to the blend/update as sRGB */
 964       if (ctx->Color.sRGBEnabled)
 965          format = brw_format_for_mesa_format(rb_format);
 966       else
 967          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 968       break;
 969    default:
 970       format = brw->render_target_format[rb_format];
 971       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 972          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 973                        __FUNCTION__, _mesa_get_format_name(rb_format));
 974       }
 975       break;
 976    }
 977
 978    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 979               format << BRW_SURFACE_FORMAT_SHIFT);
 980
 981    /* reloc */
 982    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 983               region->bo->offset);
 984
 985    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 986               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 987
 988    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 989               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 990
 991    surf[4] = 0;
 992
 993    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 994    /* Note that the low bits of these fields are missing, so
 995     * there's the possibility of getting in trouble.
 996     */
 997    assert(tile_x % 4 == 0);
 998    assert(tile_y % 2 == 0);
 999    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1000               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1001               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1002
1003    if (intel->gen < 6) {
1004       /* _NEW_COLOR */
1005       if (!ctx->Color.ColorLogicOpEnabled &&
1006           (ctx->Color.BlendEnabled & (1 << unit)))
1007          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1008
1009       if (!ctx->Color.ColorMask[unit][0])
1010          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1011       if (!ctx->Color.ColorMask[unit][1])
1012          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1013       if (!ctx->Color.ColorMask[unit][2])
1014          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1015
1016       /* As mentioned above, disable writes to the alpha component when the
1017        * renderbuffer is XRGB.
1018        */
1019       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1020           !ctx->Color.ColorMask[unit][3]) {
1021          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1022       }
1023    }
1024
1025    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1026                            brw->wm.surf_offset[unit] + 4,
1027                            region->bo,
1028                            surf[1] - region->bo->offset,
1029                            I915_GEM_DOMAIN_RENDER,
1030                            I915_GEM_DOMAIN_RENDER);
1031 }
1032
1033 /**
1034  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1035  */
1036 static void
1037 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1038 {
1039    struct intel_context *intel = &brw->intel;
1040    struct gl_context *ctx = &brw->intel.ctx;
1041    GLuint i;
1042
1043    /* _NEW_BUFFERS | _NEW_COLOR */
1044    /* Update surfaces for drawing buffers */
1045    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1046       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1047          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1048             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1049          } else {
1050             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1051          }
1052       }
1053    } else {
1054       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1055    }
1056    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1057 }
1058
1059 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1060    .dirty = {
1061       .mesa = (_NEW_COLOR |
1062                _NEW_BUFFERS),
1063       .brw = BRW_NEW_BATCH,
1064       .cache = 0
1065    },
1066    .emit = brw_update_renderbuffer_surfaces,
1067 };
1068
1069 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1070    .dirty = {
1071       .mesa = _NEW_BUFFERS,
1072       .brw = BRW_NEW_BATCH,
1073       .cache = 0
1074    },
1075    .emit = brw_update_renderbuffer_surfaces,
1076 };
1077
1078 /**
1079  * Construct SURFACE_STATE objects for enabled textures.
1080  */
1081 static void
1082 brw_update_texture_surfaces(struct brw_context *brw)
1083 {
1084    struct gl_context *ctx = &brw->intel.ctx;
1085
1086    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1087       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1088       const GLuint surf = SURF_INDEX_TEXTURE(i);
1089
1090       /* _NEW_TEXTURE */
1091       if (texUnit->_ReallyEnabled) {
1092          brw->intel.vtbl.update_texture_surface(ctx, i);
1093       } else {
1094          brw->wm.surf_offset[surf] = 0;
1095       }
1096
1097       /* For now, just mirror the texture setup to the VS slots. */
1098       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
1099          brw->wm.surf_offset[surf];
1100    }
1101
1102    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1103 }
1104
1105 const struct brw_tracked_state brw_texture_surfaces = {
1106    .dirty = {
1107       .mesa = _NEW_TEXTURE,
1108       .brw = BRW_NEW_BATCH,
1109       .cache = 0
1110    },
1111    .emit = brw_update_texture_surfaces,
1112 };
1113
1114 /**
1115  * Constructs the binding table for the WM surface state, which maps unit
1116  * numbers to surface state objects.
1117  */
1118 static void
1119 brw_upload_wm_binding_table(struct brw_context *brw)
1120 {
1121    uint32_t *bind;
1122    int i;
1123
1124    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1125     * space for the binding table.
1126     */
1127    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1128                           sizeof(uint32_t) * BRW_MAX_SURFACES,
1129                           32, &brw->wm.bind_bo_offset);
1130
1131    /* BRW_NEW_SURFACES */
1132    for (i = 0; i < BRW_MAX_SURFACES; i++) {
1133       bind[i] = brw->wm.surf_offset[i];
1134    }
1135
1136    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1137 }
1138
1139 const struct brw_tracked_state brw_wm_binding_table = {
1140    .dirty = {
1141       .mesa = 0,
1142       .brw = (BRW_NEW_BATCH |
1143               BRW_NEW_SURFACES),
1144       .cache = 0
1145    },
1146    .emit = brw_upload_wm_binding_table,
1147 };
1148
1149 void
1150 gen4_init_vtable_surface_functions(struct brw_context *brw)
1151 {
1152    struct intel_context *intel = &brw->intel;
1153
1154    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1155    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1156    intel->vtbl.update_null_renderbuffer_surface =
1157       brw_update_null_renderbuffer_surface;
1158    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1159 }