src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/context.h"
  34 #include "main/mtypes.h"
  35 #include "main/samplerobj.h"
  36 #include "program/prog_parameter.h"
  37
  38 #include "intel_mipmap_tree.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_fbo.h"
  42 #include "intel_buffer_objects.h"
  43
  44 #include "brw_context.h"
  45 #include "brw_state.h"
  46 #include "brw_defines.h"
  47 #include "brw_wm.h"
  48
  49 GLuint
  50 translate_tex_target(GLenum target)
  51 {
  52    switch (target) {
  53    case GL_TEXTURE_1D:
  54    case GL_TEXTURE_1D_ARRAY_EXT:
  55       return BRW_SURFACE_1D;
  56
  57    case GL_TEXTURE_RECTANGLE_NV:
  58       return BRW_SURFACE_2D;
  59
  60    case GL_TEXTURE_2D:
  61    case GL_TEXTURE_2D_ARRAY_EXT:
  62    case GL_TEXTURE_EXTERNAL_OES:
  63    case GL_TEXTURE_2D_MULTISAMPLE:
  64    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
  65       return BRW_SURFACE_2D;
  66
  67    case GL_TEXTURE_3D:
  68       return BRW_SURFACE_3D;
  69
  70    case GL_TEXTURE_CUBE_MAP:
  71    case GL_TEXTURE_CUBE_MAP_ARRAY:
  72       return BRW_SURFACE_CUBE;
  73
  74    default:
  75       assert(0);
  76       return 0;
  77    }
  78 }
  79
  80 struct surface_format_info {
  81    bool exists;
  82    int sampling;
  83    int filtering;
  84    int shadow_compare;
  85    int chroma_key;
  86    int render_target;
  87    int alpha_blend;
  88    int input_vb;
  89    int streamed_output_vb;
  90    int color_processing;
  91 };
  92
  93 /* This macro allows us to write the table almost as it appears in the PRM,
  94  * while restructuring it to turn it into the C code we want.
  95  */
  96 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  97    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  98
  99 #define Y 0
 100 #define x 999
 101 /**
 102  * This is the table of support for surface (texture, renderbuffer, and vertex
 103  * buffer, but not depthbuffer) formats across the various hardware generations.
 104  *
 105  * The table is formatted to match the documentation, except that the docs have
 106  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 107  * it in our table, here's the mapping:
 108  *
 109  * Y*: 45
 110  * Y+: 45 (g45/gm45)
 111  * Y~: 50 (gen5)
 112  * Y^: 60 (gen6)
 113  * Y#: 70 (gen7)
 114  *
 115  * The abbreviations in the header below are:
 116  * smpl  - Sampling Engine
 117  * filt  - Sampling Engine Filtering
 118  * shad  - Sampling Engine Shadow Map
 119  * CK    - Sampling Engine Chroma Key
 120  * RT    - Render Target
 121  * AB    - Alpha Blend Render Target
 122  * VB    - Input Vertex Buffer
 123  * SO    - Steamed Output Vertex Buffers (transform feedback)
 124  * color - Color Processing
 125  *
 126  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 127  */
 128 const struct surface_format_info surface_formats[] = {
 129 /* smpl filt shad CK  RT  AB  VB  SO  color */
 130    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 131    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 132    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 133    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 134    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 135    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 136    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 137    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 138    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 139    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 140    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 141    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 145    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 146    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 147    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 148    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 149    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 150    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 151    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 152    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 153    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 154    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 155    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 156    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 157    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 158    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 159    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 160    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 161    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 162    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 163    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 164    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 165    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 166    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 167    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 168    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 169    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 171 /* smpl filt shad CK  RT  AB  VB  SO  color */
 172    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 173    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 175    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 176    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 177    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 178    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 179    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 180    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 181    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 182    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 183    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 184    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 185    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 186    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 187    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 189    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 190    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 191    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 192    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 193    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 194    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 195    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 196    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 197    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 198    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 199    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 200    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 201    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 202    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 203    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 204    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 205    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 206    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 207    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 208    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 209    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 210 /* smpl filt shad CK  RT  AB  VB  SO  color */
 211    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 212    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 213    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 214    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 215    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 216    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 217    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 218    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 219    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 220    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 221    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 222    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 223    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 224    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 225    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 226    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 227    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 228    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 229    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 230    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 231    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 232    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 233    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 234    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 235    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 236    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 237    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 238    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 239    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 240    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 241    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 242    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 243    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 245    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 246 /* smpl filt shad CK  RT  AB  VB  SO  color */
 247    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 248    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 249    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 250    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 251    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 252    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 253    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 255    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 258    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 259    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 260    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 261    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 262    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 263    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 264    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 265    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 266    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 267    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 268    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 269    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 272    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 273    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 274    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 275    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 276    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 277 /* smpl filt shad CK  RT  AB  VB  SO  color */
 278    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 279    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 280    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 281    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 282    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 283    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 284    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 285    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 286    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 287    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 288    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 289    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 290    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 291 };
 292 #undef x
 293 #undef Y
 294
 295 uint32_t
 296 brw_format_for_mesa_format(gl_format mesa_format)
 297 {
 298    /* This table is ordered according to the enum ordering in formats.h.  We do
 299     * expect that enum to be extended without our explicit initialization
 300     * staying in sync, so we initialize to 0 even though
 301     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 302     */
 303    static const uint32_t table[MESA_FORMAT_COUNT] =
 304    {
 305       [MESA_FORMAT_RGBA8888] = 0,
 306       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 307       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 308       [MESA_FORMAT_ARGB8888_REV] = 0,
 309       [MESA_FORMAT_RGBX8888] = 0,
 310       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 311       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 312       [MESA_FORMAT_XRGB8888_REV] = 0,
 313       [MESA_FORMAT_RGB888] = 0,
 314       [MESA_FORMAT_BGR888] = 0,
 315       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 316       [MESA_FORMAT_RGB565_REV] = 0,
 317       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 318       [MESA_FORMAT_ARGB4444_REV] = 0,
 319       [MESA_FORMAT_RGBA5551] = 0,
 320       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 321       [MESA_FORMAT_ARGB1555_REV] = 0,
 322       [MESA_FORMAT_AL44] = 0,
 323       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 324       [MESA_FORMAT_AL88_REV] = 0,
 325       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 326       [MESA_FORMAT_AL1616_REV] = 0,
 327       [MESA_FORMAT_RGB332] = 0,
 328       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 329       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 330       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 331       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 332       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 333       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 334       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 335       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 336       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 337       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 338       [MESA_FORMAT_RG88] = 0,
 339       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 340       [MESA_FORMAT_GR1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 341       [MESA_FORMAT_RG1616] = 0,
 342       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 343       [MESA_FORMAT_ABGR2101010_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT,
 344       [MESA_FORMAT_Z24_S8] = 0,
 345       [MESA_FORMAT_S8_Z24] = 0,
 346       [MESA_FORMAT_Z16] = 0,
 347       [MESA_FORMAT_X8_Z24] = 0,
 348       [MESA_FORMAT_Z24_X8] = 0,
 349       [MESA_FORMAT_Z32] = 0,
 350       [MESA_FORMAT_S8] = 0,
 351
 352       [MESA_FORMAT_SRGB8] = 0,
 353       [MESA_FORMAT_SRGBA8] = 0,
 354       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 355       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 356       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 357       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 358       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 359       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 360       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 361
 362       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 363       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 364       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 365       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 366       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 367       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 368
 369       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 370       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 371       [MESA_FORMAT_RGB_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32_FLOAT,
 372       [MESA_FORMAT_RGB_FLOAT16] = 0,
 373       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 374       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 375       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 376       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 377       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 378       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 379       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 380       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 381       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 382       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 383       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 384       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 385
 386       [MESA_FORMAT_ALPHA_UINT8] = 0,
 387       [MESA_FORMAT_ALPHA_UINT16] = 0,
 388       [MESA_FORMAT_ALPHA_UINT32] = 0,
 389       [MESA_FORMAT_ALPHA_INT8] = 0,
 390       [MESA_FORMAT_ALPHA_INT16] = 0,
 391       [MESA_FORMAT_ALPHA_INT32] = 0,
 392
 393       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 394       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 395       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 396       [MESA_FORMAT_INTENSITY_INT8] = 0,
 397       [MESA_FORMAT_INTENSITY_INT16] = 0,
 398       [MESA_FORMAT_INTENSITY_INT32] = 0,
 399
 400       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 401       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 402       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 403       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 404       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 405       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 406
 407       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 408       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 409       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 410       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 411       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 412       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 413
 414       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 415       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 416       [MESA_FORMAT_RGB_INT8] = 0,
 417       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 418       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 419       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 420       [MESA_FORMAT_RGB_INT16] = 0,
 421       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 422       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 423       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 424       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 425       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 426
 427       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 428       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 429       [MESA_FORMAT_RGB_UINT8] = 0,
 430       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 431       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 432       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 433       [MESA_FORMAT_RGB_UINT16] = 0,
 434       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 435       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 436       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 437       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 438       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 439
 440       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 441       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 442       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 443       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 444       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 445       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 446       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 447       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 448       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 449       [MESA_FORMAT_SIGNED_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM,
 450       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 451
 452       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 453       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 454       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 455       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 456
 457       [MESA_FORMAT_L_LATC1] = 0,
 458       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 459       [MESA_FORMAT_LA_LATC2] = 0,
 460       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 461
 462       [MESA_FORMAT_SIGNED_A8] = 0,
 463       [MESA_FORMAT_SIGNED_L8] = 0,
 464       [MESA_FORMAT_SIGNED_AL88] = 0,
 465       [MESA_FORMAT_SIGNED_I8] = 0,
 466       [MESA_FORMAT_SIGNED_A16] = 0,
 467       [MESA_FORMAT_SIGNED_L16] = 0,
 468       [MESA_FORMAT_SIGNED_AL1616] = 0,
 469       [MESA_FORMAT_SIGNED_I16] = 0,
 470
 471       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 472       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 473
 474       [MESA_FORMAT_Z32_FLOAT] = 0,
 475       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 476    };
 477    assert(mesa_format < MESA_FORMAT_COUNT);
 478    return table[mesa_format];
 479 }
 480
 481 void
 482 brw_init_surface_formats(struct brw_context *brw)
 483 {
 484    struct intel_context *intel = &brw->intel;
 485    struct gl_context *ctx = &intel->ctx;
 486    int gen;
 487    gl_format format;
 488
 489    gen = intel->gen * 10;
 490    if (intel->is_g4x)
 491       gen += 5;
 492
 493    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 494       uint32_t texture, render;
 495       const struct surface_format_info *rinfo, *tinfo;
 496       bool is_integer = _mesa_is_format_integer_color(format);
 497
 498       render = texture = brw_format_for_mesa_format(format);
 499       tinfo = &surface_formats[texture];
 500
 501       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 502        * it.
 503        */
 504       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 505          continue;
 506
 507       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 508          ctx->TextureFormatSupported[format] = true;
 509
 510       /* Re-map some render target formats to make them supported when they
 511        * wouldn't be using their format for texturing.
 512        */
 513       switch (render) {
 514          /* For these formats, we just need to read/write the first
 515           * channel into R, which is to say that we just treat them as
 516           * GL_RED.
 517           */
 518       case BRW_SURFACEFORMAT_I32_FLOAT:
 519       case BRW_SURFACEFORMAT_L32_FLOAT:
 520          render = BRW_SURFACEFORMAT_R32_FLOAT;
 521          break;
 522       case BRW_SURFACEFORMAT_I16_FLOAT:
 523       case BRW_SURFACEFORMAT_L16_FLOAT:
 524          render = BRW_SURFACEFORMAT_R16_FLOAT;
 525          break;
 526       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 527          /* XRGB is handled as ARGB because the chips in this family
 528           * cannot render to XRGB targets.  This means that we have to
 529           * mask writes to alpha (ala glColorMask) and reconfigure the
 530           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 531           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 532           * used.
 533           */
 534          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 535          break;
 536       }
 537
 538       rinfo = &surface_formats[render];
 539
 540       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 541        * integer, so we don't need hardware support for blending on it.  Other
 542        * than that, GL in general requires alpha blending for render targets,
 543        * even though we don't support it for some formats.
 544        */
 545       if (gen >= rinfo->render_target &&
 546           (gen >= rinfo->alpha_blend || is_integer)) {
 547          brw->render_target_format[format] = render;
 548          brw->format_supported_as_render_target[format] = true;
 549       }
 550    }
 551
 552    /* We will check this table for FBO completeness, but the surface format
 553     * table above only covered color rendering.
 554     */
 555    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 556    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 557    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 558    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 559    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 560    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 561
 562    /* We remap depth formats to a supported texturing format in
 563     * translate_tex_format().
 564     */
 565    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 566    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 567    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 568    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 569    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 570
 571    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 572     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 573     */
 574    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 575
 576    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 577     * MESA_FORMAT during glCompressedTexImage2D().
 578     * See intel_mipmap_tree::wraps_etc2.
 579     */
 580    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 581    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 582    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 583    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 584    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 585    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 586    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 587    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 588    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 589    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 590 }
 591
 592 bool
 593 brw_render_target_supported(struct intel_context *intel,
 594                             struct gl_renderbuffer *rb)
 595 {
 596    struct brw_context *brw = brw_context(&intel->ctx);
 597    gl_format format = rb->Format;
 598
 599    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 600     * we would consider them renderable even though we don't have surface
 601     * support for their alpha behavior and don't have the blending unit
 602     * available to fake it like we do for XRGB8888.  Force them to being
 603     * unsupported.
 604     */
 605    if ((rb->_BaseFormat != GL_RGBA &&
 606         rb->_BaseFormat != GL_RG &&
 607         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 608       return false;
 609
 610    /* Under some conditions, MSAA is not supported for formats whose width is
 611     * more than 64 bits.
 612     */
 613    if (rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 614       /* Gen6: MSAA on >64 bit formats is unsupported. */
 615       if (intel->gen <= 6)
 616          return false;
 617
 618       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 619       if (rb->NumSamples >= 8)
 620          return false;
 621    }
 622
 623    return brw->format_supported_as_render_target[format];
 624 }
 625
 626 GLuint
 627 translate_tex_format(struct intel_context *intel,
 628                      gl_format mesa_format,
 629                      GLenum internal_format,
 630                      GLenum depth_mode,
 631                      GLenum srgb_decode)
 632 {
 633    if (srgb_decode == GL_SKIP_DECODE_EXT)
 634       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 635
 636    switch( mesa_format ) {
 637
 638    case MESA_FORMAT_Z16:
 639       return BRW_SURFACEFORMAT_I16_UNORM;
 640
 641    case MESA_FORMAT_S8_Z24:
 642    case MESA_FORMAT_X8_Z24:
 643       return BRW_SURFACEFORMAT_I24X8_UNORM;
 644
 645    case MESA_FORMAT_Z32_FLOAT:
 646       return BRW_SURFACEFORMAT_I32_FLOAT;
 647
 648    case MESA_FORMAT_Z32_FLOAT_X24S8:
 649       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 650
 651    case MESA_FORMAT_RGBA_FLOAT32:
 652       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 653        * assertion below.
 654        */
 655       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 656
 657    case MESA_FORMAT_SRGB_DXT1:
 658       if (intel->gen == 4 && !intel->is_g4x) {
 659          /* Work around missing SRGB DXT1 support on original gen4 by just
 660           * skipping SRGB decode.  It's not worth not supporting sRGB in
 661           * general to prevent this.
 662           */
 663          WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
 664          mesa_format = MESA_FORMAT_RGB_DXT1;
 665       }
 666       return brw_format_for_mesa_format(mesa_format);
 667
 668    default:
 669       assert(brw_format_for_mesa_format(mesa_format) != 0);
 670       return brw_format_for_mesa_format(mesa_format);
 671    }
 672 }
 673
 674 uint32_t
 675 brw_get_surface_tiling_bits(uint32_t tiling)
 676 {
 677    switch (tiling) {
 678    case I915_TILING_X:
 679       return BRW_SURFACE_TILED;
 680    case I915_TILING_Y:
 681       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 682    default:
 683       return 0;
 684    }
 685 }
 686
 687
 688 uint32_t
 689 brw_get_surface_num_multisamples(unsigned num_samples)
 690 {
 691    if (num_samples > 1)
 692       return BRW_SURFACE_MULTISAMPLECOUNT_4;
 693    else
 694       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 695 }
 696
 697
 698 /**
 699  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
 700  * swizzling.
 701  */
 702 int
 703 brw_get_texture_swizzle(const struct gl_context *ctx,
 704                         const struct gl_texture_object *t)
 705 {
 706    const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 707
 708    int swizzles[SWIZZLE_NIL + 1] = {
 709       SWIZZLE_X,
 710       SWIZZLE_Y,
 711       SWIZZLE_Z,
 712       SWIZZLE_W,
 713       SWIZZLE_ZERO,
 714       SWIZZLE_ONE,
 715       SWIZZLE_NIL
 716    };
 717
 718    if (img->_BaseFormat == GL_DEPTH_COMPONENT ||
 719        img->_BaseFormat == GL_DEPTH_STENCIL) {
 720       GLenum depth_mode = t->DepthMode;
 721
 722       /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
 723        * with depth component data specified with a sized internal format.
 724        * Otherwise, it's left at the old default, GL_LUMINANCE.
 725        */
 726       if (_mesa_is_gles3(ctx) &&
 727           img->InternalFormat != GL_DEPTH_COMPONENT &&
 728           img->InternalFormat != GL_DEPTH_STENCIL) {
 729          depth_mode = GL_RED;
 730       }
 731
 732       switch (depth_mode) {
 733       case GL_ALPHA:
 734          swizzles[0] = SWIZZLE_ZERO;
 735          swizzles[1] = SWIZZLE_ZERO;
 736          swizzles[2] = SWIZZLE_ZERO;
 737          swizzles[3] = SWIZZLE_X;
 738          break;
 739       case GL_LUMINANCE:
 740          swizzles[0] = SWIZZLE_X;
 741          swizzles[1] = SWIZZLE_X;
 742          swizzles[2] = SWIZZLE_X;
 743          swizzles[3] = SWIZZLE_ONE;
 744          break;
 745       case GL_INTENSITY:
 746          swizzles[0] = SWIZZLE_X;
 747          swizzles[1] = SWIZZLE_X;
 748          swizzles[2] = SWIZZLE_X;
 749          swizzles[3] = SWIZZLE_X;
 750          break;
 751       case GL_RED:
 752          swizzles[0] = SWIZZLE_X;
 753          swizzles[1] = SWIZZLE_ZERO;
 754          swizzles[2] = SWIZZLE_ZERO;
 755          swizzles[3] = SWIZZLE_ONE;
 756          break;
 757       }
 758    }
 759
 760    /* If the texture's format is alpha-only, force R, G, and B to
 761     * 0.0. Similarly, if the texture's format has no alpha channel,
 762     * force the alpha value read to 1.0. This allows for the
 763     * implementation to use an RGBA texture for any of these formats
 764     * without leaking any unexpected values.
 765     */
 766    switch (img->_BaseFormat) {
 767    case GL_ALPHA:
 768       swizzles[0] = SWIZZLE_ZERO;
 769       swizzles[1] = SWIZZLE_ZERO;
 770       swizzles[2] = SWIZZLE_ZERO;
 771       break;
 772    case GL_RED:
 773    case GL_RG:
 774    case GL_RGB:
 775       swizzles[3] = SWIZZLE_ONE;
 776       break;
 777    }
 778
 779    return MAKE_SWIZZLE4(swizzles[GET_SWZ(t->_Swizzle, 0)],
 780                         swizzles[GET_SWZ(t->_Swizzle, 1)],
 781                         swizzles[GET_SWZ(t->_Swizzle, 2)],
 782                         swizzles[GET_SWZ(t->_Swizzle, 3)]);
 783 }
 784
 785
 786 static void
 787 brw_update_buffer_texture_surface(struct gl_context *ctx,
 788                                   unsigned unit,
 789                                   uint32_t *binding_table,
 790                                   unsigned surf_index)
 791 {
 792    struct brw_context *brw = brw_context(ctx);
 793    struct intel_context *intel = &brw->intel;
 794    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 795    uint32_t *surf;
 796    struct intel_buffer_object *intel_obj =
 797       intel_buffer_object(tObj->BufferObject);
 798    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 799    gl_format format = tObj->_BufferObjectFormat;
 800    uint32_t brw_format = brw_format_for_mesa_format(format);
 801    int texel_size = _mesa_get_format_bytes(format);
 802
 803    if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 804       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 805                     _mesa_get_format_name(format));
 806    }
 807
 808    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 809                           6 * 4, 32, &binding_table[surf_index]);
 810
 811    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 812               (brw_format_for_mesa_format(format) << BRW_SURFACE_FORMAT_SHIFT));
 813
 814    if (intel->gen >= 6)
 815       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 816
 817    if (bo) {
 818       surf[1] = bo->offset; /* reloc */
 819
 820       /* Emit relocation to surface contents. */
 821       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 822                               binding_table[surf_index] + 4,
 823                               bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 824
 825       int w = intel_obj->Base.Size / texel_size;
 826       surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 827                  ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 828       surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 829                  (texel_size - 1) << BRW_SURFACE_PITCH_SHIFT);
 830    } else {
 831       surf[1] = 0;
 832       surf[2] = 0;
 833       surf[3] = 0;
 834    }
 835
 836    surf[4] = 0;
 837    surf[5] = 0;
 838 }
 839
 840 static void
 841 brw_update_texture_surface(struct gl_context *ctx,
 842                            unsigned unit,
 843                            uint32_t *binding_table,
 844                            unsigned surf_index)
 845 {
 846    struct intel_context *intel = intel_context(ctx);
 847    struct brw_context *brw = brw_context(ctx);
 848    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 849    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 850    struct intel_mipmap_tree *mt = intelObj->mt;
 851    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 852    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 853    uint32_t *surf;
 854    int width, height, depth;
 855    uint32_t tile_x, tile_y;
 856
 857    if (tObj->Target == GL_TEXTURE_BUFFER) {
 858       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 859       return;
 860    }
 861
 862    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 863
 864    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 865                           6 * 4, 32, &binding_table[surf_index]);
 866
 867    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 868               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 869               BRW_SURFACE_CUBEFACE_ENABLES |
 870               (translate_tex_format(intel,
 871                                     mt->format,
 872                                     firstImage->InternalFormat,
 873                                     tObj->DepthMode,
 874                                     sampler->sRGBDecode) <<
 875                BRW_SURFACE_FORMAT_SHIFT));
 876
 877    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 878
 879    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 880               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 881               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 882
 883    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 884               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 885               (intelObj->mt->region->pitch - 1) <<
 886               BRW_SURFACE_PITCH_SHIFT);
 887
 888    surf[4] = 0;
 889
 890    intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 891                                   &tile_x, &tile_y);
 892    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 893    /* Note that the low bits of these fields are missing, so
 894     * there's the possibility of getting in trouble.
 895     */
 896    assert(tile_x % 4 == 0);
 897    assert(tile_y % 2 == 0);
 898    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 899               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 900               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 901
 902    /* Emit relocation to surface contents */
 903    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 904                            binding_table[surf_index] + 4,
 905                            intelObj->mt->region->bo,
 906                            intelObj->mt->offset,
 907                            I915_GEM_DOMAIN_SAMPLER, 0);
 908 }
 909
 910 /**
 911  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 912  * read from this buffer with Data Port Read instructions/messages.
 913  */
 914 void
 915 brw_create_constant_surface(struct brw_context *brw,
 916                             drm_intel_bo *bo,
 917                             uint32_t offset,
 918                             int width,
 919                             uint32_t *out_offset)
 920 {
 921    struct intel_context *intel = &brw->intel;
 922    const GLint w = width - 1;
 923    uint32_t *surf;
 924
 925    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 926                           6 * 4, 32, out_offset);
 927
 928    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 929               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 930               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 931
 932    if (intel->gen >= 6)
 933       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 934
 935    surf[1] = bo->offset + offset; /* reloc */
 936
 937    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 938               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 939
 940    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 941               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 942
 943    surf[4] = 0;
 944    surf[5] = 0;
 945
 946    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 947     * bspec ("Data Cache") says that the data cache does not exist as
 948     * a separate cache and is just the sampler cache.
 949     */
 950    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 951                            *out_offset + 4,
 952                            bo, offset,
 953                            I915_GEM_DOMAIN_SAMPLER, 0);
 954 }
 955
 956 /**
 957  * Set up a binding table entry for use by stream output logic (transform
 958  * feedback).
 959  *
 960  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 961  */
 962 void
 963 brw_update_sol_surface(struct brw_context *brw,
 964                        struct gl_buffer_object *buffer_obj,
 965                        uint32_t *out_offset, unsigned num_vector_components,
 966                        unsigned stride_dwords, unsigned offset_dwords)
 967 {
 968    struct intel_context *intel = &brw->intel;
 969    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 970    drm_intel_bo *bo =
 971       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 972    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 973                                     out_offset);
 974    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 975    uint32_t offset_bytes = 4 * offset_dwords;
 976    size_t size_dwords = buffer_obj->Size / 4;
 977    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 978
 979    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 980     * too big to map using a single binding table entry?
 981     */
 982    assert((size_dwords - offset_dwords) / stride_dwords
 983           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 984
 985    if (size_dwords > offset_dwords + num_vector_components) {
 986       /* There is room for at least 1 transform feedback output in the buffer.
 987        * Compute the number of additional transform feedback outputs the
 988        * buffer has room for.
 989        */
 990       buffer_size_minus_1 =
 991          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 992    } else {
 993       /* There isn't even room for a single transform feedback output in the
 994        * buffer.  We can't configure the binding table entry to prevent output
 995        * entirely; we'll have to rely on the geometry shader to detect
 996        * overflow.  But to minimize the damage in case of a bug, set up the
 997        * binding table entry to just allow a single output.
 998        */
 999       buffer_size_minus_1 = 0;
1000    }
1001    width = buffer_size_minus_1 & 0x7f;
1002    height = (buffer_size_minus_1 & 0xfff80) >> 7;
1003    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
1004
1005    switch (num_vector_components) {
1006    case 1:
1007       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1008       break;
1009    case 2:
1010       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1011       break;
1012    case 3:
1013       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
1014       break;
1015    case 4:
1016       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
1017       break;
1018    default:
1019       assert(!"Invalid vector size for transform feedback output");
1020       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
1021       break;
1022    }
1023
1024    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
1025       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
1026       surface_format << BRW_SURFACE_FORMAT_SHIFT |
1027       BRW_SURFACE_RC_READ_WRITE;
1028    surf[1] = bo->offset + offset_bytes; /* reloc */
1029    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
1030               height << BRW_SURFACE_HEIGHT_SHIFT);
1031    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1032               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1033    surf[4] = 0;
1034    surf[5] = 0;
1035
1036    /* Emit relocation to surface contents. */
1037    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1038                            *out_offset + 4,
1039                            bo, offset_bytes,
1040                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1041 }
1042
1043 /* Creates a new WM constant buffer reflecting the current fragment program's
1044  * constants, if needed by the fragment program.
1045  *
1046  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
1047  * state atom.
1048  */
1049 static void
1050 brw_upload_wm_pull_constants(struct brw_context *brw)
1051 {
1052    struct gl_context *ctx = &brw->intel.ctx;
1053    struct intel_context *intel = &brw->intel;
1054    /* BRW_NEW_FRAGMENT_PROGRAM */
1055    struct brw_fragment_program *fp =
1056       (struct brw_fragment_program *) brw->fragment_program;
1057    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
1058    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
1059    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
1060    float *constants;
1061    unsigned int i;
1062
1063    _mesa_load_state_parameters(ctx, params);
1064
1065    /* CACHE_NEW_WM_PROG */
1066    if (brw->wm.prog_data->nr_pull_params == 0) {
1067       if (brw->wm.const_bo) {
1068          drm_intel_bo_unreference(brw->wm.const_bo);
1069          brw->wm.const_bo = NULL;
1070          brw->wm.surf_offset[surf_index] = 0;
1071          brw->state.dirty.brw |= BRW_NEW_SURFACES;
1072       }
1073       return;
1074    }
1075
1076    drm_intel_bo_unreference(brw->wm.const_bo);
1077    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
1078                                          size, 64);
1079
1080    /* _NEW_PROGRAM_CONSTANTS */
1081    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
1082    constants = brw->wm.const_bo->virtual;
1083    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
1084       constants[i] = *brw->wm.prog_data->pull_param[i];
1085    }
1086    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
1087
1088    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo, 0,
1089                                        ALIGN(brw->wm.prog_data->nr_pull_params, 4) / 4,
1090                                        &brw->wm.surf_offset[surf_index]);
1091
1092    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1093 }
1094
1095 const struct brw_tracked_state brw_wm_pull_constants = {
1096    .dirty = {
1097       .mesa = (_NEW_PROGRAM_CONSTANTS),
1098       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
1099       .cache = CACHE_NEW_WM_PROG,
1100    },
1101    .emit = brw_upload_wm_pull_constants,
1102 };
1103
1104 static void
1105 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
1106 {
1107    /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
1108     * Notes):
1109     *
1110     *     A null surface will be used in instances where an actual surface is
1111     *     not bound. When a write message is generated to a null surface, no
1112     *     actual surface is written to. When a read message (including any
1113     *     sampling engine message) is generated to a null surface, the result
1114     *     is all zeros. Note that a null surface type is allowed to be used
1115     *     with all messages, even if it is not specificially indicated as
1116     *     supported. All of the remaining fields in surface state are ignored
1117     *     for null surfaces, with the following exceptions:
1118     *
1119     *     - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
1120     *       depth buffer’s corresponding state for all render target surfaces,
1121     *       including null.
1122     *
1123     *     - Surface Format must be R8G8B8A8_UNORM.
1124     */
1125    struct intel_context *intel = &brw->intel;
1126    struct gl_context *ctx = &intel->ctx;
1127    uint32_t *surf;
1128    unsigned surface_type = BRW_SURFACE_NULL;
1129    drm_intel_bo *bo = NULL;
1130    unsigned pitch_minus_1 = 0;
1131    uint32_t multisampling_state = 0;
1132
1133    /* _NEW_BUFFERS */
1134    const struct gl_framebuffer *fb = ctx->DrawBuffer;
1135
1136    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1137                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1138
1139    if (fb->Visual.samples > 1) {
1140       /* On Gen6, null render targets seem to cause GPU hangs when
1141        * multisampling.  So work around this problem by rendering into dummy
1142        * color buffer.
1143        *
1144        * To decrease the amount of memory needed by the workaround buffer, we
1145        * set its pitch to 128 bytes (the width of a Y tile).  This means that
1146        * the amount of memory needed for the workaround buffer is
1147        * (width_in_tiles + height_in_tiles - 1) tiles.
1148        *
1149        * Note that since the workaround buffer will be interpreted by the
1150        * hardware as an interleaved multisampled buffer, we need to compute
1151        * width_in_tiles and height_in_tiles by dividing the width and height
1152        * by 16 rather than the normal Y-tile size of 32.
1153        */
1154       unsigned width_in_tiles = ALIGN(fb->Width, 16) / 16;
1155       unsigned height_in_tiles = ALIGN(fb->Height, 16) / 16;
1156       unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096;
1157       brw_get_scratch_bo(intel, &brw->wm.multisampled_null_render_target_bo,
1158                          size_needed);
1159       bo = brw->wm.multisampled_null_render_target_bo;
1160       surface_type = BRW_SURFACE_2D;
1161       pitch_minus_1 = 127;
1162       multisampling_state =
1163          brw_get_surface_num_multisamples(fb->Visual.samples);
1164    }
1165
1166    surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT |
1167               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
1168    if (intel->gen < 6) {
1169       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
1170                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
1171                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1172                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
1173    }
1174    surf[1] = bo ? bo->offset : 0;
1175    surf[2] = ((fb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1176               (fb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1177
1178    /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
1179     * Notes):
1180     *
1181     *     If Surface Type is SURFTYPE_NULL, this field must be TRUE
1182     */
1183    surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y |
1184               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
1185    surf[4] = multisampling_state;
1186    surf[5] = 0;
1187
1188    if (bo) {
1189       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1190                               brw->wm.surf_offset[unit] + 4,
1191                               bo, 0,
1192                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
1193    }
1194 }
1195
1196 /**
1197  * Sets up a surface state structure to point at the given region.
1198  * While it is only used for the front/back buffer currently, it should be
1199  * usable for further buffers when doing ARB_draw_buffer support.
1200  */
1201 static void
1202 brw_update_renderbuffer_surface(struct brw_context *brw,
1203                                 struct gl_renderbuffer *rb,
1204                                 unsigned int unit)
1205 {
1206    struct intel_context *intel = &brw->intel;
1207    struct gl_context *ctx = &intel->ctx;
1208    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
1209    struct intel_mipmap_tree *mt = irb->mt;
1210    struct intel_region *region;
1211    uint32_t *surf;
1212    uint32_t tile_x, tile_y;
1213    uint32_t format = 0;
1214    gl_format rb_format = intel_rb_format(irb);
1215
1216    if (irb->tex_image && !brw->has_surface_tile_offset) {
1217       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
1218
1219       if (tile_x != 0 || tile_y != 0) {
1220          /* Original gen4 hardware couldn't draw to a non-tile-aligned
1221           * destination in a miptree unless you actually setup your renderbuffer
1222           * as a miptree and used the fragile lod/array_index/etc. controls to
1223           * select the image.  So, instead, we just make a new single-level
1224           * miptree and render into that.
1225           */
1226          intel_renderbuffer_move_to_temp(intel, irb);
1227          mt = irb->mt;
1228       }
1229    }
1230
1231    region = irb->mt->region;
1232
1233    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
1234                           6 * 4, 32, &brw->wm.surf_offset[unit]);
1235
1236    switch (rb_format) {
1237    case MESA_FORMAT_SARGB8:
1238       /* _NEW_BUFFERS
1239        *
1240        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
1241        * blend/update as sRGB.
1242        */
1243       if (ctx->Color.sRGBEnabled)
1244          format = brw_format_for_mesa_format(rb_format);
1245       else
1246          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
1247       break;
1248    default:
1249       format = brw->render_target_format[rb_format];
1250       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
1251          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
1252                        __FUNCTION__, _mesa_get_format_name(rb_format));
1253       }
1254       break;
1255    }
1256
1257    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
1258               format << BRW_SURFACE_FORMAT_SHIFT);
1259
1260    /* reloc */
1261    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
1262               region->bo->offset);
1263
1264    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
1265               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
1266
1267    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
1268               (region->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
1269
1270    surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
1271
1272    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
1273    /* Note that the low bits of these fields are missing, so
1274     * there's the possibility of getting in trouble.
1275     */
1276    assert(tile_x % 4 == 0);
1277    assert(tile_y % 2 == 0);
1278    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1279               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1280               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1281
1282    if (intel->gen < 6) {
1283       /* _NEW_COLOR */
1284       if (!ctx->Color.ColorLogicOpEnabled &&
1285           (ctx->Color.BlendEnabled & (1 << unit)))
1286          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1287
1288       if (!ctx->Color.ColorMask[unit][0])
1289          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1290       if (!ctx->Color.ColorMask[unit][1])
1291          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1292       if (!ctx->Color.ColorMask[unit][2])
1293          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1294
1295       /* As mentioned above, disable writes to the alpha component when the
1296        * renderbuffer is XRGB.
1297        */
1298       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1299           !ctx->Color.ColorMask[unit][3]) {
1300          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1301       }
1302    }
1303
1304    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1305                            brw->wm.surf_offset[unit] + 4,
1306                            region->bo,
1307                            surf[1] - region->bo->offset,
1308                            I915_GEM_DOMAIN_RENDER,
1309                            I915_GEM_DOMAIN_RENDER);
1310 }
1311
1312 /**
1313  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1314  */
1315 static void
1316 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1317 {
1318    struct intel_context *intel = &brw->intel;
1319    struct gl_context *ctx = &brw->intel.ctx;
1320    GLuint i;
1321
1322    /* _NEW_BUFFERS | _NEW_COLOR */
1323    /* Update surfaces for drawing buffers */
1324    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1325       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1326          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1327             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1328          } else {
1329             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1330          }
1331       }
1332    } else {
1333       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1334    }
1335    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1336 }
1337
1338 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1339    .dirty = {
1340       .mesa = (_NEW_COLOR |
1341                _NEW_BUFFERS),
1342       .brw = BRW_NEW_BATCH,
1343       .cache = 0
1344    },
1345    .emit = brw_update_renderbuffer_surfaces,
1346 };
1347
1348 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1349    .dirty = {
1350       .mesa = _NEW_BUFFERS,
1351       .brw = BRW_NEW_BATCH,
1352       .cache = 0
1353    },
1354    .emit = brw_update_renderbuffer_surfaces,
1355 };
1356
1357 /**
1358  * Construct SURFACE_STATE objects for enabled textures.
1359  */
1360 static void
1361 brw_update_texture_surfaces(struct brw_context *brw)
1362 {
1363    struct intel_context *intel = &brw->intel;
1364    struct gl_context *ctx = &intel->ctx;
1365
1366    /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
1367     * Unfortunately, we're stuck using the gl_program structs until the
1368     * ARB_fragment_program front-end gets converted to GLSL IR.  These
1369     * have the downside that SamplerUnits is split and only contains the
1370     * mappings for samplers active in that stage.
1371     */
1372    struct gl_program *vs = (struct gl_program *) brw->vertex_program;
1373    struct gl_program *fs = (struct gl_program *) brw->fragment_program;
1374
1375    unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed);
1376
1377    for (unsigned s = 0; s < num_samplers; s++) {
1378       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(s)] = 0;
1379       brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
1380
1381       if (vs->SamplersUsed & (1 << s)) {
1382          const unsigned unit = vs->SamplerUnits[s];
1383
1384          /* _NEW_TEXTURE */
1385          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1386             intel->vtbl.update_texture_surface(ctx, unit,
1387                                                brw->vs.surf_offset,
1388                                                SURF_INDEX_VS_TEXTURE(s));
1389          }
1390       }
1391
1392       if (fs->SamplersUsed & (1 << s)) {
1393          const unsigned unit = fs->SamplerUnits[s];
1394
1395          /* _NEW_TEXTURE */
1396          if (ctx->Texture.Unit[unit]._ReallyEnabled) {
1397             intel->vtbl.update_texture_surface(ctx, unit,
1398                                                brw->wm.surf_offset,
1399                                                SURF_INDEX_TEXTURE(s));
1400          }
1401       }
1402    }
1403
1404    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1405 }
1406
1407 const struct brw_tracked_state brw_texture_surfaces = {
1408    .dirty = {
1409       .mesa = _NEW_TEXTURE,
1410       .brw = BRW_NEW_BATCH |
1411              BRW_NEW_VERTEX_PROGRAM |
1412              BRW_NEW_FRAGMENT_PROGRAM,
1413       .cache = 0
1414    },
1415    .emit = brw_update_texture_surfaces,
1416 };
1417
1418 void
1419 brw_upload_ubo_surfaces(struct brw_context *brw,
1420                         struct gl_shader *shader,
1421                         uint32_t *surf_offsets)
1422 {
1423    struct gl_context *ctx = &brw->intel.ctx;
1424    struct intel_context *intel = &brw->intel;
1425
1426    if (!shader)
1427       return;
1428
1429    for (int i = 0; i < shader->NumUniformBlocks; i++) {
1430       struct gl_uniform_buffer_binding *binding;
1431       struct intel_buffer_object *intel_bo;
1432
1433       binding = &ctx->UniformBufferBindings[shader->UniformBlocks[i].Binding];
1434       intel_bo = intel_buffer_object(binding->BufferObject);
1435       drm_intel_bo *bo = intel_bufferobj_buffer(intel, intel_bo, INTEL_READ);
1436
1437       /* Because behavior for referencing outside of the binding's size in the
1438        * glBindBufferRange case is undefined, we can just bind the whole buffer
1439        * glBindBufferBase wants and be a correct implementation.
1440        */
1441       int size = bo->size - binding->Offset;
1442       size = ALIGN(size, 16) / 16; /* The interface takes a number of vec4s */
1443
1444       intel->vtbl.create_constant_surface(brw, bo, binding->Offset,
1445                                           size,
1446                                           &surf_offsets[i]);
1447    }
1448
1449    if (shader->NumUniformBlocks)
1450       brw->state.dirty.brw |= BRW_NEW_SURFACES;
1451 }
1452
1453 static void
1454 brw_upload_wm_ubo_surfaces(struct brw_context *brw)
1455 {
1456    struct gl_context *ctx = &brw->intel.ctx;
1457    /* _NEW_PROGRAM */
1458    struct gl_shader_program *prog = ctx->Shader._CurrentFragmentProgram;
1459
1460    if (!prog)
1461       return;
1462
1463    brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_FRAGMENT],
1464                            &brw->wm.surf_offset[SURF_INDEX_WM_UBO(0)]);
1465 }
1466
1467 const struct brw_tracked_state brw_wm_ubo_surfaces = {
1468    .dirty = {
1469       .mesa = (_NEW_PROGRAM |
1470                _NEW_BUFFER_OBJECT),
1471       .brw = BRW_NEW_BATCH,
1472       .cache = 0,
1473    },
1474    .emit = brw_upload_wm_ubo_surfaces,
1475 };
1476
1477 /**
1478  * Constructs the binding table for the WM surface state, which maps unit
1479  * numbers to surface state objects.
1480  */
1481 static void
1482 brw_upload_wm_binding_table(struct brw_context *brw)
1483 {
1484    struct intel_context *intel = &brw->intel;
1485    uint32_t *bind;
1486    int i;
1487
1488    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1489       intel->vtbl.create_constant_surface(brw, brw->shader_time.bo, 0,
1490                                           brw->shader_time.bo->size,
1491                                           &brw->wm.surf_offset[SURF_INDEX_WM_SHADER_TIME]);
1492    }
1493
1494    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1495     * space for the binding table.
1496     */
1497    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1498                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1499                           32, &brw->wm.bind_bo_offset);
1500
1501    /* BRW_NEW_SURFACES */
1502    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1503       bind[i] = brw->wm.surf_offset[i];
1504    }
1505
1506    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1507 }
1508
1509 const struct brw_tracked_state brw_wm_binding_table = {
1510    .dirty = {
1511       .mesa = 0,
1512       .brw = (BRW_NEW_BATCH |
1513               BRW_NEW_SURFACES),
1514       .cache = 0
1515    },
1516    .emit = brw_upload_wm_binding_table,
1517 };
1518
1519 void
1520 gen4_init_vtable_surface_functions(struct brw_context *brw)
1521 {
1522    struct intel_context *intel = &brw->intel;
1523
1524    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1525    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1526    intel->vtbl.update_null_renderbuffer_surface =
1527       brw_update_null_renderbuffer_surface;
1528    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1529 }