src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = 0,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 295       [MESA_FORMAT_XRGB8888_REV] = 0,
 296       [MESA_FORMAT_RGB888] = 0,
 297       [MESA_FORMAT_BGR888] = 0,
 298       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 299       [MESA_FORMAT_RGB565_REV] = 0,
 300       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 301       [MESA_FORMAT_ARGB4444_REV] = 0,
 302       [MESA_FORMAT_RGBA5551] = 0,
 303       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 304       [MESA_FORMAT_ARGB1555_REV] = 0,
 305       [MESA_FORMAT_AL44] = 0,
 306       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 307       [MESA_FORMAT_AL88_REV] = 0,
 308       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 309       [MESA_FORMAT_AL1616_REV] = 0,
 310       [MESA_FORMAT_RGB332] = 0,
 311       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 312       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 313       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 314       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 315       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 316       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 317       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 318       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 319       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 320       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 321       [MESA_FORMAT_RG88] = 0,
 322       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 323       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 324       [MESA_FORMAT_RG1616_REV] = 0,
 325       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 326       [MESA_FORMAT_Z24_S8] = 0,
 327       [MESA_FORMAT_S8_Z24] = 0,
 328       [MESA_FORMAT_Z16] = 0,
 329       [MESA_FORMAT_X8_Z24] = 0,
 330       [MESA_FORMAT_Z24_S8] = 0,
 331       [MESA_FORMAT_Z32] = 0,
 332       [MESA_FORMAT_S8] = 0,
 333
 334       [MESA_FORMAT_SRGB8] = 0,
 335       [MESA_FORMAT_SRGBA8] = 0,
 336       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 337       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 338       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 340       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 341       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 343
 344       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 345       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 346       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 347       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 348       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 349       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 350
 351       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 352       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 353       [MESA_FORMAT_RGB_FLOAT32] = 0,
 354       [MESA_FORMAT_RGB_FLOAT16] = 0,
 355       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 356       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 357       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 358       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 361       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 362       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 363       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 364       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 365       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 366       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 367
 368       [MESA_FORMAT_ALPHA_UINT8] = 0,
 369       [MESA_FORMAT_ALPHA_UINT16] = 0,
 370       [MESA_FORMAT_ALPHA_UINT32] = 0,
 371       [MESA_FORMAT_ALPHA_INT8] = 0,
 372       [MESA_FORMAT_ALPHA_INT16] = 0,
 373       [MESA_FORMAT_ALPHA_INT32] = 0,
 374
 375       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 376       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 377       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 378       [MESA_FORMAT_INTENSITY_INT8] = 0,
 379       [MESA_FORMAT_INTENSITY_INT16] = 0,
 380       [MESA_FORMAT_INTENSITY_INT32] = 0,
 381
 382       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 383       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 384       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 385       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 386       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 388
 389       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 390       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 395
 396       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 397       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 398       [MESA_FORMAT_RGB_INT8] = 0,
 399       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 400       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 401       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 402       [MESA_FORMAT_RGB_INT16] = 0,
 403       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 404       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 405       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 406       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 407       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 408
 409       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 410       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 411       [MESA_FORMAT_RGB_UINT8] = 0,
 412       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 413       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 414       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 415       [MESA_FORMAT_RGB_UINT16] = 0,
 416       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 417       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 418       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 419       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 420       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 421
 422       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 423       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 424       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 426       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 427       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 428       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 429       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 430       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 431       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 432       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 433
 434       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 435       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 436       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 437       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 438
 439       [MESA_FORMAT_L_LATC1] = 0,
 440       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 441       [MESA_FORMAT_LA_LATC2] = 0,
 442       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 443
 444       [MESA_FORMAT_SIGNED_A8] = 0,
 445       [MESA_FORMAT_SIGNED_L8] = 0,
 446       [MESA_FORMAT_SIGNED_AL88] = 0,
 447       [MESA_FORMAT_SIGNED_I8] = 0,
 448       [MESA_FORMAT_SIGNED_A16] = 0,
 449       [MESA_FORMAT_SIGNED_L16] = 0,
 450       [MESA_FORMAT_SIGNED_AL1616] = 0,
 451       [MESA_FORMAT_SIGNED_I16] = 0,
 452
 453       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 454       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 455
 456       [MESA_FORMAT_Z32_FLOAT] = 0,
 457       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 458    };
 459    assert(mesa_format < MESA_FORMAT_COUNT);
 460    return table[mesa_format];
 461 }
 462
 463 void
 464 brw_init_surface_formats(struct brw_context *brw)
 465 {
 466    struct intel_context *intel = &brw->intel;
 467    struct gl_context *ctx = &intel->ctx;
 468    int gen;
 469    gl_format format;
 470
 471    gen = intel->gen * 10;
 472    if (intel->is_g4x)
 473       gen += 5;
 474
 475    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 476       uint32_t texture, render;
 477       const struct surface_format_info *rinfo, *tinfo;
 478       bool is_integer = _mesa_is_format_integer_color(format);
 479
 480       render = texture = brw_format_for_mesa_format(format);
 481       tinfo = &surface_formats[texture];
 482
 483       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 484        * it.
 485        */
 486       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 487          continue;
 488
 489       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 490          ctx->TextureFormatSupported[format] = true;
 491
 492       /* Re-map some render target formats to make them supported when they
 493        * wouldn't be using their format for texturing.
 494        */
 495       switch (render) {
 496          /* For these formats, we just need to read/write the first
 497           * channel into R, which is to say that we just treat them as
 498           * GL_RED.
 499           */
 500       case BRW_SURFACEFORMAT_I32_FLOAT:
 501       case BRW_SURFACEFORMAT_L32_FLOAT:
 502          render = BRW_SURFACEFORMAT_R32_FLOAT;
 503          break;
 504       case BRW_SURFACEFORMAT_I16_FLOAT:
 505       case BRW_SURFACEFORMAT_L16_FLOAT:
 506          render = BRW_SURFACEFORMAT_R16_FLOAT;
 507          break;
 508       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 509          /* XRGB is handled as ARGB because the chips in this family
 510           * cannot render to XRGB targets.  This means that we have to
 511           * mask writes to alpha (ala glColorMask) and reconfigure the
 512           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 513           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 514           * used.
 515           */
 516          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 517          break;
 518       }
 519
 520       rinfo = &surface_formats[render];
 521
 522       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 523        * integer, so we don't need hardware support for blending on it.  Other
 524        * than that, GL in general requires alpha blending for render targets,
 525        * even though we don't support it for some formats.
 526        *
 527        * We don't currently support rendering to SNORM textures because some of
 528        * the ARB_color_buffer_float clamping is broken for it
 529        * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
 530        */
 531       if (gen >= rinfo->render_target &&
 532           (gen >= rinfo->alpha_blend || is_integer) &&
 533           _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
 534          brw->render_target_format[format] = render;
 535          brw->format_supported_as_render_target[format] = true;
 536       }
 537    }
 538
 539    /* We will check this table for FBO completeness, but the surface format
 540     * table above only covered color rendering.
 541     */
 542    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 543    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 544    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 545    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 546    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 547    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 548
 549    /* We remap depth formats to a supported texturing format in
 550     * translate_tex_format().
 551     */
 552    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 553    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 554    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 555    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 556 }
 557
 558 bool
 559 brw_render_target_supported(struct intel_context *intel, gl_format format)
 560 {
 561    struct brw_context *brw = brw_context(&intel->ctx);
 562    /* Not exactly true, as some of those formats are not renderable.
 563     * But at least we know how to translate them.
 564     */
 565    return brw->format_supported_as_render_target[format];
 566 }
 567
 568 GLuint
 569 translate_tex_format(gl_format mesa_format,
 570                      GLenum internal_format,
 571                      GLenum depth_mode,
 572                      GLenum srgb_decode)
 573 {
 574    switch( mesa_format ) {
 575
 576    case MESA_FORMAT_Z16:
 577       return BRW_SURFACEFORMAT_I16_UNORM;
 578
 579    case MESA_FORMAT_S8_Z24:
 580    case MESA_FORMAT_X8_Z24:
 581       return BRW_SURFACEFORMAT_I24X8_UNORM;
 582
 583    case MESA_FORMAT_Z32_FLOAT:
 584       return BRW_SURFACEFORMAT_I32_FLOAT;
 585
 586    case MESA_FORMAT_Z32_FLOAT_X24S8:
 587       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 588
 589    case MESA_FORMAT_SARGB8:
 590    case MESA_FORMAT_SLA8:
 591    case MESA_FORMAT_SL8:
 592       if (srgb_decode == GL_DECODE_EXT)
 593          return brw_format_for_mesa_format(mesa_format);
 594       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 595          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 596
 597    case MESA_FORMAT_RGBA8888_REV:
 598       /* This format is not renderable? */
 599       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 600
 601    case MESA_FORMAT_RGBA_FLOAT32:
 602       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 603        * assertion below.
 604        */
 605       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 606
 607    default:
 608       assert(brw_format_for_mesa_format(mesa_format) != 0);
 609       return brw_format_for_mesa_format(mesa_format);
 610    }
 611 }
 612
 613 static uint32_t
 614 brw_get_surface_tiling_bits(uint32_t tiling)
 615 {
 616    switch (tiling) {
 617    case I915_TILING_X:
 618       return BRW_SURFACE_TILED;
 619    case I915_TILING_Y:
 620       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 621    default:
 622       return 0;
 623    }
 624 }
 625
 626 static void
 627 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 628 {
 629    struct brw_context *brw = brw_context(ctx);
 630    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 631    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 632    struct intel_mipmap_tree *mt = intelObj->mt;
 633    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 634    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 635    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 636    uint32_t *surf;
 637    int width, height, depth;
 638
 639    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 640
 641    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 642                           6 * 4, 32, &brw->bind.surf_offset[surf_index]);
 643
 644    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 645               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 646               BRW_SURFACE_CUBEFACE_ENABLES |
 647               (translate_tex_format(mt->format,
 648                                     firstImage->InternalFormat,
 649                                     sampler->DepthMode,
 650                                     sampler->sRGBDecode) <<
 651                BRW_SURFACE_FORMAT_SHIFT));
 652
 653    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 654
 655    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 656               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 657               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 658
 659    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 660               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 661               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 662               BRW_SURFACE_PITCH_SHIFT);
 663
 664    surf[4] = 0;
 665
 666    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 667
 668    /* Emit relocation to surface contents */
 669    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 670                            brw->bind.surf_offset[surf_index] + 4,
 671                            intelObj->mt->region->bo, 0,
 672                            I915_GEM_DOMAIN_SAMPLER, 0);
 673 }
 674
 675 /**
 676  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 677  * read from this buffer with Data Port Read instructions/messages.
 678  */
 679 void
 680 brw_create_constant_surface(struct brw_context *brw,
 681                             drm_intel_bo *bo,
 682                             int width,
 683                             uint32_t *out_offset)
 684 {
 685    struct intel_context *intel = &brw->intel;
 686    const GLint w = width - 1;
 687    uint32_t *surf;
 688
 689    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 690                           6 * 4, 32, out_offset);
 691
 692    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 693               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 694               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 695
 696    if (intel->gen >= 6)
 697       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 698
 699    surf[1] = bo->offset; /* reloc */
 700
 701    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 702               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 703
 704    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 705               (width * 16 - 1) << BRW_SURFACE_PITCH_SHIFT);
 706
 707    surf[4] = 0;
 708    surf[5] = 0;
 709
 710    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 711     * bspec ("Data Cache") says that the data cache does not exist as
 712     * a separate cache and is just the sampler cache.
 713     */
 714    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 715                            *out_offset + 4,
 716                            bo, 0,
 717                            I915_GEM_DOMAIN_SAMPLER, 0);
 718 }
 719
 720 /**
 721  * Set up a binding table entry for use by stream output logic (transform
 722  * feedback).
 723  *
 724  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 725  */
 726 void
 727 brw_update_sol_surface(struct brw_context *brw,
 728                        struct gl_buffer_object *buffer_obj,
 729                        uint32_t *out_offset, unsigned num_vector_components,
 730                        unsigned stride_dwords, unsigned offset_dwords)
 731 {
 732    drm_intel_bo *bo = intel_buffer_object(buffer_obj)->buffer;
 733    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 734                                     out_offset);
 735    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 736    uint32_t offset_bytes = 4 * offset_dwords;
 737    size_t size_dwords = buffer_obj->Size / 4;
 738    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 739
 740    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 741     * too big to map using a single binding table entry?
 742     */
 743    assert((size_dwords - offset_dwords) / stride_dwords
 744           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 745
 746    if (size_dwords > offset_dwords + num_vector_components) {
 747       /* There is room for at least 1 transform feedback output in the buffer.
 748        * Compute the number of additional transform feedback outputs the
 749        * buffer has room for.
 750        */
 751       buffer_size_minus_1 =
 752          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 753    } else {
 754       /* There isn't even room for a single transform feedback output in the
 755        * buffer.  We can't configure the binding table entry to prevent output
 756        * entirely; we'll have to rely on the geometry shader to detect
 757        * overflow.  But to minimize the damage in case of a bug, set up the
 758        * binding table entry to just allow a single output.
 759        */
 760       buffer_size_minus_1 = 0;
 761    }
 762    width = buffer_size_minus_1 & 0x7f;
 763    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 764    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 765
 766    switch (num_vector_components) {
 767    case 1:
 768       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 769       break;
 770    case 2:
 771       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 772       break;
 773    case 3:
 774       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 775       break;
 776    case 4:
 777       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 778       break;
 779    default:
 780       assert(!"Invalid vector size for transform feedback output");
 781       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 782       break;
 783    }
 784
 785    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 786       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 787       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 788       BRW_SURFACE_RC_READ_WRITE;
 789    surf[1] = bo->offset + offset_bytes; /* reloc */
 790    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 791               height << BRW_SURFACE_HEIGHT_SHIFT);
 792    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 793               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 794    surf[4] = 0;
 795    surf[5] = 0;
 796
 797    /* Emit relocation to surface contents. */
 798    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 799                            *out_offset + 4,
 800                            bo, offset_bytes,
 801                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 802 }
 803
 804 /* Creates a new WM constant buffer reflecting the current fragment program's
 805  * constants, if needed by the fragment program.
 806  *
 807  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 808  * state atom.
 809  */
 810 static void
 811 brw_upload_wm_pull_constants(struct brw_context *brw)
 812 {
 813    struct gl_context *ctx = &brw->intel.ctx;
 814    struct intel_context *intel = &brw->intel;
 815    /* BRW_NEW_FRAGMENT_PROGRAM */
 816    struct brw_fragment_program *fp =
 817       (struct brw_fragment_program *) brw->fragment_program;
 818    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 819    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 820    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 821    float *constants;
 822    unsigned int i;
 823
 824    _mesa_load_state_parameters(ctx, params);
 825
 826    /* CACHE_NEW_WM_PROG */
 827    if (brw->wm.prog_data->nr_pull_params == 0) {
 828       if (brw->wm.const_bo) {
 829          drm_intel_bo_unreference(brw->wm.const_bo);
 830          brw->wm.const_bo = NULL;
 831          brw->bind.surf_offset[surf_index] = 0;
 832          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 833       }
 834       return;
 835    }
 836
 837    drm_intel_bo_unreference(brw->wm.const_bo);
 838    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 839                                          size, 64);
 840
 841    /* _NEW_PROGRAM_CONSTANTS */
 842    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 843    constants = brw->wm.const_bo->virtual;
 844    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 845       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 846                                    brw->wm.prog_data->pull_param[i]);
 847    }
 848    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 849
 850    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 851                                        params->NumParameters,
 852                                        &brw->bind.surf_offset[surf_index]);
 853
 854    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 855 }
 856
 857 const struct brw_tracked_state brw_wm_pull_constants = {
 858    .dirty = {
 859       .mesa = (_NEW_PROGRAM_CONSTANTS),
 860       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 861       .cache = CACHE_NEW_WM_PROG,
 862    },
 863    .emit = brw_upload_wm_pull_constants,
 864 };
 865
 866 static void
 867 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 868 {
 869    struct intel_context *intel = &brw->intel;
 870    uint32_t *surf;
 871
 872    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 873                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 874
 875    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 876               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 877    if (intel->gen < 6) {
 878       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 879                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 880                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 881                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 882    }
 883    surf[1] = 0;
 884    surf[2] = 0;
 885    surf[3] = 0;
 886    surf[4] = 0;
 887    surf[5] = 0;
 888 }
 889
 890 /**
 891  * Sets up a surface state structure to point at the given region.
 892  * While it is only used for the front/back buffer currently, it should be
 893  * usable for further buffers when doing ARB_draw_buffer support.
 894  */
 895 static void
 896 brw_update_renderbuffer_surface(struct brw_context *brw,
 897                                 struct gl_renderbuffer *rb,
 898                                 unsigned int unit)
 899 {
 900    struct intel_context *intel = &brw->intel;
 901    struct gl_context *ctx = &intel->ctx;
 902    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 903    struct intel_mipmap_tree *mt = irb->mt;
 904    struct intel_region *region = irb->mt->region;
 905    uint32_t *surf;
 906    uint32_t tile_x, tile_y;
 907    uint32_t format = 0;
 908
 909    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 910                           6 * 4, 32, &brw->bind.surf_offset[unit]);
 911
 912    switch (irb->Base.Format) {
 913    case MESA_FORMAT_SARGB8:
 914       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 915          surfaces to the blend/update as sRGB */
 916       if (ctx->Color.sRGBEnabled)
 917          format = brw_format_for_mesa_format(irb->Base.Format);
 918       else
 919          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 920       break;
 921    default:
 922       format = brw->render_target_format[irb->Base.Format];
 923       if (unlikely(!brw->format_supported_as_render_target[irb->Base.Format])) {
 924          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 925                        __FUNCTION__, _mesa_get_format_name(irb->Base.Format));
 926       }
 927       break;
 928    }
 929
 930    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 931               format << BRW_SURFACE_FORMAT_SHIFT);
 932
 933    /* reloc */
 934    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 935               region->bo->offset);
 936
 937    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 938               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 939
 940    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 941               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 942
 943    surf[4] = 0;
 944
 945    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 946    /* Note that the low bits of these fields are missing, so
 947     * there's the possibility of getting in trouble.
 948     */
 949    assert(tile_x % 4 == 0);
 950    assert(tile_y % 2 == 0);
 951    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 952               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 953               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 954
 955    if (intel->gen < 6) {
 956       /* _NEW_COLOR */
 957       if (!ctx->Color.ColorLogicOpEnabled &&
 958           (ctx->Color.BlendEnabled & (1 << unit)))
 959          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
 960
 961       if (!ctx->Color.ColorMask[unit][0])
 962          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
 963       if (!ctx->Color.ColorMask[unit][1])
 964          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
 965       if (!ctx->Color.ColorMask[unit][2])
 966          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
 967
 968       /* As mentioned above, disable writes to the alpha component when the
 969        * renderbuffer is XRGB.
 970        */
 971       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
 972           !ctx->Color.ColorMask[unit][3]) {
 973          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
 974       }
 975    }
 976
 977    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 978                            brw->bind.surf_offset[unit] + 4,
 979                            region->bo,
 980                            surf[1] - region->bo->offset,
 981                            I915_GEM_DOMAIN_RENDER,
 982                            I915_GEM_DOMAIN_RENDER);
 983 }
 984
 985 /**
 986  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
 987  */
 988 static void
 989 brw_update_renderbuffer_surfaces(struct brw_context *brw)
 990 {
 991    struct intel_context *intel = &brw->intel;
 992    struct gl_context *ctx = &brw->intel.ctx;
 993    GLuint i;
 994
 995    /* _NEW_BUFFERS | _NEW_COLOR */
 996    /* Update surfaces for drawing buffers */
 997    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 998       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 999          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1000             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1001          } else {
1002             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1003          }
1004       }
1005    } else {
1006       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1007    }
1008    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1009 }
1010
1011 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1012    .dirty = {
1013       .mesa = (_NEW_COLOR |
1014                _NEW_BUFFERS),
1015       .brw = BRW_NEW_BATCH,
1016       .cache = 0
1017    },
1018    .emit = brw_update_renderbuffer_surfaces,
1019 };
1020
1021 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1022    .dirty = {
1023       .mesa = _NEW_BUFFERS,
1024       .brw = BRW_NEW_BATCH,
1025       .cache = 0
1026    },
1027    .emit = brw_update_renderbuffer_surfaces,
1028 };
1029
1030 /**
1031  * Construct SURFACE_STATE objects for enabled textures.
1032  */
1033 static void
1034 brw_update_texture_surfaces(struct brw_context *brw)
1035 {
1036    struct gl_context *ctx = &brw->intel.ctx;
1037
1038    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1039       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1040       const GLuint surf = SURF_INDEX_TEXTURE(i);
1041
1042       /* _NEW_TEXTURE */
1043       if (texUnit->_ReallyEnabled) {
1044          brw->intel.vtbl.update_texture_surface(ctx, i);
1045       } else {
1046          brw->bind.surf_offset[surf] = 0;
1047       }
1048    }
1049
1050    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1051 }
1052
1053 const struct brw_tracked_state brw_texture_surfaces = {
1054    .dirty = {
1055       .mesa = _NEW_TEXTURE,
1056       .brw = BRW_NEW_BATCH,
1057       .cache = 0
1058    },
1059    .emit = brw_update_texture_surfaces,
1060 };
1061
1062 /**
1063  * Constructs the binding table for the WM surface state, which maps unit
1064  * numbers to surface state objects.
1065  */
1066 static void
1067 brw_upload_binding_table(struct brw_context *brw)
1068 {
1069    uint32_t *bind;
1070    int i;
1071
1072    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1073     * space for the binding table.
1074     */
1075    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1076                           sizeof(uint32_t) * BRW_MAX_SURFACES,
1077                           32, &brw->bind.bo_offset);
1078
1079    /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */
1080    for (i = 0; i < BRW_MAX_SURFACES; i++) {
1081       bind[i] = brw->bind.surf_offset[i];
1082    }
1083
1084    brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
1085    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1086 }
1087
1088 const struct brw_tracked_state brw_binding_table = {
1089    .dirty = {
1090       .mesa = 0,
1091       .brw = (BRW_NEW_BATCH |
1092               BRW_NEW_VS_CONSTBUF |
1093               BRW_NEW_SURFACES),
1094       .cache = 0
1095    },
1096    .emit = brw_upload_binding_table,
1097 };
1098
1099 void
1100 gen4_init_vtable_surface_functions(struct brw_context *brw)
1101 {
1102    struct intel_context *intel = &brw->intel;
1103
1104    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1105    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1106    intel->vtbl.update_null_renderbuffer_surface =
1107       brw_update_null_renderbuffer_surface;
1108    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1109 }