src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/samplerobj.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41 #include "intel_buffer_objects.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46 #include "brw_wm.h"
  47
  48 GLuint
  49 translate_tex_target(GLenum target)
  50 {
  51    switch (target) {
  52    case GL_TEXTURE_1D:
  53    case GL_TEXTURE_1D_ARRAY_EXT:
  54       return BRW_SURFACE_1D;
  55
  56    case GL_TEXTURE_RECTANGLE_NV:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_2D:
  60    case GL_TEXTURE_2D_ARRAY_EXT:
  61    case GL_TEXTURE_EXTERNAL_OES:
  62       return BRW_SURFACE_2D;
  63
  64    case GL_TEXTURE_3D:
  65       return BRW_SURFACE_3D;
  66
  67    case GL_TEXTURE_CUBE_MAP:
  68       return BRW_SURFACE_CUBE;
  69
  70    default:
  71       assert(0);
  72       return 0;
  73    }
  74 }
  75
  76 struct surface_format_info {
  77    bool exists;
  78    int sampling;
  79    int filtering;
  80    int shadow_compare;
  81    int chroma_key;
  82    int render_target;
  83    int alpha_blend;
  84    int input_vb;
  85    int streamed_output_vb;
  86    int color_processing;
  87 };
  88
  89 /* This macro allows us to write the table almost as it appears in the PRM,
  90  * while restructuring it to turn it into the C code we want.
  91  */
  92 #define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, sf) \
  93    [sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color },
  94
  95 #define Y 0
  96 #define x 999
  97 /**
  98  * This is the table of support for surface (texture, renderbuffer, and vertex
  99  * buffer, but not depthbuffer) formats across the various hardware generations.
 100  *
 101  * The table is formatted to match the documentation, except that the docs have
 102  * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever".  To put
 103  * it in our table, here's the mapping:
 104  *
 105  * Y*: 45
 106  * Y+: 45 (g45/gm45)
 107  * Y~: 50 (gen5)
 108  * Y^: 60 (gen6)
 109  * Y#: 70 (gen7)
 110  *
 111  * See page 88 of the Sandybridge PRM VOL4_Part1 PDF.
 112  */
 113 const struct surface_format_info surface_formats[] = {
 114 /* smpl filt shad CK  RT  AB  VB  SO  color */
 115    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT)
 116    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_SINT)
 117    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32A32_UINT)
 118    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM)
 119    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM)
 120    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64_FLOAT)
 121    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT)
 122    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED)
 123    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED)
 124    SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_FLOAT)
 125    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_SINT)
 126    SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32B32_UINT)
 127    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_UNORM)
 128    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SNORM)
 129    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_SSCALED)
 130    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32B32_USCALED)
 131    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM)
 132    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM)
 133    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SINT)
 134    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_UINT)
 135    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT)
 136    SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_FLOAT)
 137    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_SINT)
 138    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32G32_UINT)
 139    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS)
 140    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT)
 141    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32A32_FLOAT)
 142    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_UNORM)
 143    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SNORM)
 144    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64_FLOAT)
 145    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM)
 146    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT)
 147    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32X32_FLOAT)
 148    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32X32_FLOAT)
 149    SF( Y, 50,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32X32_FLOAT)
 150    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED)
 151    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED)
 152    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_SSCALED)
 153    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32G32_USCALED)
 154    SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM)
 155    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB)
 156 /* smpl filt shad CK  RT  AB  VB  SO  color */
 157    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM)
 158    SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB)
 159    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10A2_UINT)
 160    SF( Y,  Y,  x,  x,  x,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM)
 161    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM)
 162    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB)
 163    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM)
 164    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SINT)
 165    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_UINT)
 166    SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UNORM)
 167    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SNORM)
 168    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SINT)
 169    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_UINT)
 170    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_FLOAT)
 171    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM)
 172    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB)
 173    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R11G11B10_FLOAT)
 174    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_SINT)
 175    SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_UINT)
 176    SF( Y, 50,  Y,  x,  Y,  Y,  Y,  Y,  x, BRW_SURFACEFORMAT_R32_FLOAT)
 177    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS)
 178    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT)
 179    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_UNORM)
 180    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I24X8_UNORM)
 181    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L24X8_UNORM)
 182    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A24X8_UNORM)
 183    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I32_FLOAT)
 184    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L32_FLOAT)
 185    SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A32_FLOAT)
 186    SF( Y,  Y,  x,  Y,  x,  x,  x,  x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM)
 187    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB)
 188    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM)
 189    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB)
 190    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP)
 191    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM)
 192    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16A16_FLOAT)
 193    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_UNORM)
 194    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SNORM)
 195 /* smpl filt shad CK  RT  AB  VB  SO  color */
 196    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED)
 197    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED)
 198    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED)
 199    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_SSCALED)
 200    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16_USCALED)
 201    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_SSCALED)
 202    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R32_USCALED)
 203    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM)
 204    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB)
 205    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM)
 206    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB)
 207    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM)
 208    SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB)
 209    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UNORM)
 210    SF( Y,  Y,  x,  Y,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SNORM)
 211    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SINT)
 212    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_UINT)
 213    SF( Y,  Y,  Y,  x,  Y, 45,  Y,  x, 70, BRW_SURFACEFORMAT_R16_UNORM)
 214    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SNORM)
 215    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SINT)
 216    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_UINT)
 217    SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R16_FLOAT)
 218    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_UNORM)
 219    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_UNORM)
 220    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_UNORM)
 221    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM)
 222    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I16_FLOAT)
 223    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L16_FLOAT)
 224    SF( Y,  Y,  Y,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A16_FLOAT)
 225    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB)
 226    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM)
 227    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM)
 228    SF( x,  x,  x,  x,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB)
 229    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_SSCALED)
 230    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8_USCALED)
 231 /* smpl filt shad CK  RT  AB  VB  SO  color */
 232    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_SSCALED)
 233    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16_USCALED)
 234    SF( Y,  Y,  x, 45,  Y,  Y,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UNORM)
 235    SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SNORM)
 236    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SINT)
 237    SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_UINT)
 238    SF( Y,  Y,  x,  Y,  Y,  Y,  x,  x,  x, BRW_SURFACEFORMAT_A8_UNORM)
 239    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_I8_UNORM)
 240    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM)
 241    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_P4A4_UNORM)
 242    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_A4P4_UNORM)
 243    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_SSCALED)
 244    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8_USCALED)
 245    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_L8_UNORM_SRGB)
 246    SF(45, 45,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB)
 247    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_R1_UINT)
 248    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL)
 249    SF( Y,  Y,  x,  Y,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY)
 250    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM)
 251    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM)
 252    SF( Y,  Y,  x,  Y,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM)
 253    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_UNORM)
 254    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_UNORM)
 255    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB)
 256    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB)
 257    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB)
 258    SF( Y,  x,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_MONO8)
 259    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV)
 260    SF( Y,  Y,  x,  x,  Y,  x,  x,  x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY)
 261    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_DXT1_RGB)
 262 /* smpl filt shad CK  RT  AB  VB  SO  color */
 263    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_FXT1)
 264    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_UNORM)
 265    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SNORM)
 266    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_SSCALED)
 267    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R8G8B8_USCALED)
 268    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT)
 269    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
 270    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC4_SNORM)
 271    SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x, BRW_SURFACEFORMAT_BC5_SNORM)
 272    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
 273    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
 274    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
 275    SF( x,  x,  x,  x,  x,  x,  Y,  x,  x, BRW_SURFACEFORMAT_R16G16B16_USCALED)
 276 };
 277 #undef x
 278 #undef Y
 279
 280 uint32_t
 281 brw_format_for_mesa_format(gl_format mesa_format)
 282 {
 283    /* This table is ordered according to the enum ordering in formats.h.  We do
 284     * expect that enum to be extended without our explicit initialization
 285     * staying in sync, so we initialize to 0 even though
 286     * BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to also be 0.
 287     */
 288    static const uint32_t table[MESA_FORMAT_COUNT] =
 289    {
 290       [MESA_FORMAT_RGBA8888] = 0,
 291       [MESA_FORMAT_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM,
 292       [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
 293       [MESA_FORMAT_ARGB8888_REV] = 0,
 294       [MESA_FORMAT_RGBX8888] = 0,
 295       [MESA_FORMAT_RGBX8888_REV] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM,
 296       [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
 297       [MESA_FORMAT_XRGB8888_REV] = 0,
 298       [MESA_FORMAT_RGB888] = 0,
 299       [MESA_FORMAT_BGR888] = 0,
 300       [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
 301       [MESA_FORMAT_RGB565_REV] = 0,
 302       [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
 303       [MESA_FORMAT_ARGB4444_REV] = 0,
 304       [MESA_FORMAT_RGBA5551] = 0,
 305       [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
 306       [MESA_FORMAT_ARGB1555_REV] = 0,
 307       [MESA_FORMAT_AL44] = 0,
 308       [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
 309       [MESA_FORMAT_AL88_REV] = 0,
 310       [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
 311       [MESA_FORMAT_AL1616_REV] = 0,
 312       [MESA_FORMAT_RGB332] = 0,
 313       [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
 314       [MESA_FORMAT_A16] = BRW_SURFACEFORMAT_A16_UNORM,
 315       [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
 316       [MESA_FORMAT_L16] = BRW_SURFACEFORMAT_L16_UNORM,
 317       [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
 318       [MESA_FORMAT_I16] = BRW_SURFACEFORMAT_I16_UNORM,
 319       [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
 320       [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
 321       [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
 322       [MESA_FORMAT_GR88] = BRW_SURFACEFORMAT_R8G8_UNORM,
 323       [MESA_FORMAT_RG88] = 0,
 324       [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
 325       [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
 326       [MESA_FORMAT_RG1616_REV] = 0,
 327       [MESA_FORMAT_ARGB2101010] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM,
 328       [MESA_FORMAT_Z24_S8] = 0,
 329       [MESA_FORMAT_S8_Z24] = 0,
 330       [MESA_FORMAT_Z16] = 0,
 331       [MESA_FORMAT_X8_Z24] = 0,
 332       [MESA_FORMAT_Z24_X8] = 0,
 333       [MESA_FORMAT_Z32] = 0,
 334       [MESA_FORMAT_S8] = 0,
 335
 336       [MESA_FORMAT_SRGB8] = 0,
 337       [MESA_FORMAT_SRGBA8] = 0,
 338       [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
 339       [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
 340       [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
 341       [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB,
 342       [MESA_FORMAT_SRGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
 343       [MESA_FORMAT_SRGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB,
 344       [MESA_FORMAT_SRGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB,
 345
 346       [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
 347       [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
 348       [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
 349       [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
 350       [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
 351       [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
 352
 353       [MESA_FORMAT_RGBA_FLOAT32] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT,
 354       [MESA_FORMAT_RGBA_FLOAT16] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
 355       [MESA_FORMAT_RGB_FLOAT32] = 0,
 356       [MESA_FORMAT_RGB_FLOAT16] = 0,
 357       [MESA_FORMAT_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_A32_FLOAT,
 358       [MESA_FORMAT_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_A16_FLOAT,
 359       [MESA_FORMAT_LUMINANCE_FLOAT32] = BRW_SURFACEFORMAT_L32_FLOAT,
 360       [MESA_FORMAT_LUMINANCE_FLOAT16] = BRW_SURFACEFORMAT_L16_FLOAT,
 361       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32] = BRW_SURFACEFORMAT_L32A32_FLOAT,
 362       [MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16] = BRW_SURFACEFORMAT_L16A16_FLOAT,
 363       [MESA_FORMAT_INTENSITY_FLOAT32] = BRW_SURFACEFORMAT_I32_FLOAT,
 364       [MESA_FORMAT_INTENSITY_FLOAT16] = BRW_SURFACEFORMAT_I16_FLOAT,
 365       [MESA_FORMAT_R_FLOAT32] = BRW_SURFACEFORMAT_R32_FLOAT,
 366       [MESA_FORMAT_R_FLOAT16] = BRW_SURFACEFORMAT_R16_FLOAT,
 367       [MESA_FORMAT_RG_FLOAT32] = BRW_SURFACEFORMAT_R32G32_FLOAT,
 368       [MESA_FORMAT_RG_FLOAT16] = BRW_SURFACEFORMAT_R16G16_FLOAT,
 369
 370       [MESA_FORMAT_ALPHA_UINT8] = 0,
 371       [MESA_FORMAT_ALPHA_UINT16] = 0,
 372       [MESA_FORMAT_ALPHA_UINT32] = 0,
 373       [MESA_FORMAT_ALPHA_INT8] = 0,
 374       [MESA_FORMAT_ALPHA_INT16] = 0,
 375       [MESA_FORMAT_ALPHA_INT32] = 0,
 376
 377       [MESA_FORMAT_INTENSITY_UINT8] = 0,
 378       [MESA_FORMAT_INTENSITY_UINT16] = 0,
 379       [MESA_FORMAT_INTENSITY_UINT32] = 0,
 380       [MESA_FORMAT_INTENSITY_INT8] = 0,
 381       [MESA_FORMAT_INTENSITY_INT16] = 0,
 382       [MESA_FORMAT_INTENSITY_INT32] = 0,
 383
 384       [MESA_FORMAT_LUMINANCE_UINT8] = 0,
 385       [MESA_FORMAT_LUMINANCE_UINT16] = 0,
 386       [MESA_FORMAT_LUMINANCE_UINT32] = 0,
 387       [MESA_FORMAT_LUMINANCE_INT8] = 0,
 388       [MESA_FORMAT_LUMINANCE_INT16] = 0,
 389       [MESA_FORMAT_LUMINANCE_INT32] = 0,
 390
 391       [MESA_FORMAT_LUMINANCE_ALPHA_UINT8] = 0,
 392       [MESA_FORMAT_LUMINANCE_ALPHA_UINT16] = 0,
 393       [MESA_FORMAT_LUMINANCE_ALPHA_UINT32] = 0,
 394       [MESA_FORMAT_LUMINANCE_ALPHA_INT8] = 0,
 395       [MESA_FORMAT_LUMINANCE_ALPHA_INT16] = 0,
 396       [MESA_FORMAT_LUMINANCE_ALPHA_INT32] = 0,
 397
 398       [MESA_FORMAT_R_INT8] = BRW_SURFACEFORMAT_R8_SINT,
 399       [MESA_FORMAT_RG_INT8] = BRW_SURFACEFORMAT_R8G8_SINT,
 400       [MESA_FORMAT_RGB_INT8] = 0,
 401       [MESA_FORMAT_RGBA_INT8] = BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 402       [MESA_FORMAT_R_INT16] = BRW_SURFACEFORMAT_R16_SINT,
 403       [MESA_FORMAT_RG_INT16] = BRW_SURFACEFORMAT_R16G16_SINT,
 404       [MESA_FORMAT_RGB_INT16] = 0,
 405       [MESA_FORMAT_RGBA_INT16] = BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 406       [MESA_FORMAT_R_INT32] = BRW_SURFACEFORMAT_R32_SINT,
 407       [MESA_FORMAT_RG_INT32] = BRW_SURFACEFORMAT_R32G32_SINT,
 408       [MESA_FORMAT_RGB_INT32] = BRW_SURFACEFORMAT_R32G32B32_SINT,
 409       [MESA_FORMAT_RGBA_INT32] = BRW_SURFACEFORMAT_R32G32B32A32_SINT,
 410
 411       [MESA_FORMAT_R_UINT8] = BRW_SURFACEFORMAT_R8_UINT,
 412       [MESA_FORMAT_RG_UINT8] = BRW_SURFACEFORMAT_R8G8_UINT,
 413       [MESA_FORMAT_RGB_UINT8] = 0,
 414       [MESA_FORMAT_RGBA_UINT8] = BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 415       [MESA_FORMAT_R_UINT16] = BRW_SURFACEFORMAT_R16_UINT,
 416       [MESA_FORMAT_RG_UINT16] = BRW_SURFACEFORMAT_R16G16_UINT,
 417       [MESA_FORMAT_RGB_UINT16] = 0,
 418       [MESA_FORMAT_RGBA_UINT16] = BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 419       [MESA_FORMAT_R_UINT32] = BRW_SURFACEFORMAT_R32_UINT,
 420       [MESA_FORMAT_RG_UINT32] = BRW_SURFACEFORMAT_R32G32_UINT,
 421       [MESA_FORMAT_RGB_UINT32] = BRW_SURFACEFORMAT_R32G32B32_UINT,
 422       [MESA_FORMAT_RGBA_UINT32] = BRW_SURFACEFORMAT_R32G32B32A32_UINT,
 423
 424       [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
 425       [MESA_FORMAT_SIGNED_R8] = BRW_SURFACEFORMAT_R8_SNORM,
 426       [MESA_FORMAT_SIGNED_RG88_REV] = BRW_SURFACEFORMAT_R8G8_SNORM,
 427       [MESA_FORMAT_SIGNED_RGBX8888] = 0,
 428       [MESA_FORMAT_SIGNED_RGBA8888] = 0,
 429       [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
 430       [MESA_FORMAT_SIGNED_R16] = BRW_SURFACEFORMAT_R16_SNORM,
 431       [MESA_FORMAT_SIGNED_GR1616] = BRW_SURFACEFORMAT_R16G16_SNORM,
 432       [MESA_FORMAT_SIGNED_RGB_16] = 0,
 433       [MESA_FORMAT_SIGNED_RGBA_16] = 0,
 434       [MESA_FORMAT_RGBA_16] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM,
 435
 436       [MESA_FORMAT_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_UNORM,
 437       [MESA_FORMAT_SIGNED_RED_RGTC1] = BRW_SURFACEFORMAT_BC4_SNORM,
 438       [MESA_FORMAT_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_UNORM,
 439       [MESA_FORMAT_SIGNED_RG_RGTC2] = BRW_SURFACEFORMAT_BC5_SNORM,
 440
 441       [MESA_FORMAT_L_LATC1] = 0,
 442       [MESA_FORMAT_SIGNED_L_LATC1] = 0,
 443       [MESA_FORMAT_LA_LATC2] = 0,
 444       [MESA_FORMAT_SIGNED_LA_LATC2] = 0,
 445
 446       [MESA_FORMAT_SIGNED_A8] = 0,
 447       [MESA_FORMAT_SIGNED_L8] = 0,
 448       [MESA_FORMAT_SIGNED_AL88] = 0,
 449       [MESA_FORMAT_SIGNED_I8] = 0,
 450       [MESA_FORMAT_SIGNED_A16] = 0,
 451       [MESA_FORMAT_SIGNED_L16] = 0,
 452       [MESA_FORMAT_SIGNED_AL1616] = 0,
 453       [MESA_FORMAT_SIGNED_I16] = 0,
 454
 455       [MESA_FORMAT_RGB9_E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP,
 456       [MESA_FORMAT_R11_G11_B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT,
 457
 458       [MESA_FORMAT_Z32_FLOAT] = 0,
 459       [MESA_FORMAT_Z32_FLOAT_X24S8] = 0,
 460    };
 461    assert(mesa_format < MESA_FORMAT_COUNT);
 462    return table[mesa_format];
 463 }
 464
 465 void
 466 brw_init_surface_formats(struct brw_context *brw)
 467 {
 468    struct intel_context *intel = &brw->intel;
 469    struct gl_context *ctx = &intel->ctx;
 470    int gen;
 471    gl_format format;
 472
 473    gen = intel->gen * 10;
 474    if (intel->is_g4x)
 475       gen += 5;
 476
 477    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 478       uint32_t texture, render;
 479       const struct surface_format_info *rinfo, *tinfo;
 480       bool is_integer = _mesa_is_format_integer_color(format);
 481
 482       render = texture = brw_format_for_mesa_format(format);
 483       tinfo = &surface_formats[texture];
 484
 485       /* The value of BRW_SURFACEFORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 486        * it.
 487        */
 488       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 489          continue;
 490
 491       if (gen >= tinfo->sampling && (gen >= tinfo->filtering || is_integer))
 492          ctx->TextureFormatSupported[format] = true;
 493
 494       /* Re-map some render target formats to make them supported when they
 495        * wouldn't be using their format for texturing.
 496        */
 497       switch (render) {
 498          /* For these formats, we just need to read/write the first
 499           * channel into R, which is to say that we just treat them as
 500           * GL_RED.
 501           */
 502       case BRW_SURFACEFORMAT_I32_FLOAT:
 503       case BRW_SURFACEFORMAT_L32_FLOAT:
 504          render = BRW_SURFACEFORMAT_R32_FLOAT;
 505          break;
 506       case BRW_SURFACEFORMAT_I16_FLOAT:
 507       case BRW_SURFACEFORMAT_L16_FLOAT:
 508          render = BRW_SURFACEFORMAT_R16_FLOAT;
 509          break;
 510       case BRW_SURFACEFORMAT_B8G8R8X8_UNORM:
 511          /* XRGB is handled as ARGB because the chips in this family
 512           * cannot render to XRGB targets.  This means that we have to
 513           * mask writes to alpha (ala glColorMask) and reconfigure the
 514           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 515           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 516           * used.
 517           */
 518          render = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 519          break;
 520       }
 521
 522       rinfo = &surface_formats[render];
 523
 524       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 525        * integer, so we don't need hardware support for blending on it.  Other
 526        * than that, GL in general requires alpha blending for render targets,
 527        * even though we don't support it for some formats.
 528        *
 529        * We don't currently support rendering to SNORM textures because some of
 530        * the ARB_color_buffer_float clamping is broken for it
 531        * (piglit arb_color_buffer_float-drawpixels GL_RGBA8_SNORM).
 532        */
 533       if (gen >= rinfo->render_target &&
 534           (gen >= rinfo->alpha_blend || is_integer) &&
 535           _mesa_get_format_datatype(format) != GL_SIGNED_NORMALIZED) {
 536          brw->render_target_format[format] = render;
 537          brw->format_supported_as_render_target[format] = true;
 538       }
 539    }
 540
 541    /* We will check this table for FBO completeness, but the surface format
 542     * table above only covered color rendering.
 543     */
 544    brw->format_supported_as_render_target[MESA_FORMAT_S8_Z24] = true;
 545    brw->format_supported_as_render_target[MESA_FORMAT_X8_Z24] = true;
 546    brw->format_supported_as_render_target[MESA_FORMAT_S8] = true;
 547    brw->format_supported_as_render_target[MESA_FORMAT_Z16] = true;
 548    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT] = true;
 549    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 550
 551    /* We remap depth formats to a supported texturing format in
 552     * translate_tex_format().
 553     */
 554    ctx->TextureFormatSupported[MESA_FORMAT_S8_Z24] = true;
 555    ctx->TextureFormatSupported[MESA_FORMAT_X8_Z24] = true;
 556    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT] = true;
 557    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_X24S8] = true;
 558    ctx->TextureFormatSupported[MESA_FORMAT_Z16] = true;
 559 }
 560
 561 bool
 562 brw_render_target_supported(struct intel_context *intel,
 563                             struct gl_renderbuffer *rb)
 564 {
 565    struct brw_context *brw = brw_context(&intel->ctx);
 566    gl_format format = rb->Format;
 567
 568    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 569     * we would consider them renderable even though we don't have surface
 570     * support for their alpha behavior and don't have the blending unit
 571     * available to fake it like we do for XRGB8888.  Force them to being
 572     * unsupported.
 573     */
 574    if ((rb->_BaseFormat != GL_RGBA &&
 575         rb->_BaseFormat != GL_RG &&
 576         rb->_BaseFormat != GL_RED) && _mesa_is_format_integer_color(format))
 577       return false;
 578
 579    return brw->format_supported_as_render_target[format];
 580 }
 581
 582 GLuint
 583 translate_tex_format(gl_format mesa_format,
 584                      GLenum internal_format,
 585                      GLenum depth_mode,
 586                      GLenum srgb_decode)
 587 {
 588    switch( mesa_format ) {
 589
 590    case MESA_FORMAT_Z16:
 591       return BRW_SURFACEFORMAT_I16_UNORM;
 592
 593    case MESA_FORMAT_S8_Z24:
 594    case MESA_FORMAT_X8_Z24:
 595       return BRW_SURFACEFORMAT_I24X8_UNORM;
 596
 597    case MESA_FORMAT_Z32_FLOAT:
 598       return BRW_SURFACEFORMAT_I32_FLOAT;
 599
 600    case MESA_FORMAT_Z32_FLOAT_X24S8:
 601       return BRW_SURFACEFORMAT_R32G32_FLOAT;
 602
 603    case MESA_FORMAT_SARGB8:
 604    case MESA_FORMAT_SLA8:
 605    case MESA_FORMAT_SL8:
 606       if (srgb_decode == GL_DECODE_EXT)
 607          return brw_format_for_mesa_format(mesa_format);
 608       else if (srgb_decode == GL_SKIP_DECODE_EXT)
 609          return brw_format_for_mesa_format(_mesa_get_srgb_format_linear(mesa_format));
 610
 611    case MESA_FORMAT_RGBA_FLOAT32:
 612       /* The value of this BRW_SURFACEFORMAT is 0, which tricks the
 613        * assertion below.
 614        */
 615       return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 616
 617    default:
 618       assert(brw_format_for_mesa_format(mesa_format) != 0);
 619       return brw_format_for_mesa_format(mesa_format);
 620    }
 621 }
 622
 623 static uint32_t
 624 brw_get_surface_tiling_bits(uint32_t tiling)
 625 {
 626    switch (tiling) {
 627    case I915_TILING_X:
 628       return BRW_SURFACE_TILED;
 629    case I915_TILING_Y:
 630       return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y;
 631    default:
 632       return 0;
 633    }
 634 }
 635
 636 static void
 637 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 638 {
 639    struct brw_context *brw = brw_context(ctx);
 640    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 641    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 642    struct intel_mipmap_tree *mt = intelObj->mt;
 643    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 644    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 645    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 646    uint32_t *surf;
 647    int width, height, depth;
 648
 649    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 650
 651    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 652                           6 * 4, 32, &brw->wm.surf_offset[surf_index]);
 653
 654    surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 655               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 656               BRW_SURFACE_CUBEFACE_ENABLES |
 657               (translate_tex_format(mt->format,
 658                                     firstImage->InternalFormat,
 659                                     sampler->DepthMode,
 660                                     sampler->sRGBDecode) <<
 661                BRW_SURFACE_FORMAT_SHIFT));
 662
 663    surf[1] = intelObj->mt->region->bo->offset; /* reloc */
 664
 665    surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 666               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 667               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 668
 669    surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
 670               (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 671               ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1) <<
 672               BRW_SURFACE_PITCH_SHIFT);
 673
 674    surf[4] = 0;
 675
 676    surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 677
 678    /* Emit relocation to surface contents */
 679    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 680                            brw->wm.surf_offset[surf_index] + 4,
 681                            intelObj->mt->region->bo, 0,
 682                            I915_GEM_DOMAIN_SAMPLER, 0);
 683 }
 684
 685 /**
 686  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 687  * read from this buffer with Data Port Read instructions/messages.
 688  */
 689 void
 690 brw_create_constant_surface(struct brw_context *brw,
 691                             drm_intel_bo *bo,
 692                             int width,
 693                             uint32_t *out_offset)
 694 {
 695    struct intel_context *intel = &brw->intel;
 696    const GLint w = width - 1;
 697    uint32_t *surf;
 698
 699    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 700                           6 * 4, 32, out_offset);
 701
 702    surf[0] = (BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 703               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 704               BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT);
 705
 706    if (intel->gen >= 6)
 707       surf[0] |= BRW_SURFACE_RC_READ_WRITE;
 708
 709    surf[1] = bo->offset; /* reloc */
 710
 711    surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
 712               ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT);
 713
 714    surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
 715               (16 - 1) << BRW_SURFACE_PITCH_SHIFT); /* ignored */
 716
 717    surf[4] = 0;
 718    surf[5] = 0;
 719
 720    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 721     * bspec ("Data Cache") says that the data cache does not exist as
 722     * a separate cache and is just the sampler cache.
 723     */
 724    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 725                            *out_offset + 4,
 726                            bo, 0,
 727                            I915_GEM_DOMAIN_SAMPLER, 0);
 728 }
 729
 730 /**
 731  * Set up a binding table entry for use by stream output logic (transform
 732  * feedback).
 733  *
 734  * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
 735  */
 736 void
 737 brw_update_sol_surface(struct brw_context *brw,
 738                        struct gl_buffer_object *buffer_obj,
 739                        uint32_t *out_offset, unsigned num_vector_components,
 740                        unsigned stride_dwords, unsigned offset_dwords)
 741 {
 742    struct intel_context *intel = &brw->intel;
 743    struct intel_buffer_object *intel_bo = intel_buffer_object(buffer_obj);
 744    drm_intel_bo *bo =
 745       intel_bufferobj_buffer(intel, intel_bo, INTEL_WRITE_PART);
 746    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
 747                                     out_offset);
 748    uint32_t pitch_minus_1 = 4*stride_dwords - 1;
 749    uint32_t offset_bytes = 4 * offset_dwords;
 750    size_t size_dwords = buffer_obj->Size / 4;
 751    uint32_t buffer_size_minus_1, width, height, depth, surface_format;
 752
 753    /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
 754     * too big to map using a single binding table entry?
 755     */
 756    assert((size_dwords - offset_dwords) / stride_dwords
 757           <= BRW_MAX_NUM_BUFFER_ENTRIES);
 758
 759    if (size_dwords > offset_dwords + num_vector_components) {
 760       /* There is room for at least 1 transform feedback output in the buffer.
 761        * Compute the number of additional transform feedback outputs the
 762        * buffer has room for.
 763        */
 764       buffer_size_minus_1 =
 765          (size_dwords - offset_dwords - num_vector_components) / stride_dwords;
 766    } else {
 767       /* There isn't even room for a single transform feedback output in the
 768        * buffer.  We can't configure the binding table entry to prevent output
 769        * entirely; we'll have to rely on the geometry shader to detect
 770        * overflow.  But to minimize the damage in case of a bug, set up the
 771        * binding table entry to just allow a single output.
 772        */
 773       buffer_size_minus_1 = 0;
 774    }
 775    width = buffer_size_minus_1 & 0x7f;
 776    height = (buffer_size_minus_1 & 0xfff80) >> 7;
 777    depth = (buffer_size_minus_1 & 0x7f00000) >> 20;
 778
 779    switch (num_vector_components) {
 780    case 1:
 781       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 782       break;
 783    case 2:
 784       surface_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
 785       break;
 786    case 3:
 787       surface_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT;
 788       break;
 789    case 4:
 790       surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 791       break;
 792    default:
 793       assert(!"Invalid vector size for transform feedback output");
 794       surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 795       break;
 796    }
 797
 798    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 799       BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
 800       surface_format << BRW_SURFACE_FORMAT_SHIFT |
 801       BRW_SURFACE_RC_READ_WRITE;
 802    surf[1] = bo->offset + offset_bytes; /* reloc */
 803    surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
 804               height << BRW_SURFACE_HEIGHT_SHIFT);
 805    surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
 806               pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
 807    surf[4] = 0;
 808    surf[5] = 0;
 809
 810    /* Emit relocation to surface contents. */
 811    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 812                            *out_offset + 4,
 813                            bo, offset_bytes,
 814                            I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 815 }
 816
 817 /* Creates a new WM constant buffer reflecting the current fragment program's
 818  * constants, if needed by the fragment program.
 819  *
 820  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 821  * state atom.
 822  */
 823 static void
 824 brw_upload_wm_pull_constants(struct brw_context *brw)
 825 {
 826    struct gl_context *ctx = &brw->intel.ctx;
 827    struct intel_context *intel = &brw->intel;
 828    /* BRW_NEW_FRAGMENT_PROGRAM */
 829    struct brw_fragment_program *fp =
 830       (struct brw_fragment_program *) brw->fragment_program;
 831    struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 832    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 833    const int surf_index = SURF_INDEX_FRAG_CONST_BUFFER;
 834    float *constants;
 835    unsigned int i;
 836
 837    _mesa_load_state_parameters(ctx, params);
 838
 839    /* CACHE_NEW_WM_PROG */
 840    if (brw->wm.prog_data->nr_pull_params == 0) {
 841       if (brw->wm.const_bo) {
 842          drm_intel_bo_unreference(brw->wm.const_bo);
 843          brw->wm.const_bo = NULL;
 844          brw->wm.surf_offset[surf_index] = 0;
 845          brw->state.dirty.brw |= BRW_NEW_SURFACES;
 846       }
 847       return;
 848    }
 849
 850    drm_intel_bo_unreference(brw->wm.const_bo);
 851    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 852                                          size, 64);
 853
 854    /* _NEW_PROGRAM_CONSTANTS */
 855    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 856    constants = brw->wm.const_bo->virtual;
 857    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 858       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 859                                    brw->wm.prog_data->pull_param[i]);
 860    }
 861    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 862
 863    intel->vtbl.create_constant_surface(brw, brw->wm.const_bo,
 864                                        params->NumParameters,
 865                                        &brw->wm.surf_offset[surf_index]);
 866
 867    brw->state.dirty.brw |= BRW_NEW_SURFACES;
 868 }
 869
 870 const struct brw_tracked_state brw_wm_pull_constants = {
 871    .dirty = {
 872       .mesa = (_NEW_PROGRAM_CONSTANTS),
 873       .brw = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
 874       .cache = CACHE_NEW_WM_PROG,
 875    },
 876    .emit = brw_upload_wm_pull_constants,
 877 };
 878
 879 static void
 880 brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit)
 881 {
 882    struct intel_context *intel = &brw->intel;
 883    uint32_t *surf;
 884
 885    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 886                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 887
 888    surf[0] = (BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 889               BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT);
 890    if (intel->gen < 6) {
 891       surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT |
 892                   1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT |
 893                   1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
 894                   1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
 895    }
 896    surf[1] = 0;
 897    surf[2] = 0;
 898    surf[3] = 0;
 899    surf[4] = 0;
 900    surf[5] = 0;
 901 }
 902
 903 /**
 904  * Sets up a surface state structure to point at the given region.
 905  * While it is only used for the front/back buffer currently, it should be
 906  * usable for further buffers when doing ARB_draw_buffer support.
 907  */
 908 static void
 909 brw_update_renderbuffer_surface(struct brw_context *brw,
 910                                 struct gl_renderbuffer *rb,
 911                                 unsigned int unit)
 912 {
 913    struct intel_context *intel = &brw->intel;
 914    struct gl_context *ctx = &intel->ctx;
 915    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 916    struct intel_mipmap_tree *mt = irb->mt;
 917    struct intel_region *region;
 918    uint32_t *surf;
 919    uint32_t tile_x, tile_y;
 920    uint32_t format = 0;
 921    gl_format rb_format = intel_rb_format(irb);
 922
 923    if (irb->tex_image && !brw->has_surface_tile_offset) {
 924       intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 925
 926       if (tile_x != 0 || tile_y != 0) {
 927          /* Original gen4 hardware couldn't draw to a non-tile-aligned
 928           * destination in a miptree unless you actually setup your renderbuffer
 929           * as a miptree and used the fragile lod/array_index/etc. controls to
 930           * select the image.  So, instead, we just make a new single-level
 931           * miptree and render into that.
 932           */
 933          struct intel_context *intel = intel_context(ctx);
 934          struct intel_texture_image *intel_image =
 935             intel_texture_image(irb->tex_image);
 936          struct intel_mipmap_tree *new_mt;
 937          int width, height, depth;
 938
 939          intel_miptree_get_dimensions_for_image(irb->tex_image, &width, &height, &depth);
 940
 941          new_mt = intel_miptree_create(intel, irb->tex_image->TexObject->Target,
 942                                        intel_image->base.Base.TexFormat,
 943                                        intel_image->base.Base.Level,
 944                                        intel_image->base.Base.Level,
 945                                        width, height, depth,
 946                                        true);
 947
 948          intel_miptree_copy_teximage(intel, intel_image, new_mt);
 949          intel_miptree_reference(&irb->mt, intel_image->mt);
 950          intel_renderbuffer_set_draw_offset(irb);
 951          intel_miptree_release(&new_mt);
 952
 953          mt = irb->mt;
 954       }
 955    }
 956
 957    region = irb->mt->region;
 958
 959    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 960                           6 * 4, 32, &brw->wm.surf_offset[unit]);
 961
 962    switch (rb_format) {
 963    case MESA_FORMAT_SARGB8:
 964       /* _NEW_BUFFERS
 965        *
 966        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
 967        * blend/update as sRGB.
 968        */
 969       if (ctx->Color.sRGBEnabled)
 970          format = brw_format_for_mesa_format(rb_format);
 971       else
 972          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 973       break;
 974    default:
 975       format = brw->render_target_format[rb_format];
 976       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 977          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 978                        __FUNCTION__, _mesa_get_format_name(rb_format));
 979       }
 980       break;
 981    }
 982
 983    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 984               format << BRW_SURFACE_FORMAT_SHIFT);
 985
 986    /* reloc */
 987    surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 988               region->bo->offset);
 989
 990    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
 991               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 992
 993    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 994               ((region->pitch * region->cpp) - 1) << BRW_SURFACE_PITCH_SHIFT);
 995
 996    surf[4] = 0;
 997
 998    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 999    /* Note that the low bits of these fields are missing, so
1000     * there's the possibility of getting in trouble.
1001     */
1002    assert(tile_x % 4 == 0);
1003    assert(tile_y % 2 == 0);
1004    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
1005               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
1006               (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
1007
1008    if (intel->gen < 6) {
1009       /* _NEW_COLOR */
1010       if (!ctx->Color.ColorLogicOpEnabled &&
1011           (ctx->Color.BlendEnabled & (1 << unit)))
1012          surf[0] |= BRW_SURFACE_BLEND_ENABLED;
1013
1014       if (!ctx->Color.ColorMask[unit][0])
1015          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT;
1016       if (!ctx->Color.ColorMask[unit][1])
1017          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT;
1018       if (!ctx->Color.ColorMask[unit][2])
1019          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT;
1020
1021       /* As mentioned above, disable writes to the alpha component when the
1022        * renderbuffer is XRGB.
1023        */
1024       if (ctx->DrawBuffer->Visual.alphaBits == 0 ||
1025           !ctx->Color.ColorMask[unit][3]) {
1026          surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT;
1027       }
1028    }
1029
1030    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
1031                            brw->wm.surf_offset[unit] + 4,
1032                            region->bo,
1033                            surf[1] - region->bo->offset,
1034                            I915_GEM_DOMAIN_RENDER,
1035                            I915_GEM_DOMAIN_RENDER);
1036 }
1037
1038 /**
1039  * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
1040  */
1041 static void
1042 brw_update_renderbuffer_surfaces(struct brw_context *brw)
1043 {
1044    struct intel_context *intel = &brw->intel;
1045    struct gl_context *ctx = &brw->intel.ctx;
1046    GLuint i;
1047
1048    /* _NEW_BUFFERS | _NEW_COLOR */
1049    /* Update surfaces for drawing buffers */
1050    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
1051       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1052          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
1053             intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i);
1054          } else {
1055             intel->vtbl.update_null_renderbuffer_surface(brw, i);
1056          }
1057       }
1058    } else {
1059       intel->vtbl.update_null_renderbuffer_surface(brw, 0);
1060    }
1061    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1062 }
1063
1064 const struct brw_tracked_state brw_renderbuffer_surfaces = {
1065    .dirty = {
1066       .mesa = (_NEW_COLOR |
1067                _NEW_BUFFERS),
1068       .brw = BRW_NEW_BATCH,
1069       .cache = 0
1070    },
1071    .emit = brw_update_renderbuffer_surfaces,
1072 };
1073
1074 const struct brw_tracked_state gen6_renderbuffer_surfaces = {
1075    .dirty = {
1076       .mesa = _NEW_BUFFERS,
1077       .brw = BRW_NEW_BATCH,
1078       .cache = 0
1079    },
1080    .emit = brw_update_renderbuffer_surfaces,
1081 };
1082
1083 /**
1084  * Construct SURFACE_STATE objects for enabled textures.
1085  */
1086 static void
1087 brw_update_texture_surfaces(struct brw_context *brw)
1088 {
1089    struct gl_context *ctx = &brw->intel.ctx;
1090
1091    for (unsigned i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1092       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
1093       const GLuint surf = SURF_INDEX_TEXTURE(i);
1094
1095       /* _NEW_TEXTURE */
1096       if (texUnit->_ReallyEnabled) {
1097          brw->intel.vtbl.update_texture_surface(ctx, i);
1098       } else {
1099          brw->wm.surf_offset[surf] = 0;
1100       }
1101
1102       /* For now, just mirror the texture setup to the VS slots. */
1103       brw->vs.surf_offset[SURF_INDEX_VS_TEXTURE(i)] =
1104          brw->wm.surf_offset[surf];
1105    }
1106
1107    brw->state.dirty.brw |= BRW_NEW_SURFACES;
1108 }
1109
1110 const struct brw_tracked_state brw_texture_surfaces = {
1111    .dirty = {
1112       .mesa = _NEW_TEXTURE,
1113       .brw = BRW_NEW_BATCH,
1114       .cache = 0
1115    },
1116    .emit = brw_update_texture_surfaces,
1117 };
1118
1119 /**
1120  * Constructs the binding table for the WM surface state, which maps unit
1121  * numbers to surface state objects.
1122  */
1123 static void
1124 brw_upload_wm_binding_table(struct brw_context *brw)
1125 {
1126    uint32_t *bind;
1127    int i;
1128
1129    /* Might want to calculate nr_surfaces first, to avoid taking up so much
1130     * space for the binding table.
1131     */
1132    bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
1133                           sizeof(uint32_t) * BRW_MAX_WM_SURFACES,
1134                           32, &brw->wm.bind_bo_offset);
1135
1136    /* BRW_NEW_SURFACES */
1137    for (i = 0; i < BRW_MAX_WM_SURFACES; i++) {
1138       bind[i] = brw->wm.surf_offset[i];
1139    }
1140
1141    brw->state.dirty.brw |= BRW_NEW_PS_BINDING_TABLE;
1142 }
1143
1144 const struct brw_tracked_state brw_wm_binding_table = {
1145    .dirty = {
1146       .mesa = 0,
1147       .brw = (BRW_NEW_BATCH |
1148               BRW_NEW_SURFACES),
1149       .cache = 0
1150    },
1151    .emit = brw_upload_wm_binding_table,
1152 };
1153
1154 void
1155 gen4_init_vtable_surface_functions(struct brw_context *brw)
1156 {
1157    struct intel_context *intel = &brw->intel;
1158
1159    intel->vtbl.update_texture_surface = brw_update_texture_surface;
1160    intel->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface;
1161    intel->vtbl.update_null_renderbuffer_surface =
1162       brw_update_null_renderbuffer_surface;
1163    intel->vtbl.create_constant_surface = brw_create_constant_surface;
1164 }