2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen7_blorp.h"
43 * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
44 * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
45 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
46 * programmed in order for the programming of this state to be
50 gen7_blorp_emit_urb_config(struct brw_context *brw,
51 const brw_blorp_params *params)
53 /* The minimum valid value is 32. See 3DSTATE_URB_VS,
54 * Dword 1.15:0 "VS Number of URB Entries".
56 int num_vs_entries = 32;
58 int vs_start = 2; /* skip over push constants */
60 gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
64 /* 3DSTATE_BLEND_STATE_POINTERS */
66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
67 const brw_blorp_params *params,
68 uint32_t cc_blend_state_offset)
70 struct intel_context *intel = &brw->intel;
73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
74 OUT_BATCH(cc_blend_state_offset | 1);
79 /* 3DSTATE_CC_STATE_POINTERS */
81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
82 const brw_blorp_params *params,
83 uint32_t cc_state_offset)
85 struct intel_context *intel = &brw->intel;
88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
89 OUT_BATCH(cc_state_offset | 1);
94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
95 const brw_blorp_params *params)
97 struct intel_context *intel = &brw->intel;
98 struct brw_cc_viewport *ccv;
99 uint32_t cc_vp_offset;
101 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
104 ccv->min_depth = 0.0;
105 ccv->max_depth = 1.0;
108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
109 OUT_BATCH(cc_vp_offset);
114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
120 const brw_blorp_params *params,
121 uint32_t depthstencil_offset)
123 struct intel_context *intel = &brw->intel;
126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
127 OUT_BATCH(depthstencil_offset | 1);
132 /* SURFACE_STATE for renderbuffer or texture surface (see
133 * brw_update_renderbuffer_surface and brw_update_texture_surface)
136 gen7_blorp_emit_surface_state(struct brw_context *brw,
137 const brw_blorp_params *params,
138 const brw_blorp_surface_info *surface,
139 uint32_t read_domains, uint32_t write_domain,
140 bool is_render_target)
142 struct intel_context *intel = &brw->intel;
144 uint32_t wm_surf_offset;
145 uint32_t width = surface->width;
146 uint32_t height = surface->height;
147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
148 * color surfaces, width and height are measured in pixels; we don't need
149 * to divide them by 2 as we do for Gen6 (see
150 * gen6_blorp_emit_surface_state).
152 struct intel_region *region = surface->mt->region;
153 uint32_t tile_x, tile_y;
155 uint32_t tiling = surface->map_stencil_as_y_tiled
156 ? I915_TILING_Y : region->tiling;
158 uint32_t *surf = (uint32_t *)
159 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
160 memset(surf, 0, 8 * 4);
162 surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
163 surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
164 gen7_surface_tiling_mode(tiling);
166 if (surface->mt->align_h == 4)
167 surf[0] |= GEN7_SURFACE_VALIGN_4;
168 if (surface->mt->align_w == 8)
169 surf[0] |= GEN7_SURFACE_HALIGN_8;
171 if (surface->array_spacing_lod0)
172 surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
174 surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
178 surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset;
180 /* Note that the low bits of these fields are missing, so
181 * there's the possibility of getting in trouble.
183 assert(tile_x % 4 == 0);
184 assert(tile_y % 2 == 0);
185 surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
186 SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
188 surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
189 SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
191 uint32_t pitch_bytes = region->pitch * region->cpp;
192 if (surface->map_stencil_as_y_tiled)
194 surf[3] = pitch_bytes - 1;
196 surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
197 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
198 gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
202 if (intel->is_haswell) {
203 surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
204 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
205 SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
206 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
209 /* Emit relocation to surface contents */
210 drm_intel_bo_emit_reloc(intel->batch.bo,
213 surf[1] - region->bo->offset,
214 read_domains, write_domain);
216 gen7_check_surface_setup(surf, is_render_target);
218 return wm_surf_offset;
223 * SAMPLER_STATE. See gen7_update_sampler_state().
226 gen7_blorp_emit_sampler_state(struct brw_context *brw,
227 const brw_blorp_params *params)
229 uint32_t sampler_offset;
231 struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
232 brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
233 sizeof(struct gen7_sampler_state),
234 32, &sampler_offset);
235 memset(sampler, 0, sizeof(*sampler));
237 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
238 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
239 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
241 sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
242 sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
243 sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
245 // sampler->ss0.min_mag_neq = 1;
249 sampler->ss0.lod_bias = 0;
251 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
252 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
254 /* Set BaseMipLevel, MaxLOD, MinLOD:
256 * XXX: I don't think that using firstLevel, lastLevel works,
257 * because we always setup the surface state as if firstLevel ==
258 * level zero. Probably have to subtract firstLevel from each of
261 sampler->ss0.base_level = U_FIXED(0, 1);
263 sampler->ss1.max_lod = U_FIXED(0, 8);
264 sampler->ss1.min_lod = U_FIXED(0, 8);
266 sampler->ss3.non_normalized_coord = 1;
268 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
269 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
270 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
271 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
272 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
273 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
275 return sampler_offset;
281 * Disable the hull shader.
284 gen7_blorp_emit_hs_disable(struct brw_context *brw,
285 const brw_blorp_params *params)
287 struct intel_context *intel = &brw->intel;
290 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
303 * Disable the tesselation engine.
306 gen7_blorp_emit_te_disable(struct brw_context *brw,
307 const brw_blorp_params *params)
309 struct intel_context *intel = &brw->intel;
312 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
322 * Disable the domain shader.
325 gen7_blorp_emit_ds_disable(struct brw_context *brw,
326 const brw_blorp_params *params)
328 struct intel_context *intel = &brw->intel;
331 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
346 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
347 const brw_blorp_params *params)
349 struct intel_context *intel = &brw->intel;
352 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
360 gen7_blorp_emit_sf_config(struct brw_context *brw,
361 const brw_blorp_params *params)
363 struct intel_context *intel = &brw->intel;
367 * Disable ViewportTransformEnable (dw1.1)
369 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
370 * Primitives Overview":
371 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
372 * use of screen- space coordinates).
374 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
375 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
377 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
378 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
379 * SOLID: Any triangle or rectangle object found to be front-facing
380 * is rendered as a solid object. This setting is required when
381 * (rendering rectangle (RECTLIST) objects.
385 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
386 OUT_BATCH(params->depth_format <<
387 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
388 OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
399 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
400 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
401 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
402 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
403 for (int i = 0; i < 12; ++i)
411 * Disable thread dispatch (dw5.19) and enable the HiZ op.
414 gen7_blorp_emit_wm_config(struct brw_context *brw,
415 const brw_blorp_params *params,
416 brw_blorp_prog_data *prog_data)
418 struct intel_context *intel = &brw->intel;
420 uint32_t dw1 = 0, dw2 = 0;
422 switch (params->hiz_op) {
423 case GEN6_HIZ_OP_DEPTH_CLEAR:
424 dw1 |= GEN7_WM_DEPTH_CLEAR;
426 case GEN6_HIZ_OP_DEPTH_RESOLVE:
427 dw1 |= GEN7_WM_DEPTH_RESOLVE;
429 case GEN6_HIZ_OP_HIZ_RESOLVE:
430 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
432 case GEN6_HIZ_OP_NONE:
438 dw1 |= GEN7_WM_STATISTICS_ENABLE;
439 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
440 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
441 dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
442 if (params->use_wm_prog) {
443 dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
444 dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
447 if (params->num_samples > 1) {
448 dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
449 if (prog_data && prog_data->persample_msaa_dispatch)
450 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
452 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
454 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
455 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
459 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
469 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
470 * that, thread dispatch info must still be specified.
471 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
472 * states that the valid range for this field is [0x3, 0x2f].
473 * - A dispatch mode must be given; that is, at least one of the
474 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
475 * discovered through simulator error messages.
478 gen7_blorp_emit_ps_config(struct brw_context *brw,
479 const brw_blorp_params *params,
480 uint32_t prog_offset,
481 brw_blorp_prog_data *prog_data)
483 struct intel_context *intel = &brw->intel;
484 uint32_t dw2, dw4, dw5;
485 const int max_threads_shift = brw->intel.is_haswell ?
486 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
489 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
491 /* If there's a WM program, we need to do 16-pixel dispatch since that's
492 * what the program is compiled for. If there isn't, then it shouldn't
493 * matter because no program is actually being run. However, the hardware
494 * gets angry if we don't enable at least one dispatch mode, so just enable
495 * 16-pixel dispatch unconditionally.
497 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
499 if (intel->is_haswell)
500 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
501 if (params->use_wm_prog) {
502 dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
503 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
504 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
508 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
509 OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
521 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
522 const brw_blorp_params *params,
523 uint32_t wm_bind_bo_offset)
525 struct intel_context *intel = &brw->intel;
528 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
529 OUT_BATCH(wm_bind_bo_offset);
535 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
536 const brw_blorp_params *params,
537 uint32_t sampler_offset)
539 struct intel_context *intel = &brw->intel;
542 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
543 OUT_BATCH(sampler_offset);
549 gen7_blorp_emit_constant_ps(struct brw_context *brw,
550 const brw_blorp_params *params,
551 uint32_t wm_push_const_offset)
553 struct intel_context *intel = &brw->intel;
555 /* Make sure the push constants fill an exact integer number of
558 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
560 /* There must be at least one register worth of push constant data. */
561 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
563 /* Enable push constant buffer 0. */
565 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
567 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
569 OUT_BATCH(wm_push_const_offset);
578 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
579 const brw_blorp_params *params)
581 struct intel_context *intel = &brw->intel;
582 uint32_t draw_x = params->depth.x_offset;
583 uint32_t draw_y = params->depth.y_offset;
584 uint32_t tile_mask_x, tile_mask_y;
586 if (params->depth.mt) {
587 brw_get_depthstencil_tile_masks(params->depth.mt, NULL,
588 &tile_mask_x, &tile_mask_y);
591 /* 3DSTATE_DEPTH_BUFFER */
593 uint32_t tile_x = draw_x & tile_mask_x;
594 uint32_t tile_y = draw_y & tile_mask_y;
596 intel_region_get_aligned_offset(params->depth.mt->region,
597 draw_x & ~tile_mask_x,
598 draw_y & ~tile_mask_y, false);
600 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
601 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
602 * Coordinate Offset X/Y":
604 * "The 3 LSBs of both offsets must be zero to ensure correct
607 * We have no guarantee that tile_x and tile_y are correctly aligned,
608 * since they are determined by the mipmap layout, which is only aligned
611 * So, to avoid hanging the GPU, just smash the low order 3 bits of
612 * tile_x and tile_y to 0. This is a temporary workaround until we come
613 * up with a better solution.
618 intel_emit_depth_stall_flushes(intel);
621 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
622 uint32_t pitch_bytes =
623 params->depth.mt->region->pitch * params->depth.mt->region->cpp;
624 OUT_BATCH((pitch_bytes - 1) |
625 params->depth_format << 18 |
626 1 << 22 | /* hiz enable */
627 1 << 28 | /* depth write */
628 BRW_SURFACE_2D << 29);
629 OUT_RELOC(params->depth.mt->region->bo,
630 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
632 OUT_BATCH((params->depth.width + tile_x - 1) << 4 |
633 (params->depth.height + tile_y - 1) << 18);
641 /* 3DSTATE_HIER_DEPTH_BUFFER */
643 struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
644 uint32_t hiz_offset =
645 intel_region_get_aligned_offset(hiz_region,
646 draw_x & ~tile_mask_x,
647 (draw_y & ~tile_mask_y) / 2, false);
650 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
651 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
652 OUT_RELOC(hiz_region->bo,
653 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
658 /* 3DSTATE_STENCIL_BUFFER */
661 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
670 gen7_blorp_emit_depth_disable(struct brw_context *brw,
671 const brw_blorp_params *params)
673 struct intel_context *intel = &brw->intel;
676 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
677 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
687 /* 3DSTATE_CLEAR_PARAMS
689 * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
690 * 3DSTATE_CLEAR_PARAMS:
691 * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
692 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
693 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
696 gen7_blorp_emit_clear_params(struct brw_context *brw,
697 const brw_blorp_params *params)
699 struct intel_context *intel = &brw->intel;
702 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
703 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
704 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
711 gen7_blorp_emit_primitive(struct brw_context *brw,
712 const brw_blorp_params *params)
714 struct intel_context *intel = &brw->intel;
717 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
718 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
720 OUT_BATCH(3); /* vertex count per instance */
722 OUT_BATCH(1); /* instance count */
730 * \copydoc gen6_blorp_exec()
733 gen7_blorp_exec(struct intel_context *intel,
734 const brw_blorp_params *params)
736 struct gl_context *ctx = &intel->ctx;
737 struct brw_context *brw = brw_context(ctx);
738 brw_blorp_prog_data *prog_data = NULL;
739 uint32_t cc_blend_state_offset = 0;
740 uint32_t cc_state_offset = 0;
741 uint32_t depthstencil_offset;
742 uint32_t wm_push_const_offset = 0;
743 uint32_t wm_bind_bo_offset = 0;
744 uint32_t sampler_offset = 0;
746 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
747 gen6_blorp_emit_batch_head(brw, params);
748 gen7_allocate_push_constants(brw);
749 gen6_emit_3dstate_multisample(brw, params->num_samples);
750 gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
751 gen6_blorp_emit_state_base_address(brw, params);
752 gen6_blorp_emit_vertices(brw, params);
753 gen7_blorp_emit_urb_config(brw, params);
754 if (params->use_wm_prog) {
755 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
756 cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
757 gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
758 gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
760 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
761 gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
762 depthstencil_offset);
763 if (params->use_wm_prog) {
764 uint32_t wm_surf_offset_renderbuffer;
765 uint32_t wm_surf_offset_texture;
766 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
767 wm_surf_offset_renderbuffer =
768 gen7_blorp_emit_surface_state(brw, params, ¶ms->dst,
769 I915_GEM_DOMAIN_RENDER,
770 I915_GEM_DOMAIN_RENDER,
771 true /* is_render_target */);
772 wm_surf_offset_texture =
773 gen7_blorp_emit_surface_state(brw, params, ¶ms->src,
774 I915_GEM_DOMAIN_SAMPLER, 0,
775 false /* is_render_target */);
777 gen6_blorp_emit_binding_table(brw, params,
778 wm_surf_offset_renderbuffer,
779 wm_surf_offset_texture);
780 sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
782 gen6_blorp_emit_vs_disable(brw, params);
783 gen7_blorp_emit_hs_disable(brw, params);
784 gen7_blorp_emit_te_disable(brw, params);
785 gen7_blorp_emit_ds_disable(brw, params);
786 gen6_blorp_emit_gs_disable(brw, params);
787 gen7_blorp_emit_streamout_disable(brw, params);
788 gen6_blorp_emit_clip_disable(brw, params);
789 gen7_blorp_emit_sf_config(brw, params);
790 gen7_blorp_emit_wm_config(brw, params, prog_data);
791 if (params->use_wm_prog) {
792 gen7_blorp_emit_binding_table_pointers_ps(brw, params,
794 gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
795 gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
797 gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
798 gen7_blorp_emit_cc_viewport(brw, params);
800 if (params->depth.mt)
801 gen7_blorp_emit_depth_stencil_config(brw, params);
803 gen7_blorp_emit_depth_disable(brw, params);
804 gen7_blorp_emit_clear_params(brw, params);
805 gen6_blorp_emit_drawing_rectangle(brw, params);
806 gen7_blorp_emit_primitive(brw, params);
808 /* See comments above at first invocation of intel_flush() in
809 * gen6_blorp_emit_batch_head().
814 brw->state.dirty.brw = ~0;
815 brw->state.dirty.cache = ~0;