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25 * @file gen7_sol_state.c
27 * Controls the stream output logic (SOL) stage of the gen7 hardware, which is
28 * used to implement GL_EXT_transform_feedback.
31 #include "brw_context.h"
32 #include "brw_state.h"
33 #include "brw_defines.h"
34 #include "intel_batchbuffer.h"
35 #include "intel_buffer_objects.h"
38 upload_3dstate_so_buffers(struct brw_context *brw)
40 struct intel_context *intel = &brw->intel;
41 struct gl_context *ctx = &intel->ctx;
42 /* BRW_NEW_VERTEX_PROGRAM */
43 const struct gl_shader_program *vs_prog =
44 ctx->Shader.CurrentVertexProgram;
45 const struct gl_transform_feedback_info *linked_xfb_info =
46 &vs_prog->LinkedTransformFeedback;
47 /* _NEW_TRANSFORM_FEEDBACK */
48 struct gl_transform_feedback_object *xfb_obj =
49 ctx->TransformFeedback.CurrentObject;
52 /* Set up the up to 4 output buffers. These are the ranges defined in the
53 * gl_transform_feedback_object.
55 for (i = 0; i < 4; i++) {
56 struct gl_buffer_object *bufferobj = xfb_obj->Buffers[i];
60 if (!xfb_obj->Buffers[i]) {
61 /* The pitch of 0 in this command indicates that the buffer is
62 * unbound and won't be written to.
65 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
66 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
74 bo = intel_buffer_object(bufferobj)->buffer;
76 start = xfb_obj->Offset[i];
77 assert(start % 4 == 0);
78 end = ALIGN(start + xfb_obj->Size[i], 4);
79 assert(end <= bo->size);
82 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
83 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) |
84 ((linked_xfb_info->BufferStride[i] * 4) <<
85 SO_BUFFER_PITCH_SHIFT));
86 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
87 OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
93 * Outputs the 3DSTATE_SO_DECL_LIST command.
95 * The data output is a series of 64-bit entries containing a SO_DECL per
96 * stream. We only have one stream of rendering coming out of the GS unit, so
97 * we only emit stream 0 (low 16 bits) SO_DECLs.
100 upload_3dstate_so_decl_list(struct brw_context *brw,
101 struct brw_vue_map *vue_map)
103 struct intel_context *intel = &brw->intel;
104 struct gl_context *ctx = &intel->ctx;
105 /* BRW_NEW_VERTEX_PROGRAM */
106 const struct gl_shader_program *vs_prog =
107 ctx->Shader.CurrentVertexProgram;
108 /* _NEW_TRANSFORM_FEEDBACK */
109 const struct gl_transform_feedback_info *linked_xfb_info =
110 &vs_prog->LinkedTransformFeedback;
112 uint16_t so_decl[128];
114 int next_offset[4] = {0, 0, 0, 0};
116 STATIC_ASSERT(ARRAY_SIZE(so_decl) >= MAX_PROGRAM_OUTPUTS);
118 /* Construct the list of SO_DECLs to be emitted. The formatting of the
119 * command is feels strange -- each dword pair contains a SO_DECL per stream.
121 for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
122 int buffer = linked_xfb_info->Outputs[i].OutputBuffer;
124 int vert_result = linked_xfb_info->Outputs[i].OutputRegister;
125 unsigned component_mask =
126 (1 << linked_xfb_info->Outputs[i].NumComponents) - 1;
128 /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */
129 if (vert_result == VERT_RESULT_PSIZ) {
130 assert(linked_xfb_info->Outputs[i].NumComponents == 1);
131 component_mask <<= 3;
133 component_mask <<= linked_xfb_info->Outputs[i].ComponentOffset;
136 buffer_mask |= 1 << buffer;
138 decl |= buffer << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
139 decl |= vue_map->vert_result_to_slot[vert_result] <<
140 SO_DECL_REGISTER_INDEX_SHIFT;
141 decl |= component_mask << SO_DECL_COMPONENT_MASK_SHIFT;
143 /* This assert should be true until GL_ARB_transform_feedback_instanced
144 * is added and we start using the hole flag.
146 assert(linked_xfb_info->Outputs[i].DstOffset == next_offset[buffer]);
148 next_offset[buffer] += linked_xfb_info->Outputs[i].NumComponents;
153 BEGIN_BATCH(linked_xfb_info->NumOutputs * 2 + 3);
154 OUT_BATCH(_3DSTATE_SO_DECL_LIST << 16 |
155 (linked_xfb_info->NumOutputs * 2 + 1));
157 OUT_BATCH((buffer_mask << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT) |
158 (0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT) |
159 (0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT) |
160 (0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT));
162 OUT_BATCH((linked_xfb_info->NumOutputs << SO_NUM_ENTRIES_0_SHIFT) |
163 (0 << SO_NUM_ENTRIES_1_SHIFT) |
164 (0 << SO_NUM_ENTRIES_2_SHIFT) |
165 (0 << SO_NUM_ENTRIES_3_SHIFT));
167 for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
168 OUT_BATCH(so_decl[i]);
176 upload_3dstate_streamout(struct brw_context *brw, bool active,
177 struct brw_vue_map *vue_map)
179 struct intel_context *intel = &brw->intel;
180 struct gl_context *ctx = &intel->ctx;
181 /* _NEW_TRANSFORM_FEEDBACK */
182 struct gl_transform_feedback_object *xfb_obj =
183 ctx->TransformFeedback.CurrentObject;
184 uint32_t dw1 = 0, dw2 = 0;
187 /* _NEW_RASTERIZER_DISCARD */
188 if (ctx->RasterDiscard)
189 dw1 |= SO_RENDERING_DISABLE;
192 int urb_entry_read_offset = 0;
193 int urb_entry_read_length = (vue_map->num_slots + 1) / 2 -
194 urb_entry_read_offset;
196 dw1 |= SO_FUNCTION_ENABLE;
197 dw1 |= SO_STATISTICS_ENABLE;
200 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION)
201 dw1 |= SO_REORDER_TRAILING;
203 for (i = 0; i < 4; i++) {
204 if (xfb_obj->Buffers[i]) {
205 dw1 |= SO_BUFFER_ENABLE(i);
209 /* We always read the whole vertex. This could be reduced at some
210 * point by reading less and offsetting the register index in the
213 dw2 |= urb_entry_read_offset << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT;
214 dw2 |= (urb_entry_read_length - 1) <<
215 SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
219 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
226 upload_sol_state(struct brw_context *brw)
228 struct intel_context *intel = &brw->intel;
229 struct gl_context *ctx = &intel->ctx;
230 /* _NEW_TRANSFORM_FEEDBACK */
231 struct gl_transform_feedback_object *xfb_obj =
232 ctx->TransformFeedback.CurrentObject;
233 bool active = xfb_obj->Active && !xfb_obj->Paused;
234 struct brw_vue_map vue_map;
236 /* _NEW_TRANSFORM, CACHE_NEW_VS_PROG */
237 brw_compute_vue_map(&vue_map, intel, ctx->Transform.ClipPlanesEnabled != 0,
238 brw->vs.prog_data->outputs_written);
241 upload_3dstate_so_buffers(brw);
242 upload_3dstate_so_decl_list(brw, &vue_map);
244 intel->batch.needs_sol_reset = true;
247 /* Finally, set up the SOL stage. This command must always follow updates to
248 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
249 * MMIO register updates (current performed by the kernel at each batch
252 upload_3dstate_streamout(brw, active, &vue_map);
255 const struct brw_tracked_state gen7_sol_state = {
257 .mesa = (_NEW_RASTERIZER_DISCARD |
259 _NEW_TRANSFORM_FEEDBACK |
261 .brw = (BRW_NEW_BATCH |
262 BRW_NEW_VERTEX_PROGRAM),
263 .cache = CACHE_NEW_VS_PROG,
265 .emit = upload_sol_state,