2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "intel_batchbuffer.h"
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 * Define the base addresses which some state is referenced from.
32 static void upload_state_base_address(struct brw_context *brw)
34 uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
36 perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
38 int pkt_len = brw->gen >= 9 ? 19 : 16;
41 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
42 /* General state base address: stateless DP read/write requests */
43 OUT_BATCH(mocs_wb << 4 | 1);
45 OUT_BATCH(mocs_wb << 16);
46 /* Surface state base address: */
47 OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
49 /* Dynamic state base address: */
50 OUT_RELOC64(brw->batch.bo,
51 I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
53 /* Indirect object base address: MEDIA_OBJECT data */
54 OUT_BATCH(mocs_wb << 4 | 1);
56 /* Instruction base address: shader kernels (incl. SIP) */
57 OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
60 /* General state buffer size */
61 OUT_BATCH(0xfffff001);
62 /* Dynamic state buffer size */
63 OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
64 /* Indirect object upper bound */
65 OUT_BATCH(0xfffff001);
66 /* Instruction access upper bound */
67 OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
75 brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
78 const struct brw_tracked_state gen8_state_base_address = {
81 .brw = BRW_NEW_BATCH |
82 BRW_NEW_PROGRAM_CACHE,
84 .emit = upload_state_base_address