1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_context.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_buffer_objects.h"
31 #include "intel_decode.h"
32 #include "intel_reg.h"
33 #include "intel_bufmgr.h"
34 #include "intel_buffers.h"
37 intel_batchbuffer_reset(struct intel_batchbuffer *batch)
39 struct intel_context *intel = batch->intel;
41 if (batch->buf != NULL) {
42 drm_intel_bo_unreference(batch->buf);
46 batch->buf = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
47 intel->maxBatchSize, 4096);
48 drm_intel_gem_bo_map_gtt(batch->buf);
49 batch->map = batch->buf->virtual;
51 batch->size = intel->maxBatchSize;
52 batch->ptr = batch->map;
53 batch->reserved_space = BATCH_RESERVED;
54 batch->dirty_state = ~0;
55 batch->state_batch_offset = batch->size;
58 struct intel_batchbuffer *
59 intel_batchbuffer_alloc(struct intel_context *intel)
61 struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
64 intel_batchbuffer_reset(batch);
70 intel_batchbuffer_free(struct intel_batchbuffer *batch)
73 drm_intel_gem_bo_unmap_gtt(batch->buf);
76 dri_bo_unreference(batch->buf);
83 /* TODO: Push this whole function into bufmgr.
86 do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
88 struct intel_context *intel = batch->intel;
90 int x_off = 0, y_off = 0;
92 drm_intel_gem_bo_unmap_gtt(batch->buf);
96 if (!intel->intelScreen->no_hw) {
99 if (intel->gen < 6 || !intel->batch->is_blit) {
100 ring = I915_EXEC_RENDER;
102 ring = I915_EXEC_BLT;
105 drm_intel_bo_mrb_exec(batch->buf, used, NULL, 0,
106 (x_off & 0xffff) | (y_off << 16), ring);
109 if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
110 drm_intel_bo_map(batch->buf, GL_FALSE);
111 intel_decode(batch->buf->virtual, used / 4, batch->buf->offset,
112 intel->intelScreen->deviceID, GL_TRUE);
113 drm_intel_bo_unmap(batch->buf);
115 if (intel->vtbl.debug_batch != NULL)
116 intel->vtbl.debug_batch(intel);
122 intel->vtbl.new_batch(intel);
126 _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
129 struct intel_context *intel = batch->intel;
130 GLuint used = batch->ptr - batch->map;
132 if (intel->first_post_swapbuffers_batch == NULL) {
133 intel->first_post_swapbuffers_batch = intel->batch->buf;
134 drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
140 if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
141 fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
144 batch->reserved_space = 0;
146 if (intel->always_flush_cache) {
147 intel_batchbuffer_emit_mi_flush(batch);
148 used = batch->ptr - batch->map;
151 /* Round batchbuffer usage to 2 DWORDs. */
153 if ((used & 4) == 0) {
154 *(GLuint *) (batch->ptr) = 0; /* noop */
156 used = batch->ptr - batch->map;
159 /* Mark the end of the buffer. */
160 *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END;
162 used = batch->ptr - batch->map;
163 assert (used <= batch->buf->size);
165 /* Workaround for recursive batchbuffer flushing: If the window is
166 * moved, we can get into a case where we try to flush during a
167 * flush. What happens is that when we try to grab the lock for
168 * the first flush, we detect that the window moved which then
169 * causes another flush (from the intel_draw_buffer() call in
170 * intelUpdatePageFlipping()). To work around this we reset the
171 * batchbuffer tail pointer before trying to get the lock. This
172 * prevent the nested buffer flush, but a better fix would be to
173 * avoid that in the first place. */
174 batch->ptr = batch->map;
176 if (intel->vtbl.finish_batch)
177 intel->vtbl.finish_batch(intel);
179 intel_upload_finish(intel);
181 /* Check that we didn't just wrap our batchbuffer at a bad time. */
182 assert(!intel->no_batch_wrap);
184 do_flush_locked(batch, used);
186 if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
187 fprintf(stderr, "waiting for idle\n");
188 drm_intel_bo_map(batch->buf, GL_TRUE);
189 drm_intel_bo_unmap(batch->buf);
194 intel_batchbuffer_reset(batch);
198 /* This is the only way buffers get added to the validate list.
201 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
202 drm_intel_bo *buffer,
203 uint32_t read_domains, uint32_t write_domain,
208 assert(delta < buffer->size);
210 if (batch->ptr - batch->map > batch->buf->size)
211 printf ("bad relocation ptr %p map %p offset %d size %lu\n",
212 batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
213 ret = drm_intel_bo_emit_reloc(batch->buf, batch->ptr - batch->map,
215 read_domains, write_domain);
218 * Using the old buffer offset, write in what the right data would be, in case
219 * the buffer doesn't move and we can short-circuit the relocation processing
222 intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
228 intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
229 drm_intel_bo *buffer,
230 uint32_t read_domains, uint32_t write_domain,
235 assert(delta < buffer->size);
237 if (batch->ptr - batch->map > batch->buf->size)
238 printf ("bad relocation ptr %p map %p offset %d size %lu\n",
239 batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
240 ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map,
242 read_domains, write_domain);
245 * Using the old buffer offset, write in what the right data would
246 * be, in case the buffer doesn't move and we can short-circuit the
247 * relocation processing in the kernel
249 intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
255 intel_batchbuffer_data(struct intel_batchbuffer *batch,
256 const void *data, GLuint bytes, bool is_blit)
258 assert((bytes & 3) == 0);
259 intel_batchbuffer_require_space(batch, bytes, is_blit);
260 __memcpy(batch->ptr, data, bytes);
264 /* Emit a pipelined flush to either flush render and texture cache for
265 * reading from a FBO-drawn texture, or flush so that frontbuffer
266 * render appears on the screen in DRI1.
268 * This is also used for the always_flush_cache driconf debug option.
271 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
273 struct intel_context *intel = batch->intel;
275 if (intel->gen >= 6) {
276 if (intel->batch->is_blit) {
278 OUT_BATCH(MI_FLUSH_DW);
285 /* XXX workaround: issue any post sync != 0 before write
288 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
289 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
290 OUT_BATCH(0); /* write address */
291 OUT_BATCH(0); /* write data */
293 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
294 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
295 PIPE_CONTROL_WRITE_FLUSH |
296 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
297 PIPE_CONTROL_NO_WRITE);
298 OUT_BATCH(0); /* write address */
299 OUT_BATCH(0); /* write data */
302 } else if (intel->gen >= 4) {
304 OUT_BATCH(_3DSTATE_PIPE_CONTROL |
305 PIPE_CONTROL_WRITE_FLUSH |
306 PIPE_CONTROL_NO_WRITE);
307 OUT_BATCH(0); /* write address */
308 OUT_BATCH(0); /* write data */
309 OUT_BATCH(0); /* write data */