2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/mtypes.h"
38 #include "main/enums.h"
39 #include "main/colormac.h"
40 #include "main/light.h"
44 #include "tnl/t_pipeline.h"
46 #include "r200_context.h"
47 #include "r200_state.h"
48 #include "r200_ioctl.h"
50 #include "r200_swtcl.h"
51 #include "r200_maos.h"
53 #include "radeon_common_context.h"
59 #define HAVE_LINE_LOOP 0
60 #define HAVE_LINE_STRIPS 1
61 #define HAVE_TRIANGLES 1
62 #define HAVE_TRI_STRIPS 1
63 #define HAVE_TRI_STRIP_1 0
64 #define HAVE_TRI_FANS 1
66 #define HAVE_QUAD_STRIPS 1
67 #define HAVE_POLYGONS 1
71 #define HW_POINTS ((ctx->Point.PointSprite || \
72 ((ctx->_TriangleCaps & (DD_POINT_SIZE | DD_POINT_ATTEN)) && \
73 !(ctx->_TriangleCaps & (DD_POINT_SMOOTH)))) ? \
74 R200_VF_PRIM_POINT_SPRITES : R200_VF_PRIM_POINTS)
75 #define HW_LINES R200_VF_PRIM_LINES
76 #define HW_LINE_LOOP 0
77 #define HW_LINE_STRIP R200_VF_PRIM_LINE_STRIP
78 #define HW_TRIANGLES R200_VF_PRIM_TRIANGLES
79 #define HW_TRIANGLE_STRIP_0 R200_VF_PRIM_TRIANGLE_STRIP
80 #define HW_TRIANGLE_STRIP_1 0
81 #define HW_TRIANGLE_FAN R200_VF_PRIM_TRIANGLE_FAN
82 #define HW_QUADS R200_VF_PRIM_QUADS
83 #define HW_QUAD_STRIP R200_VF_PRIM_QUAD_STRIP
84 #define HW_POLYGON R200_VF_PRIM_POLYGON
87 static GLboolean discrete_prim[0x10] = {
95 0, /* 7 tri_w_flags */
96 1, /* 8 rect list (unused) */
97 1, /* 9 3vert point */
99 0, /* b point sprite */
102 0, /* e quad strip */
107 #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx)
108 #define ELT_TYPE GLushort
110 #define ELT_INIT(prim, hw_prim) \
111 r200TclPrimitive( ctx, prim, hw_prim | R200_VF_PRIM_WALK_IND )
113 #define GET_MESA_ELTS() TNL_CONTEXT(ctx)->vb.Elts
116 /* Don't really know how many elts will fit in what's left of cmdbuf,
117 * as there is state to emit, etc:
120 /* Testing on isosurf shows a maximum around here. Don't know if it's
121 * the card or driver or kernel module that is causing the behaviour.
123 #define GET_MAX_HW_ELTS() 300
125 #define RESET_STIPPLE() do { \
126 R200_STATECHANGE( rmesa, lin ); \
127 radeonEmitState(&rmesa->radeon); \
130 #define AUTO_STIPPLE( mode ) do { \
131 R200_STATECHANGE( rmesa, lin ); \
133 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
134 R200_LINE_PATTERN_AUTO_RESET; \
136 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
137 ~R200_LINE_PATTERN_AUTO_RESET; \
138 radeonEmitState(&rmesa->radeon); \
142 #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr )
144 static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
146 if (rmesa->radeon.dma.flush == r200FlushElts &&
147 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
149 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
150 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used);
152 rmesa->tcl.elt_used += nr*2;
157 if (rmesa->radeon.dma.flush)
158 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
161 rmesa->radeon.tcl.aos_count, 0 );
163 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count);
164 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
169 #define CLOSE_ELTS() \
171 if (0) R200_NEWPRIM( rmesa ); \
176 /* TODO: Try to extend existing primitive if both are identical,
177 * discrete and there are no intervening state changes. (Somewhat
178 * duplicates changes to DrawArrays code)
180 static void r200EmitPrim( GLcontext *ctx,
186 r200ContextPtr rmesa = R200_CONTEXT( ctx );
187 r200TclPrimitive( ctx, prim, hwprim );
189 // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
192 rmesa->radeon.tcl.aos_count,
195 /* Why couldn't this packet have taken an offset param?
197 r200EmitVbufPrim( rmesa,
198 rmesa->tcl.hw_primitive,
202 #define EMIT_PRIM(ctx, prim, hwprim, start, count) do { \
203 r200EmitPrim( ctx, prim, hwprim, start, count ); \
204 (void) rmesa; } while (0)
206 #define MAX_CONVERSION_SIZE 40
207 /* Try & join small primitives
210 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
212 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
215 rmesa->tcl.hw_primitive == (PRIM| \
216 R200_VF_TCL_OUTPUT_VTX_ENABLE| \
217 R200_VF_PRIM_WALK_IND)))
220 #ifdef MESA_BIG_ENDIAN
221 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
222 #define EMIT_ELT(dest, offset, x) do { \
223 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
224 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
225 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
226 (void)rmesa; } while (0)
228 #define EMIT_ELT(dest, offset, x) do { \
229 (dest)[offset] = (GLushort) (x); \
230 (void)rmesa; } while (0)
233 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)((dest)+offset) = ((y)<<16)|(x);
237 #define TAG(x) tcl_##x
238 #include "tnl_dd/t_dd_dmatmp2.h"
240 /**********************************************************************/
241 /* External entrypoints */
242 /**********************************************************************/
244 void r200EmitPrimitive( GLcontext *ctx,
249 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
252 void r200EmitEltPrimitive( GLcontext *ctx,
257 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
260 void r200TclPrimitive( GLcontext *ctx,
264 r200ContextPtr rmesa = R200_CONTEXT(ctx);
265 GLuint newprim = hw_prim | R200_VF_TCL_OUTPUT_VTX_ENABLE;
267 if (newprim != rmesa->tcl.hw_primitive ||
268 !discrete_prim[hw_prim&0xf]) {
269 /* need to disable perspective-correct texturing for point sprites */
270 if ((prim & PRIM_MODE_MASK) == GL_POINTS && ctx->Point.PointSprite) {
271 if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) {
272 R200_STATECHANGE( rmesa, set );
273 rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PERSPECTIVE_ENABLE;
276 else if (!(rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE)) {
277 R200_STATECHANGE( rmesa, set );
278 rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE;
280 R200_NEWPRIM( rmesa );
281 rmesa->tcl.hw_primitive = newprim;
286 /**********************************************************************/
287 /* Fog blend factor computation for hw tcl */
288 /* same calculation used as in t_vb_fog.c */
289 /**********************************************************************/
291 #define FOG_EXP_TABLE_SIZE 256
292 #define FOG_MAX (10.0)
293 #define EXP_FOG_MAX .0006595
294 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
295 static GLfloat exp_table[FOG_EXP_TABLE_SIZE];
298 #define NEG_EXP( result, narg ) \
300 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
301 GLint k = (GLint) f; \
302 if (k > FOG_EXP_TABLE_SIZE-2) \
303 result = (GLfloat) EXP_FOG_MAX; \
305 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
308 #define NEG_EXP( result, narg ) \
310 result = exp(-narg); \
316 * Initialize the exp_table[] lookup table for approximating exp().
319 r200InitStaticFogData( void )
323 for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
324 exp_table[i] = (GLfloat) exp(-f);
330 * Compute per-vertex fog blend factors from fog coordinates by
331 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
332 * Fog coordinates are distances from the eye (typically between the
333 * near and far clip plane distances).
334 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
335 * Fog blend factors are in the range [0,1].
338 r200ComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
340 GLfloat end = ctx->Fog.End;
342 const GLfloat z = FABSF(fogcoord);
344 switch (ctx->Fog.Mode) {
346 if (ctx->Fog.Start == ctx->Fog.End)
349 d = 1.0F / (ctx->Fog.End - ctx->Fog.Start);
350 temp = (end - z) * d;
351 return CLAMP(temp, 0.0F, 1.0F);
354 d = ctx->Fog.Density;
355 NEG_EXP( temp, d * z );
359 d = ctx->Fog.Density*ctx->Fog.Density;
360 NEG_EXP( temp, d * z * z );
364 _mesa_problem(ctx, "Bad fog mode in make_fog_coord");
370 * Predict total emit size for next rendering operation so there is no flush in middle of rendering
371 * Prediction has to aim towards the best possible value that is worse than worst case scenario
373 static GLuint r200EnsureEmitSize( GLcontext * ctx , GLubyte* vimap_rev )
375 r200ContextPtr rmesa = R200_CONTEXT(ctx);
376 TNLcontext *tnl = TNL_CONTEXT(ctx);
377 struct vertex_buffer *VB = &tnl->vb;
378 GLuint space_required;
382 /* predict number of aos to emit */
383 for (i = 0; i < 15; ++i)
385 if (vimap_rev[i] != 255)
392 /* count the prediction for state size */
394 state_size = radeonCountStateEmitSize( &rmesa->radeon );
395 /* vtx may be changed in r200EmitArrays so account for it if not dirty */
396 if (!rmesa->hw.vtx.dirty)
397 state_size += rmesa->hw.vtx.check(rmesa->radeon.glCtx, &rmesa->hw.vtx);
398 /* predict size for elements */
399 for (i = 0; i < VB->PrimitiveCount; ++i)
401 if (!VB->Primitive[i].count)
403 /* If primitive.count is less than MAX_CONVERSION_SIZE
404 rendering code may decide convert to elts.
405 In that case we have to make pessimistic prediction.
406 and use larger of 2 paths. */
407 const GLuint elt_count =(VB->Primitive[i].count/GET_MAX_HW_ELTS() + 1);
408 const GLuint elts = ELTS_BUFSZ(nr_aos) * elt_count;
409 const GLuint index = INDEX_BUFSZ * elt_count;
410 const GLuint vbuf = VBUF_BUFSZ;
411 if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE)
412 || vbuf > index + elts)
413 space_required += vbuf;
415 space_required += index + elts;
416 space_required += AOS_BUFSZ(nr_aos);
420 radeon_print(RADEON_RENDER,RADEON_VERBOSE,
421 "%s space %u, aos %d\n",
422 __func__, space_required, AOS_BUFSZ(nr_aos) );
423 /* flush the buffer in case we need more than is left. */
424 if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __FUNCTION__))
425 return space_required + radeonCountStateEmitSize( &rmesa->radeon );
427 return space_required + state_size;
431 /**********************************************************************/
432 /* Render pipeline stage */
433 /**********************************************************************/
438 static GLboolean r200_run_tcl_render( GLcontext *ctx,
439 struct tnl_pipeline_stage *stage )
441 r200ContextPtr rmesa = R200_CONTEXT(ctx);
442 TNLcontext *tnl = TNL_CONTEXT(ctx);
443 struct vertex_buffer *VB = &tnl->vb;
446 /* use hw fixed order for simplicity, pos 0, weight 1, normal 2, fog 3,
447 color0 - color3 4-7, texcoord0 - texcoord5 8-13, pos 1 14. Must not use
448 more than 12 of those at the same time. */
449 GLubyte map_rev_fixed[15] = {255, 255, 255, 255, 255, 255, 255, 255,
450 255, 255, 255, 255, 255, 255, 255};
453 /* TODO: separate this from the swtnl pipeline
455 if (rmesa->radeon.TclFallback)
456 return GL_TRUE; /* fallback to software t&l */
458 radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s\n", __FUNCTION__);
465 if (rmesa->radeon.NewGLState)
466 if (!r200ValidateState( ctx ))
467 return GL_TRUE; /* fallback to sw t&l */
469 if (!ctx->VertexProgram._Enabled) {
470 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
473 map_rev_fixed[0] = VERT_ATTRIB_POS;
474 /* technically there is no reason we always need VA_COLOR0. In theory
475 could disable it depending on lighting, color materials, texturing... */
476 map_rev_fixed[4] = VERT_ATTRIB_COLOR0;
478 if (ctx->Light.Enabled) {
479 map_rev_fixed[2] = VERT_ATTRIB_NORMAL;
482 /* this also enables VA_COLOR1 when using separate specular
483 lighting model, which is unnecessary.
484 FIXME: OTOH, we're missing the case where a ATI_fragment_shader accesses
485 the secondary color (if lighting is disabled). The chip seems
486 misconfigured for that though elsewhere (tcl output, might lock up) */
487 if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
488 map_rev_fixed[5] = VERT_ATTRIB_COLOR1;
491 if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
492 map_rev_fixed[3] = VERT_ATTRIB_FOG;
495 for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
496 if (ctx->Texture.Unit[i]._ReallyEnabled) {
497 if (rmesa->TexGenNeedNormals[i]) {
498 map_rev_fixed[2] = VERT_ATTRIB_NORMAL;
500 map_rev_fixed[8 + i] = VERT_ATTRIB_TEX0 + i;
503 vimap_rev = &map_rev_fixed[0];
506 /* vtx_tcl_output_vtxfmt_0/1 need to match configuration of "fragment
507 part", since using some vertex interpolator later which is not in
508 out_vtxfmt0/1 will lock up. It seems to be ok to write in vertex
509 prog to a not enabled output however, so just don't mess with it.
510 We only need to change compsel. */
511 GLuint out_compsel = 0;
512 const GLbitfield64 vp_out =
513 rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten;
515 vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0];
516 assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS));
517 out_compsel = R200_OUTPUT_XYZW;
518 if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) {
519 out_compsel |= R200_OUTPUT_COLOR_0;
521 if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) {
522 out_compsel |= R200_OUTPUT_COLOR_1;
524 if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) {
525 out_compsel |= R200_OUTPUT_DISCRETE_FOG;
527 if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) {
528 out_compsel |= R200_OUTPUT_PT_SIZE;
530 for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) {
531 if (vp_out & BITFIELD64_BIT(i)) {
532 out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0);
535 if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) {
536 R200_STATECHANGE( rmesa, vtx );
537 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = out_compsel;
541 /* Do the actual work:
543 radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ );
544 GLuint emit_end = r200EnsureEmitSize( ctx, vimap_rev )
545 + rmesa->radeon.cmdbuf.cs->cdw;
546 r200EmitArrays( ctx, vimap_rev );
548 for (i = 0 ; i < VB->PrimitiveCount ; i++)
550 GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
551 GLuint start = VB->Primitive[i].start;
552 GLuint length = VB->Primitive[i].count;
558 r200EmitEltPrimitive( ctx, start, start+length, prim );
560 r200EmitPrimitive( ctx, start, start+length, prim );
562 if ( emit_end < rmesa->radeon.cmdbuf.cs->cdw )
563 WARN_ONCE("Rendering was %d commands larger than predicted size."
564 " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end);
566 return GL_FALSE; /* finished the pipe */
571 /* Initial state for tcl stage.
573 const struct tnl_pipeline_stage _r200_tcl_stage =
580 r200_run_tcl_render /* run */
585 /**********************************************************************/
586 /* Validate state at pipeline start */
587 /**********************************************************************/
590 /*-----------------------------------------------------------------------
591 * Manage TCL fallbacks
595 static void transition_to_swtnl( GLcontext *ctx )
597 r200ContextPtr rmesa = R200_CONTEXT(ctx);
598 TNLcontext *tnl = TNL_CONTEXT(ctx);
600 R200_NEWPRIM( rmesa );
602 r200ChooseVertexState( ctx );
603 r200ChooseRenderState( ctx );
605 _mesa_validate_all_lighting_tables( ctx );
607 tnl->Driver.NotifyMaterialChange =
608 _mesa_validate_all_lighting_tables;
610 radeonReleaseArrays( ctx, ~0 );
612 /* Still using the D3D based hardware-rasterizer from the radeon;
613 * need to put the card into D3D mode to make it work:
615 R200_STATECHANGE( rmesa, vap );
616 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~(R200_VAP_TCL_ENABLE|R200_VAP_PROG_VTX_SHADER_ENABLE);
619 static void transition_to_hwtnl( GLcontext *ctx )
621 r200ContextPtr rmesa = R200_CONTEXT(ctx);
622 TNLcontext *tnl = TNL_CONTEXT(ctx);
624 _tnl_need_projected_coords( ctx, GL_FALSE );
626 r200UpdateMaterial( ctx );
628 tnl->Driver.NotifyMaterialChange = r200UpdateMaterial;
630 if ( rmesa->radeon.dma.flush )
631 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
633 rmesa->radeon.dma.flush = NULL;
635 R200_STATECHANGE( rmesa, vap );
636 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE;
637 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE;
639 if (ctx->VertexProgram._Enabled) {
640 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_PROG_VTX_SHADER_ENABLE;
643 if ( ((rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] & R200_FOG_USE_MASK)
644 == R200_FOG_USE_SPEC_ALPHA) &&
645 (ctx->Fog.FogCoordinateSource == GL_FOG_COORD )) {
646 R200_STATECHANGE( rmesa, ctx );
647 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_USE_MASK;
648 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_VTX_FOG;
651 R200_STATECHANGE( rmesa, vte );
652 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] &= ~(R200_VTX_XY_FMT|R200_VTX_Z_FMT);
653 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] |= R200_VTX_W0_FMT;
655 if (R200_DEBUG & RADEON_FALLBACKS)
656 fprintf(stderr, "R200 end tcl fallback\n");
660 static char *fallbackStrings[] = {
661 "Rasterization fallback",
662 "Unfilled triangles",
663 "Twosided lighting, differing materials",
664 "Materials in VB (maybe between begin/end)",
677 static char *getFallbackString(GLuint bit)
684 return fallbackStrings[i];
689 void r200TclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
691 r200ContextPtr rmesa = R200_CONTEXT(ctx);
692 GLuint oldfallback = rmesa->radeon.TclFallback;
695 if (oldfallback == 0) {
696 /* We have to flush before transition */
697 if ( rmesa->radeon.dma.flush )
698 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
700 if (R200_DEBUG & RADEON_FALLBACKS)
701 fprintf(stderr, "R200 begin tcl fallback %s\n",
702 getFallbackString( bit ));
703 rmesa->radeon.TclFallback |= bit;
704 transition_to_swtnl( ctx );
706 rmesa->radeon.TclFallback |= bit;
708 if (oldfallback == bit) {
709 /* We have to flush before transition */
710 if ( rmesa->radeon.dma.flush )
711 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
713 if (R200_DEBUG & RADEON_FALLBACKS)
714 fprintf(stderr, "R200 end tcl fallback %s\n",
715 getFallbackString( bit ));
716 rmesa->radeon.TclFallback &= ~bit;
717 transition_to_hwtnl( ctx );
719 rmesa->radeon.TclFallback &= ~bit;