1 /**************************************************************************
3 Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 * Gareth Hughes <gareth@valinux.com>
32 * Keith Whitwell <keithw@vmware.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/enums.h"
38 #include "main/light.h"
39 #include "main/context.h"
40 #include "main/framebuffer.h"
41 #include "main/fbobject.h"
42 #include "util/simple_list.h"
43 #include "main/state.h"
44 #include "main/stencil.h"
45 #include "main/viewport.h"
49 #include "tnl/t_pipeline.h"
50 #include "swrast_setup/swrast_setup.h"
51 #include "drivers/common/meta.h"
52 #include "util/bitscan.h"
54 #include "radeon_context.h"
55 #include "radeon_mipmap_tree.h"
56 #include "radeon_ioctl.h"
57 #include "radeon_state.h"
58 #include "radeon_tcl.h"
59 #include "radeon_tex.h"
60 #include "radeon_swtcl.h"
62 static void radeonUpdateSpecular( struct gl_context *ctx );
64 /* =============================================================
68 static void radeonAlphaFunc( struct gl_context *ctx, GLenum func, GLfloat ref )
70 r100ContextPtr rmesa = R100_CONTEXT(ctx);
71 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
74 CLAMPED_FLOAT_TO_UBYTE(refByte, ref);
76 RADEON_STATECHANGE( rmesa, ctx );
78 pp_misc &= ~(RADEON_ALPHA_TEST_OP_MASK | RADEON_REF_ALPHA_MASK);
79 pp_misc |= (refByte & RADEON_REF_ALPHA_MASK);
83 pp_misc |= RADEON_ALPHA_TEST_FAIL;
86 pp_misc |= RADEON_ALPHA_TEST_LESS;
89 pp_misc |= RADEON_ALPHA_TEST_EQUAL;
92 pp_misc |= RADEON_ALPHA_TEST_LEQUAL;
95 pp_misc |= RADEON_ALPHA_TEST_GREATER;
98 pp_misc |= RADEON_ALPHA_TEST_NEQUAL;
101 pp_misc |= RADEON_ALPHA_TEST_GEQUAL;
104 pp_misc |= RADEON_ALPHA_TEST_PASS;
108 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
111 static void radeonBlendEquationSeparate( struct gl_context *ctx,
112 GLenum modeRGB, GLenum modeA )
114 r100ContextPtr rmesa = R100_CONTEXT(ctx);
115 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK;
116 GLboolean fallback = GL_FALSE;
118 assert( modeRGB == modeA );
123 b |= RADEON_COMB_FCN_ADD_CLAMP;
126 case GL_FUNC_SUBTRACT:
127 b |= RADEON_COMB_FCN_SUB_CLAMP;
131 if (ctx->Color.BlendEnabled)
134 b |= RADEON_COMB_FCN_ADD_CLAMP;
138 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, fallback );
140 RADEON_STATECHANGE( rmesa, ctx );
141 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
142 if ( (ctx->Color.ColorLogicOpEnabled || (ctx->Color.BlendEnabled
143 && ctx->Color.Blend[0].EquationRGB == GL_LOGIC_OP)) ) {
144 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
146 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
151 static void radeonBlendFuncSeparate( struct gl_context *ctx,
152 GLenum sfactorRGB, GLenum dfactorRGB,
153 GLenum sfactorA, GLenum dfactorA )
155 r100ContextPtr rmesa = R100_CONTEXT(ctx);
156 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] &
157 ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK);
158 GLboolean fallback = GL_FALSE;
160 switch ( ctx->Color.Blend[0].SrcRGB ) {
162 b |= RADEON_SRC_BLEND_GL_ZERO;
165 b |= RADEON_SRC_BLEND_GL_ONE;
168 b |= RADEON_SRC_BLEND_GL_DST_COLOR;
170 case GL_ONE_MINUS_DST_COLOR:
171 b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR;
174 b |= RADEON_SRC_BLEND_GL_SRC_COLOR;
176 case GL_ONE_MINUS_SRC_COLOR:
177 b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR;
180 b |= RADEON_SRC_BLEND_GL_SRC_ALPHA;
182 case GL_ONE_MINUS_SRC_ALPHA:
183 b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA;
186 b |= RADEON_SRC_BLEND_GL_DST_ALPHA;
188 case GL_ONE_MINUS_DST_ALPHA:
189 b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA;
191 case GL_SRC_ALPHA_SATURATE:
192 b |= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE;
194 case GL_CONSTANT_COLOR:
195 case GL_ONE_MINUS_CONSTANT_COLOR:
196 case GL_CONSTANT_ALPHA:
197 case GL_ONE_MINUS_CONSTANT_ALPHA:
198 if (ctx->Color.BlendEnabled)
201 b |= RADEON_SRC_BLEND_GL_ONE;
207 switch ( ctx->Color.Blend[0].DstRGB ) {
209 b |= RADEON_DST_BLEND_GL_ZERO;
212 b |= RADEON_DST_BLEND_GL_ONE;
215 b |= RADEON_DST_BLEND_GL_SRC_COLOR;
217 case GL_ONE_MINUS_SRC_COLOR:
218 b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR;
221 b |= RADEON_DST_BLEND_GL_SRC_ALPHA;
223 case GL_ONE_MINUS_SRC_ALPHA:
224 b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
227 b |= RADEON_DST_BLEND_GL_DST_COLOR;
229 case GL_ONE_MINUS_DST_COLOR:
230 b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR;
233 b |= RADEON_DST_BLEND_GL_DST_ALPHA;
235 case GL_ONE_MINUS_DST_ALPHA:
236 b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA;
238 case GL_CONSTANT_COLOR:
239 case GL_ONE_MINUS_CONSTANT_COLOR:
240 case GL_CONSTANT_ALPHA:
241 case GL_ONE_MINUS_CONSTANT_ALPHA:
242 if (ctx->Color.BlendEnabled)
245 b |= RADEON_DST_BLEND_GL_ZERO;
251 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, fallback );
253 RADEON_STATECHANGE( rmesa, ctx );
254 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
259 /* =============================================================
263 static void radeonDepthFunc( struct gl_context *ctx, GLenum func )
265 r100ContextPtr rmesa = R100_CONTEXT(ctx);
267 RADEON_STATECHANGE( rmesa, ctx );
268 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK;
270 switch ( ctx->Depth.Func ) {
272 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEVER;
275 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LESS;
278 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_EQUAL;
281 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LEQUAL;
284 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GREATER;
287 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEQUAL;
290 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GEQUAL;
293 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_ALWAYS;
299 static void radeonDepthMask( struct gl_context *ctx, GLboolean flag )
301 r100ContextPtr rmesa = R100_CONTEXT(ctx);
302 RADEON_STATECHANGE( rmesa, ctx );
304 if ( ctx->Depth.Mask ) {
305 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_WRITE_ENABLE;
307 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_WRITE_ENABLE;
312 /* =============================================================
317 static void radeonFogfv( struct gl_context *ctx, GLenum pname, const GLfloat *param )
319 r100ContextPtr rmesa = R100_CONTEXT(ctx);
320 union { int i; float f; } c, d;
325 if (!ctx->Fog.Enabled)
327 RADEON_STATECHANGE(rmesa, tcl);
328 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
329 switch (ctx->Fog.Mode) {
331 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
334 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
337 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
346 if (!ctx->Fog.Enabled)
348 c.i = rmesa->hw.fog.cmd[FOG_C];
349 d.i = rmesa->hw.fog.cmd[FOG_D];
350 switch (ctx->Fog.Mode) {
353 /* While this is the opposite sign from the DDK, it makes the fog test
354 * pass, and matches r200.
356 d.f = -ctx->Fog.Density;
360 d.f = -(ctx->Fog.Density * ctx->Fog.Density);
363 if (ctx->Fog.Start == ctx->Fog.End) {
367 c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
368 /* While this is the opposite sign from the DDK, it makes the fog
369 * test pass, and matches r200.
371 d.f = -1.0/(ctx->Fog.End-ctx->Fog.Start);
377 if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) {
378 RADEON_STATECHANGE( rmesa, fog );
379 rmesa->hw.fog.cmd[FOG_C] = c.i;
380 rmesa->hw.fog.cmd[FOG_D] = d.i;
384 RADEON_STATECHANGE( rmesa, ctx );
385 _mesa_unclamped_float_rgba_to_ubyte(col, ctx->Fog.Color );
386 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~RADEON_FOG_COLOR_MASK;
387 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |=
388 radeonPackColor( 4, col[0], col[1], col[2], 0 );
390 case GL_FOG_COORD_SRC:
391 radeonUpdateSpecular( ctx );
398 /* =============================================================
402 static void radeonCullFace( struct gl_context *ctx, GLenum unused )
404 r100ContextPtr rmesa = R100_CONTEXT(ctx);
405 GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
406 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
408 s |= RADEON_FFACE_SOLID | RADEON_BFACE_SOLID;
409 t &= ~(RADEON_CULL_FRONT | RADEON_CULL_BACK);
411 if ( ctx->Polygon.CullFlag ) {
412 switch ( ctx->Polygon.CullFaceMode ) {
414 s &= ~RADEON_FFACE_SOLID;
415 t |= RADEON_CULL_FRONT;
418 s &= ~RADEON_BFACE_SOLID;
419 t |= RADEON_CULL_BACK;
421 case GL_FRONT_AND_BACK:
422 s &= ~(RADEON_FFACE_SOLID | RADEON_BFACE_SOLID);
423 t |= (RADEON_CULL_FRONT | RADEON_CULL_BACK);
428 if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
429 RADEON_STATECHANGE(rmesa, set );
430 rmesa->hw.set.cmd[SET_SE_CNTL] = s;
433 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
434 RADEON_STATECHANGE(rmesa, tcl );
435 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
439 static void radeonFrontFace( struct gl_context *ctx, GLenum mode )
441 r100ContextPtr rmesa = R100_CONTEXT(ctx);
442 int cull_face = (mode == GL_CW) ? RADEON_FFACE_CULL_CW : RADEON_FFACE_CULL_CCW;
444 RADEON_STATECHANGE( rmesa, set );
445 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_FFACE_CULL_DIR_MASK;
447 RADEON_STATECHANGE( rmesa, tcl );
448 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_CULL_FRONT_IS_CCW;
450 /* Winding is inverted when rendering to FBO */
451 if (ctx->DrawBuffer && _mesa_is_user_fbo(ctx->DrawBuffer))
452 cull_face = (mode == GL_CCW) ? RADEON_FFACE_CULL_CW : RADEON_FFACE_CULL_CCW;
453 rmesa->hw.set.cmd[SET_SE_CNTL] |= cull_face;
455 if ( mode == GL_CCW )
456 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_CULL_FRONT_IS_CCW;
460 /* =============================================================
463 static void radeonLineWidth( struct gl_context *ctx, GLfloat widthf )
465 r100ContextPtr rmesa = R100_CONTEXT(ctx);
467 RADEON_STATECHANGE( rmesa, lin );
468 RADEON_STATECHANGE( rmesa, set );
470 /* Line width is stored in U6.4 format.
472 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (GLuint)(widthf * 16.0);
473 if ( widthf > 1.0 ) {
474 rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_WIDELINE_ENABLE;
476 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_WIDELINE_ENABLE;
480 static void radeonLineStipple( struct gl_context *ctx, GLint factor, GLushort pattern )
482 r100ContextPtr rmesa = R100_CONTEXT(ctx);
484 RADEON_STATECHANGE( rmesa, lin );
485 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
486 ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern));
490 /* =============================================================
493 static void radeonColorMask( struct gl_context *ctx,
494 GLboolean r, GLboolean g,
495 GLboolean b, GLboolean a )
497 r100ContextPtr rmesa = R100_CONTEXT(ctx);
498 struct radeon_renderbuffer *rrb;
501 rrb = radeon_get_colorbuffer(&rmesa->radeon);
505 mask = radeonPackColor( rrb->cpp,
506 GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0),
507 GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1),
508 GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2),
509 GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3) );
511 if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
512 RADEON_STATECHANGE( rmesa, msk );
513 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = mask;
518 /* =============================================================
522 static void radeonPolygonOffset( struct gl_context *ctx,
523 GLfloat factor, GLfloat units, GLfloat clamp )
525 r100ContextPtr rmesa = R100_CONTEXT(ctx);
526 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
527 float_ui32_type constant = { units * depthScale };
528 float_ui32_type factoru = { factor };
530 RADEON_STATECHANGE( rmesa, zbs );
531 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = factoru.ui32;
532 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32;
535 static void radeonPolygonMode( struct gl_context *ctx, GLenum face, GLenum mode )
537 r100ContextPtr rmesa = R100_CONTEXT(ctx);
538 GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
539 ctx->Polygon.BackMode != GL_FILL);
541 /* Can't generally do unfilled via tcl, but some good special
544 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, unfilled);
545 if (rmesa->radeon.TclFallback) {
546 radeonChooseRenderState( ctx );
547 radeonChooseVertexState( ctx );
552 /* =============================================================
553 * Rendering attributes
555 * We really don't want to recalculate all this every time we bind a
556 * texture. These things shouldn't change all that often, so it makes
557 * sense to break them out of the core texture state update routines.
560 /* Examine lighting and texture state to determine if separate specular
563 static void radeonUpdateSpecular( struct gl_context *ctx )
565 r100ContextPtr rmesa = R100_CONTEXT(ctx);
566 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
569 RADEON_STATECHANGE( rmesa, tcl );
571 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
572 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
573 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_SPEC;
574 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_DIFFUSE;
575 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LIGHTING_ENABLE;
577 p &= ~RADEON_SPECULAR_ENABLE;
579 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_DIFFUSE_SPECULAR_COMBINE;
582 if (ctx->Light.Enabled &&
583 ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) {
584 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
585 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
586 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
587 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
588 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
589 p |= RADEON_SPECULAR_ENABLE;
590 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &=
591 ~RADEON_DIFFUSE_SPECULAR_COMBINE;
593 else if (ctx->Light.Enabled) {
594 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
595 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
596 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
597 } else if (ctx->Fog.ColorSumEnabled ) {
598 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
599 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
600 p |= RADEON_SPECULAR_ENABLE;
602 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
605 if (ctx->Fog.Enabled) {
606 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
607 if (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH) {
608 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
609 /* Bizzare: have to leave lighting enabled to get fog. */
610 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
613 /* cannot do tcl fog factor calculation with fog coord source
614 * (send precomputed factors). Cannot use precomputed fog
615 * factors together with tcl spec light (need tcl fallback) */
616 flag = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &
617 RADEON_TCL_COMPUTE_SPECULAR) != 0;
621 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_FOGCOORDSPEC, flag);
623 if (_mesa_need_secondary_color(ctx)) {
624 assert( (p & RADEON_SPECULAR_ENABLE) != 0 );
626 assert( (p & RADEON_SPECULAR_ENABLE) == 0 );
629 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
630 RADEON_STATECHANGE( rmesa, ctx );
631 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
634 /* Update vertex/render formats
636 if (rmesa->radeon.TclFallback) {
637 radeonChooseRenderState( ctx );
638 radeonChooseVertexState( ctx );
643 /* =============================================================
648 /* Update on colormaterial, material emmissive/ambient,
649 * lightmodel.globalambient
651 static void update_global_ambient( struct gl_context *ctx )
653 r100ContextPtr rmesa = R100_CONTEXT(ctx);
654 float *fcmd = (float *)RADEON_DB_STATE( glt );
656 /* Need to do more if both emmissive & ambient are PREMULT:
657 * Hope this is not needed for MULT
659 if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &
660 ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
661 (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0)
663 COPY_3V( &fcmd[GLT_RED],
664 ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]);
665 ACC_SCALE_3V( &fcmd[GLT_RED],
666 ctx->Light.Model.Ambient,
667 ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]);
671 COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
674 RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
677 /* Update on change to
681 static void update_light_colors( struct gl_context *ctx, GLuint p )
683 struct gl_light *l = &ctx->Light.Light[p];
685 /* fprintf(stderr, "%s\n", __func__); */
688 r100ContextPtr rmesa = R100_CONTEXT(ctx);
689 float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
691 COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
692 COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
693 COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
695 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
699 /* Also fallback for asym colormaterial mode in twoside lighting...
701 static void check_twoside_fallback( struct gl_context *ctx )
703 GLboolean fallback = GL_FALSE;
706 if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
707 if (ctx->Light.ColorMaterialEnabled &&
708 (ctx->Light._ColorMaterialBitmask & BACK_MATERIAL_BITS) !=
709 ((ctx->Light._ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1))
712 for (i = MAT_ATTRIB_FRONT_AMBIENT; i < MAT_ATTRIB_FRONT_INDEXES; i+=2)
713 if (memcmp( ctx->Light.Material.Attrib[i],
714 ctx->Light.Material.Attrib[i+1],
715 sizeof(GLfloat)*4) != 0) {
722 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE, fallback );
726 static void radeonColorMaterial( struct gl_context *ctx, GLenum face, GLenum mode )
728 r100ContextPtr rmesa = R100_CONTEXT(ctx);
729 GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
731 light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
732 (3 << RADEON_AMBIENT_SOURCE_SHIFT) |
733 (3 << RADEON_DIFFUSE_SOURCE_SHIFT) |
734 (3 << RADEON_SPECULAR_SOURCE_SHIFT));
736 if (ctx->Light.ColorMaterialEnabled) {
737 GLuint mask = ctx->Light._ColorMaterialBitmask;
739 if (mask & MAT_BIT_FRONT_EMISSION) {
740 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
741 RADEON_EMISSIVE_SOURCE_SHIFT);
744 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
745 RADEON_EMISSIVE_SOURCE_SHIFT);
748 if (mask & MAT_BIT_FRONT_AMBIENT) {
749 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
750 RADEON_AMBIENT_SOURCE_SHIFT);
753 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
754 RADEON_AMBIENT_SOURCE_SHIFT);
757 if (mask & MAT_BIT_FRONT_DIFFUSE) {
758 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
759 RADEON_DIFFUSE_SOURCE_SHIFT);
762 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
763 RADEON_DIFFUSE_SOURCE_SHIFT);
766 if (mask & MAT_BIT_FRONT_SPECULAR) {
767 light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
768 RADEON_SPECULAR_SOURCE_SHIFT);
771 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
772 RADEON_SPECULAR_SOURCE_SHIFT);
778 light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
779 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
780 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
781 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT);
784 if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) {
785 RADEON_STATECHANGE( rmesa, tcl );
786 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1;
790 void radeonUpdateMaterial( struct gl_context *ctx )
792 r100ContextPtr rmesa = R100_CONTEXT(ctx);
793 GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
794 GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
797 if (ctx->Light.ColorMaterialEnabled)
798 mask &= ~ctx->Light._ColorMaterialBitmask;
800 if (RADEON_DEBUG & RADEON_STATE)
801 fprintf(stderr, "%s\n", __func__);
804 if (mask & MAT_BIT_FRONT_EMISSION) {
805 fcmd[MTL_EMMISSIVE_RED] = mat[MAT_ATTRIB_FRONT_EMISSION][0];
806 fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1];
807 fcmd[MTL_EMMISSIVE_BLUE] = mat[MAT_ATTRIB_FRONT_EMISSION][2];
808 fcmd[MTL_EMMISSIVE_ALPHA] = mat[MAT_ATTRIB_FRONT_EMISSION][3];
810 if (mask & MAT_BIT_FRONT_AMBIENT) {
811 fcmd[MTL_AMBIENT_RED] = mat[MAT_ATTRIB_FRONT_AMBIENT][0];
812 fcmd[MTL_AMBIENT_GREEN] = mat[MAT_ATTRIB_FRONT_AMBIENT][1];
813 fcmd[MTL_AMBIENT_BLUE] = mat[MAT_ATTRIB_FRONT_AMBIENT][2];
814 fcmd[MTL_AMBIENT_ALPHA] = mat[MAT_ATTRIB_FRONT_AMBIENT][3];
816 if (mask & MAT_BIT_FRONT_DIFFUSE) {
817 fcmd[MTL_DIFFUSE_RED] = mat[MAT_ATTRIB_FRONT_DIFFUSE][0];
818 fcmd[MTL_DIFFUSE_GREEN] = mat[MAT_ATTRIB_FRONT_DIFFUSE][1];
819 fcmd[MTL_DIFFUSE_BLUE] = mat[MAT_ATTRIB_FRONT_DIFFUSE][2];
820 fcmd[MTL_DIFFUSE_ALPHA] = mat[MAT_ATTRIB_FRONT_DIFFUSE][3];
822 if (mask & MAT_BIT_FRONT_SPECULAR) {
823 fcmd[MTL_SPECULAR_RED] = mat[MAT_ATTRIB_FRONT_SPECULAR][0];
824 fcmd[MTL_SPECULAR_GREEN] = mat[MAT_ATTRIB_FRONT_SPECULAR][1];
825 fcmd[MTL_SPECULAR_BLUE] = mat[MAT_ATTRIB_FRONT_SPECULAR][2];
826 fcmd[MTL_SPECULAR_ALPHA] = mat[MAT_ATTRIB_FRONT_SPECULAR][3];
828 if (mask & MAT_BIT_FRONT_SHININESS) {
829 fcmd[MTL_SHININESS] = mat[MAT_ATTRIB_FRONT_SHININESS][0];
832 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mtl );
834 check_twoside_fallback( ctx );
835 /* update_global_ambient( ctx );*/
840 * _MESA_NEW_NEED_EYE_COORDS
842 * Uses derived state from mesa:
851 * which are calculated in light.c and are correct for the current
852 * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
853 * and _MESA_NEW_NEED_EYE_COORDS.
855 static void update_light( struct gl_context *ctx )
857 r100ContextPtr rmesa = R100_CONTEXT(ctx);
859 /* Have to check these, or have an automatic shortcircuit mechanism
860 * to remove noop statechanges. (Or just do a better job on the
864 GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
866 if (ctx->_NeedEyeCoords)
867 tmp &= ~RADEON_LIGHT_IN_MODELSPACE;
869 tmp |= RADEON_LIGHT_IN_MODELSPACE;
872 /* Leave this test disabled: (unexplained q3 lockup) (even with
875 if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL])
877 RADEON_STATECHANGE( rmesa, tcl );
878 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp;
883 GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( eye );
884 fcmd[EYE_X] = ctx->_EyeZDir[0];
885 fcmd[EYE_Y] = ctx->_EyeZDir[1];
886 fcmd[EYE_Z] = - ctx->_EyeZDir[2];
887 fcmd[EYE_RESCALE_FACTOR] = ctx->_ModelViewInvScale;
888 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.eye );
893 if (ctx->Light.Enabled) {
894 GLbitfield mask = ctx->Light._EnabledLights;
896 const int p = u_bit_scan(&mask);
897 struct gl_light *l = &ctx->Light.Light[p];
898 GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] );
900 if (l->EyePosition[3] == 0.0) {
901 COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
902 COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
903 fcmd[LIT_POSITION_W] = 0;
904 fcmd[LIT_DIRECTION_W] = 0;
906 COPY_4V( &fcmd[LIT_POSITION_X], l->_Position );
907 fcmd[LIT_DIRECTION_X] = -l->_NormSpotDirection[0];
908 fcmd[LIT_DIRECTION_Y] = -l->_NormSpotDirection[1];
909 fcmd[LIT_DIRECTION_Z] = -l->_NormSpotDirection[2];
910 fcmd[LIT_DIRECTION_W] = 0;
913 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
918 static void radeonLightfv( struct gl_context *ctx, GLenum light,
919 GLenum pname, const GLfloat *params )
921 r100ContextPtr rmesa = R100_CONTEXT(ctx);
922 GLint p = light - GL_LIGHT0;
923 struct gl_light *l = &ctx->Light.Light[p];
924 GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
931 update_light_colors( ctx, p );
934 case GL_SPOT_DIRECTION:
935 /* picked up in update_light */
939 /* positions picked up in update_light, but can do flag here */
941 GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
943 /* FIXME: Set RANGE_ATTEN only when needed */
945 flag = RADEON_LIGHT_1_IS_LOCAL;
947 flag = RADEON_LIGHT_0_IS_LOCAL;
949 RADEON_STATECHANGE(rmesa, tcl);
950 if (l->EyePosition[3] != 0.0F)
951 rmesa->hw.tcl.cmd[idx] |= flag;
953 rmesa->hw.tcl.cmd[idx] &= ~flag;
957 case GL_SPOT_EXPONENT:
958 RADEON_STATECHANGE(rmesa, lit[p]);
959 fcmd[LIT_SPOT_EXPONENT] = params[0];
962 case GL_SPOT_CUTOFF: {
963 GLuint flag = (p&1) ? RADEON_LIGHT_1_IS_SPOT : RADEON_LIGHT_0_IS_SPOT;
964 GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
966 RADEON_STATECHANGE(rmesa, lit[p]);
967 fcmd[LIT_SPOT_CUTOFF] = l->_CosCutoff;
969 RADEON_STATECHANGE(rmesa, tcl);
970 if (l->SpotCutoff != 180.0F)
971 rmesa->hw.tcl.cmd[idx] |= flag;
973 rmesa->hw.tcl.cmd[idx] &= ~flag;
978 case GL_CONSTANT_ATTENUATION:
979 RADEON_STATECHANGE(rmesa, lit[p]);
980 fcmd[LIT_ATTEN_CONST] = params[0];
981 if ( params[0] == 0.0 )
982 fcmd[LIT_ATTEN_CONST_INV] = FLT_MAX;
984 fcmd[LIT_ATTEN_CONST_INV] = 1.0 / params[0];
986 case GL_LINEAR_ATTENUATION:
987 RADEON_STATECHANGE(rmesa, lit[p]);
988 fcmd[LIT_ATTEN_LINEAR] = params[0];
990 case GL_QUADRATIC_ATTENUATION:
991 RADEON_STATECHANGE(rmesa, lit[p]);
992 fcmd[LIT_ATTEN_QUADRATIC] = params[0];
998 /* Set RANGE_ATTEN only when needed */
1001 case GL_CONSTANT_ATTENUATION:
1002 case GL_LINEAR_ATTENUATION:
1003 case GL_QUADRATIC_ATTENUATION:
1005 GLuint *icmd = (GLuint *)RADEON_DB_STATE( tcl );
1006 GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
1007 GLuint atten_flag = ( p&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
1008 : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN;
1009 GLuint atten_const_flag = ( p&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
1010 : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN;
1012 if ( l->EyePosition[3] == 0.0F ||
1013 ( ( fcmd[LIT_ATTEN_CONST] == 0.0 || fcmd[LIT_ATTEN_CONST] == 1.0 ) &&
1014 fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) ) {
1015 /* Disable attenuation */
1016 icmd[idx] &= ~atten_flag;
1018 if ( fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) {
1019 /* Enable only constant portion of attenuation calculation */
1020 icmd[idx] |= ( atten_flag | atten_const_flag );
1022 /* Enable full attenuation calculation */
1023 icmd[idx] &= ~atten_const_flag;
1024 icmd[idx] |= atten_flag;
1028 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tcl );
1039 static void radeonLightModelfv( struct gl_context *ctx, GLenum pname,
1040 const GLfloat *param )
1042 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1045 case GL_LIGHT_MODEL_AMBIENT:
1046 update_global_ambient( ctx );
1049 case GL_LIGHT_MODEL_LOCAL_VIEWER:
1050 RADEON_STATECHANGE( rmesa, tcl );
1051 if (ctx->Light.Model.LocalViewer)
1052 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LOCAL_VIEWER;
1054 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LOCAL_VIEWER;
1057 case GL_LIGHT_MODEL_TWO_SIDE:
1058 RADEON_STATECHANGE( rmesa, tcl );
1059 if (ctx->Light.Model.TwoSide)
1060 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_LIGHT_TWOSIDE;
1062 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_LIGHT_TWOSIDE;
1064 check_twoside_fallback( ctx );
1066 if (rmesa->radeon.TclFallback) {
1067 radeonChooseRenderState( ctx );
1068 radeonChooseVertexState( ctx );
1072 case GL_LIGHT_MODEL_COLOR_CONTROL:
1073 radeonUpdateSpecular(ctx);
1081 static void radeonShadeModel( struct gl_context *ctx, GLenum mode )
1083 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1084 GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
1086 s &= ~(RADEON_DIFFUSE_SHADE_MASK |
1087 RADEON_ALPHA_SHADE_MASK |
1088 RADEON_SPECULAR_SHADE_MASK |
1089 RADEON_FOG_SHADE_MASK);
1093 s |= (RADEON_DIFFUSE_SHADE_FLAT |
1094 RADEON_ALPHA_SHADE_FLAT |
1095 RADEON_SPECULAR_SHADE_FLAT |
1096 RADEON_FOG_SHADE_FLAT);
1099 s |= (RADEON_DIFFUSE_SHADE_GOURAUD |
1100 RADEON_ALPHA_SHADE_GOURAUD |
1101 RADEON_SPECULAR_SHADE_GOURAUD |
1102 RADEON_FOG_SHADE_GOURAUD);
1108 if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
1109 RADEON_STATECHANGE( rmesa, set );
1110 rmesa->hw.set.cmd[SET_SE_CNTL] = s;
1115 /* =============================================================
1119 static void radeonClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq )
1121 GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1122 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1123 GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1125 RADEON_STATECHANGE( rmesa, ucp[p] );
1126 rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1127 rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1128 rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1129 rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1132 static void radeonUpdateClipPlanes( struct gl_context *ctx )
1134 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1135 GLbitfield mask = ctx->Transform.ClipPlanesEnabled;
1138 const int p = u_bit_scan(&mask);
1139 GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1141 RADEON_STATECHANGE( rmesa, ucp[p] );
1142 rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1143 rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1144 rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1145 rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1150 /* =============================================================
1155 radeonStencilFuncSeparate( struct gl_context *ctx, GLenum face, GLenum func,
1156 GLint ref, GLuint mask )
1158 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1159 GLuint refmask = ((_mesa_get_stencil_ref(ctx, 0) << RADEON_STENCIL_REF_SHIFT) |
1160 ((ctx->Stencil.ValueMask[0] & 0xff) << RADEON_STENCIL_MASK_SHIFT));
1162 RADEON_STATECHANGE( rmesa, ctx );
1163 RADEON_STATECHANGE( rmesa, msk );
1165 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_STENCIL_TEST_MASK;
1166 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~(RADEON_STENCIL_REF_MASK|
1167 RADEON_STENCIL_VALUE_MASK);
1169 switch ( ctx->Stencil.Function[0] ) {
1171 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEVER;
1174 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LESS;
1177 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_EQUAL;
1180 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LEQUAL;
1183 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GREATER;
1186 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEQUAL;
1189 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GEQUAL;
1192 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_ALWAYS;
1196 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= refmask;
1200 radeonStencilMaskSeparate( struct gl_context *ctx, GLenum face, GLuint mask )
1202 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1204 RADEON_STATECHANGE( rmesa, msk );
1205 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK;
1206 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |=
1207 ((ctx->Stencil.WriteMask[0] & 0xff) << RADEON_STENCIL_WRITEMASK_SHIFT);
1210 static void radeonStencilOpSeparate( struct gl_context *ctx, GLenum face, GLenum fail,
1211 GLenum zfail, GLenum zpass )
1213 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1215 /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
1216 and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
1217 but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
1219 GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP;
1220 GLuint tempRADEON_STENCIL_FAIL_INC_WRAP;
1221 GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
1222 GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP;
1223 GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
1224 GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
1226 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_BROKEN_STENCIL) {
1227 tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
1228 tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
1229 tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;
1230 tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC;
1231 tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC;
1232 tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC;
1235 tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC_WRAP;
1236 tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC_WRAP;
1237 tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC_WRAP;
1238 tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC_WRAP;
1239 tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP;
1240 tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP;
1243 RADEON_STATECHANGE( rmesa, ctx );
1244 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK |
1245 RADEON_STENCIL_ZFAIL_MASK |
1246 RADEON_STENCIL_ZPASS_MASK);
1248 switch ( ctx->Stencil.FailFunc[0] ) {
1250 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_KEEP;
1253 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_ZERO;
1256 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_REPLACE;
1259 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INC;
1262 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_DEC;
1265 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_INC_WRAP;
1268 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_DEC_WRAP;
1271 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INVERT;
1275 switch ( ctx->Stencil.ZFailFunc[0] ) {
1277 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_KEEP;
1280 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_ZERO;
1283 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_REPLACE;
1286 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INC;
1289 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_DEC;
1292 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP;
1295 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
1298 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INVERT;
1302 switch ( ctx->Stencil.ZPassFunc[0] ) {
1304 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_KEEP;
1307 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_ZERO;
1310 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_REPLACE;
1313 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INC;
1316 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_DEC;
1319 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_INC_WRAP;
1322 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP;
1325 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INVERT;
1332 /* =============================================================
1333 * Window position and viewport transformation
1337 * To correctly position primitives:
1339 #define SUBPIXEL_X 0.125
1340 #define SUBPIXEL_Y 0.125
1344 * Called when window size or position changes or viewport or depth range
1345 * state is changed. We update the hardware viewport state here.
1347 void radeonUpdateWindow( struct gl_context *ctx )
1349 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1350 __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
1351 GLfloat xoffset = 0.0;
1352 GLfloat yoffset = dPriv ? (GLfloat) dPriv->h : 0;
1353 const GLboolean render_to_fbo = (ctx->DrawBuffer ? _mesa_is_user_fbo(ctx->DrawBuffer) : 0);
1354 float scale[3], translate[3];
1355 GLfloat y_scale, y_bias;
1357 if (render_to_fbo) {
1365 _mesa_get_viewport_xform(ctx, 0, scale, translate);
1366 float_ui32_type sx = { scale[0] };
1367 float_ui32_type sy = { scale[1] * y_scale };
1368 float_ui32_type sz = { scale[2] };
1369 float_ui32_type tx = { translate[0] + xoffset + SUBPIXEL_X };
1370 float_ui32_type ty = { (translate[1] * y_scale) + y_bias + SUBPIXEL_Y };
1371 float_ui32_type tz = { translate[2] };
1373 RADEON_STATECHANGE( rmesa, vpt );
1375 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1376 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1377 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1378 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1379 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1380 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
1384 static void radeonViewport(struct gl_context *ctx)
1386 /* Don't pipeline viewport changes, conflict with window offset
1387 * setting below. Could apply deltas to rescue pipelined viewport
1388 * values, or keep the originals hanging around.
1390 radeonUpdateWindow( ctx );
1392 radeon_viewport(ctx);
1395 static void radeonDepthRange(struct gl_context *ctx)
1397 radeonUpdateWindow( ctx );
1400 /* =============================================================
1404 static void radeonRenderMode( struct gl_context *ctx, GLenum mode )
1406 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1407 FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) );
1410 static void radeonLogicOpCode(struct gl_context *ctx, enum gl_logicop_mode opcode)
1412 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1414 assert((unsigned) opcode <= 15);
1416 RADEON_STATECHANGE( rmesa, msk );
1417 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = opcode;
1420 /* =============================================================
1421 * State enable/disable
1424 static void radeonEnable( struct gl_context *ctx, GLenum cap, GLboolean state )
1426 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1429 if ( RADEON_DEBUG & RADEON_STATE )
1430 fprintf( stderr, "%s( %s = %s )\n", __func__,
1431 _mesa_enum_to_string( cap ),
1432 state ? "GL_TRUE" : "GL_FALSE" );
1435 /* Fast track this one...
1443 RADEON_STATECHANGE( rmesa, ctx );
1445 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE;
1447 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE;
1452 RADEON_STATECHANGE( rmesa, ctx );
1454 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ALPHA_BLEND_ENABLE;
1456 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE;
1458 if ( (ctx->Color.ColorLogicOpEnabled || (ctx->Color.BlendEnabled
1459 && ctx->Color.Blend[0].EquationRGB == GL_LOGIC_OP)) ) {
1460 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
1462 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1465 /* Catch a possible fallback:
1468 ctx->Driver.BlendEquationSeparate( ctx,
1469 ctx->Color.Blend[0].EquationRGB,
1470 ctx->Color.Blend[0].EquationA );
1471 ctx->Driver.BlendFuncSeparate( ctx, ctx->Color.Blend[0].SrcRGB,
1472 ctx->Color.Blend[0].DstRGB,
1473 ctx->Color.Blend[0].SrcA,
1474 ctx->Color.Blend[0].DstA );
1477 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, GL_FALSE );
1478 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, GL_FALSE );
1482 case GL_CLIP_PLANE0:
1483 case GL_CLIP_PLANE1:
1484 case GL_CLIP_PLANE2:
1485 case GL_CLIP_PLANE3:
1486 case GL_CLIP_PLANE4:
1487 case GL_CLIP_PLANE5:
1488 p = cap-GL_CLIP_PLANE0;
1489 RADEON_STATECHANGE( rmesa, tcl );
1491 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (RADEON_UCP_ENABLE_0<<p);
1492 radeonClipPlane( ctx, cap, NULL );
1495 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(RADEON_UCP_ENABLE_0<<p);
1499 case GL_COLOR_MATERIAL:
1500 radeonColorMaterial( ctx, 0, 0 );
1501 radeonUpdateMaterial( ctx );
1505 radeonCullFace( ctx, 0 );
1509 RADEON_STATECHANGE(rmesa, ctx );
1511 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_Z_ENABLE;
1513 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE;
1518 RADEON_STATECHANGE(rmesa, ctx );
1520 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
1521 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable;
1523 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE;
1524 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1529 RADEON_STATECHANGE(rmesa, ctx );
1531 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE;
1532 radeonFogfv( ctx, GL_FOG_MODE, NULL );
1534 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE;
1535 RADEON_STATECHANGE(rmesa, tcl);
1536 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
1538 radeonUpdateSpecular( ctx ); /* for PK_SPEC */
1539 _mesa_allow_light_in_model( ctx, !state );
1550 RADEON_STATECHANGE(rmesa, tcl);
1551 p = cap - GL_LIGHT0;
1553 flag = (RADEON_LIGHT_1_ENABLE |
1554 RADEON_LIGHT_1_ENABLE_AMBIENT |
1555 RADEON_LIGHT_1_ENABLE_SPECULAR);
1557 flag = (RADEON_LIGHT_0_ENABLE |
1558 RADEON_LIGHT_0_ENABLE_AMBIENT |
1559 RADEON_LIGHT_0_ENABLE_SPECULAR);
1562 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] |= flag;
1564 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
1568 update_light_colors( ctx, p );
1572 RADEON_STATECHANGE(rmesa, tcl);
1573 radeonUpdateSpecular(ctx);
1574 check_twoside_fallback( ctx );
1577 case GL_LINE_SMOOTH:
1578 RADEON_STATECHANGE( rmesa, ctx );
1580 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_LINE;
1582 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE;
1586 case GL_LINE_STIPPLE:
1587 RADEON_STATECHANGE( rmesa, ctx );
1589 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_PATTERN_ENABLE;
1591 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_PATTERN_ENABLE;
1595 case GL_COLOR_LOGIC_OP:
1596 RADEON_STATECHANGE( rmesa, ctx );
1597 if ( (ctx->Color.ColorLogicOpEnabled || (ctx->Color.BlendEnabled
1598 && ctx->Color.Blend[0].EquationRGB == GL_LOGIC_OP)) ) {
1599 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
1601 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
1606 RADEON_STATECHANGE( rmesa, tcl );
1608 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_NORMALIZE_NORMALS;
1610 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_NORMALIZE_NORMALS;
1614 case GL_POLYGON_OFFSET_POINT:
1615 RADEON_STATECHANGE( rmesa, set );
1617 rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_POINT;
1619 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_POINT;
1623 case GL_POLYGON_OFFSET_LINE:
1624 RADEON_STATECHANGE( rmesa, set );
1626 rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_LINE;
1628 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_LINE;
1632 case GL_POLYGON_OFFSET_FILL:
1633 RADEON_STATECHANGE( rmesa, set );
1635 rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_TRI;
1637 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_TRI;
1641 case GL_POLYGON_SMOOTH:
1642 RADEON_STATECHANGE( rmesa, ctx );
1644 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_POLY;
1646 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_POLY;
1650 case GL_POLYGON_STIPPLE:
1651 RADEON_STATECHANGE(rmesa, ctx );
1653 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_STIPPLE_ENABLE;
1655 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_STIPPLE_ENABLE;
1659 case GL_RESCALE_NORMAL_EXT: {
1660 GLboolean tmp = ctx->_NeedEyeCoords ? state : !state;
1661 RADEON_STATECHANGE( rmesa, tcl );
1663 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_RESCALE_NORMALS;
1665 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
1670 case GL_SCISSOR_TEST:
1671 radeon_firevertices(&rmesa->radeon);
1672 rmesa->radeon.state.scissor.enabled = state;
1673 radeonUpdateScissor( ctx );
1676 case GL_STENCIL_TEST:
1678 GLboolean hw_stencil = GL_FALSE;
1679 if (ctx->DrawBuffer) {
1680 struct radeon_renderbuffer *rrbStencil
1681 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1682 hw_stencil = (rrbStencil && rrbStencil->bo);
1686 RADEON_STATECHANGE( rmesa, ctx );
1688 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE;
1690 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE;
1693 FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state );
1698 case GL_TEXTURE_GEN_Q:
1699 case GL_TEXTURE_GEN_R:
1700 case GL_TEXTURE_GEN_S:
1701 case GL_TEXTURE_GEN_T:
1702 /* Picked up in radeonUpdateTextureState.
1704 rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
1707 case GL_COLOR_SUM_EXT:
1708 radeonUpdateSpecular ( ctx );
1717 static void radeonLightingSpaceChange( struct gl_context *ctx )
1719 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1721 RADEON_STATECHANGE( rmesa, tcl );
1723 if (RADEON_DEBUG & RADEON_STATE)
1724 fprintf(stderr, "%s %d BEFORE %x\n", __func__, ctx->_NeedEyeCoords,
1725 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
1727 if (ctx->_NeedEyeCoords)
1728 tmp = ctx->Transform.RescaleNormals;
1730 tmp = !ctx->Transform.RescaleNormals;
1733 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_RESCALE_NORMALS;
1735 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
1738 if (RADEON_DEBUG & RADEON_STATE)
1739 fprintf(stderr, "%s %d AFTER %x\n", __func__, ctx->_NeedEyeCoords,
1740 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
1743 /* =============================================================
1744 * Deferred state management - matrices, textures, other?
1748 void radeonUploadTexMatrix( r100ContextPtr rmesa,
1749 int unit, GLboolean swapcols )
1751 /* Here's how this works: on r100, only 3 tex coords can be submitted, so the
1752 vector looks like this probably: (s t r|q 0) (not sure if the last coord
1753 is hardwired to 0, could be 1 too). Interestingly, it actually looks like
1754 texgen generates all 4 coords, at least tests with projtex indicated that.
1755 So: if we need the q coord in the end (solely determined by the texture
1756 target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
1757 Additionally, if we don't have texgen but 4 tex coords submitted, we swap
1758 column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
1759 will get submitted in the "wrong", i.e. 3rd, slot.
1760 If an app submits 3 coords for 2d targets, we assume it is saving on vertex
1761 size and using the texture matrix to swap the r and q coords around (ut2k3
1762 does exactly that), so we don't need the 3rd / 4th column swap - still need
1763 the 3rd / 4th row swap of course. This will potentially break for apps which
1764 use TexCoord3x just for fun. Additionally, it will never work if an app uses
1765 an "advanced" texture matrix and relies on all 4 texcoord inputs to generate
1766 the maximum needed 3. This seems impossible to do with hw tcl on r100, and
1767 incredibly hard to detect so we can't just fallback in such a case. Assume
1768 it never happens... - rs
1771 int idx = TEXMAT_0 + unit;
1772 float *dest = ((float *)RADEON_DB_STATE( mat[idx] )) + MAT_ELT_0;
1774 struct gl_texture_unit tUnit = rmesa->radeon.glCtx.Texture.Unit[unit];
1775 GLfloat *src = rmesa->tmpmat[unit].m;
1777 rmesa->TexMatColSwap &= ~(1 << unit);
1778 if (!tUnit._Current ||
1779 (tUnit._Current->Target != GL_TEXTURE_3D &&
1780 tUnit._Current->Target != GL_TEXTURE_CUBE_MAP)) {
1782 rmesa->TexMatColSwap |= 1 << unit;
1783 /* attention some elems are swapped 2 times! */
1796 /* those last 4 are probably never used */
1803 for (i = 0; i < 2; i++) {
1807 *dest++ = src[i+12];
1809 for (i = 3; i >= 2; i--) {
1813 *dest++ = src[i+12];
1818 for (i = 0 ; i < 4 ; i++) {
1822 *dest++ = src[i+12];
1826 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
1830 static void upload_matrix( r100ContextPtr rmesa, GLfloat *src, int idx )
1832 float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
1836 for (i = 0 ; i < 4 ; i++) {
1840 *dest++ = src[i+12];
1843 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
1846 static void upload_matrix_t( r100ContextPtr rmesa, GLfloat *src, int idx )
1848 float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
1849 memcpy(dest, src, 16*sizeof(float));
1850 RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
1854 static void update_texturematrix( struct gl_context *ctx )
1856 r100ContextPtr rmesa = R100_CONTEXT( ctx );
1857 GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL];
1858 GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL];
1860 GLuint texMatEnabled = 0;
1861 rmesa->NeedTexMatrix = 0;
1862 rmesa->TexMatColSwap = 0;
1864 for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) {
1865 if (ctx->Texture.Unit[unit]._Current) {
1866 GLboolean needMatrix = GL_FALSE;
1867 if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) {
1868 needMatrix = GL_TRUE;
1869 texMatEnabled |= (RADEON_TEXGEN_TEXMAT_0_ENABLE |
1870 RADEON_TEXMAT_0_ENABLE) << unit;
1872 if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
1873 /* Need to preconcatenate any active texgen
1874 * obj/eyeplane matrices:
1876 _math_matrix_mul_matrix( &rmesa->tmpmat[unit],
1877 ctx->TextureMatrixStack[unit].Top,
1878 &rmesa->TexGenMatrix[unit] );
1881 _math_matrix_copy( &rmesa->tmpmat[unit],
1882 ctx->TextureMatrixStack[unit].Top );
1885 else if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
1886 _math_matrix_copy( &rmesa->tmpmat[unit], &rmesa->TexGenMatrix[unit] );
1887 needMatrix = GL_TRUE;
1890 rmesa->NeedTexMatrix |= 1 << unit;
1891 radeonUploadTexMatrix( rmesa, unit,
1892 !ctx->Texture.FixedFuncUnit[unit].TexGenEnabled );
1897 tpc = (texMatEnabled | rmesa->TexGenEnabled);
1899 /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */
1900 vs &= ~((RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
1901 (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
1902 (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
1904 vs |= (((tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE) <<
1905 (RADEON_TCL_TEX_0_OUTPUT_SHIFT + 3)) |
1906 ((tpc & RADEON_TEXGEN_TEXMAT_1_ENABLE) <<
1907 (RADEON_TCL_TEX_1_OUTPUT_SHIFT + 2)) |
1908 ((tpc & RADEON_TEXGEN_TEXMAT_2_ENABLE) <<
1909 (RADEON_TCL_TEX_2_OUTPUT_SHIFT + 1)));
1911 if (tpc != rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] ||
1912 vs != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]) {
1914 RADEON_STATECHANGE(rmesa, tcl);
1915 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = tpc;
1916 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = vs;
1920 GLboolean r100ValidateBuffers(struct gl_context *ctx)
1922 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1923 struct radeon_renderbuffer *rrb;
1926 radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
1928 rrb = radeon_get_colorbuffer(&rmesa->radeon);
1930 if (rrb && rrb->bo) {
1931 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo,
1932 0, RADEON_GEM_DOMAIN_VRAM);
1936 rrb = radeon_get_depthbuffer(&rmesa->radeon);
1938 if (rrb && rrb->bo) {
1939 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo,
1940 0, RADEON_GEM_DOMAIN_VRAM);
1943 for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; ++i) {
1946 if (!ctx->Texture.Unit[i]._Current)
1949 t = rmesa->state.texture.unit[i].texobj;
1953 if (t->image_override && t->bo)
1954 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->bo,
1955 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
1957 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->mt->bo,
1958 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
1961 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
1967 GLboolean radeonValidateState( struct gl_context *ctx )
1969 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1970 GLuint new_state = rmesa->radeon.NewGLState;
1972 if (new_state & _NEW_BUFFERS) {
1973 _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer);
1974 /* this updates the DrawBuffer's Width/Height if it's a FBO */
1975 _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
1976 RADEON_STATECHANGE(rmesa, ctx);
1979 if (new_state & _NEW_TEXTURE) {
1980 radeonUpdateTextureState( ctx );
1981 new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */
1984 /* we need to do a space check here */
1985 if (!r100ValidateBuffers(ctx))
1988 /* Need an event driven matrix update?
1990 if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION))
1991 upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, MODEL_PROJ );
1993 /* Need these for lighting (shouldn't upload otherwise)
1995 if (new_state & (_NEW_MODELVIEW)) {
1996 upload_matrix( rmesa, ctx->ModelviewMatrixStack.Top->m, MODEL );
1997 upload_matrix_t( rmesa, ctx->ModelviewMatrixStack.Top->inv, MODEL_IT );
2000 /* Does this need to be triggered on eg. modelview for
2001 * texgen-derived objplane/eyeplane matrices?
2003 if (new_state & _NEW_TEXTURE_MATRIX) {
2004 update_texturematrix( ctx );
2007 if (new_state & (_NEW_LIGHT|_NEW_MODELVIEW|_MESA_NEW_NEED_EYE_COORDS)) {
2008 update_light( ctx );
2011 /* emit all active clip planes if projection matrix changes.
2013 if (new_state & (_NEW_PROJECTION)) {
2014 if (ctx->Transform.ClipPlanesEnabled)
2015 radeonUpdateClipPlanes( ctx );
2019 rmesa->radeon.NewGLState = 0;
2025 static void radeonInvalidateState(struct gl_context *ctx)
2027 GLuint new_state = ctx->NewState;
2029 if (new_state & (_NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT))
2030 _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
2032 _swrast_InvalidateState( ctx, new_state );
2033 _swsetup_InvalidateState( ctx, new_state );
2034 _tnl_InvalidateState( ctx, new_state );
2035 R100_CONTEXT(ctx)->radeon.NewGLState |= new_state;
2039 /* A hack. Need a faster way to find this out.
2041 static GLboolean check_material( struct gl_context *ctx )
2043 TNLcontext *tnl = TNL_CONTEXT(ctx);
2046 for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT;
2047 i < _TNL_ATTRIB_MAT_BACK_INDEXES;
2049 if (tnl->vb.AttribPtr[i] &&
2050 tnl->vb.AttribPtr[i]->stride)
2057 static void radeonWrapRunPipeline( struct gl_context *ctx )
2059 r100ContextPtr rmesa = R100_CONTEXT(ctx);
2060 GLboolean has_material;
2063 fprintf(stderr, "%s, newstate: %x\n", __func__, rmesa->radeon.NewGLState);
2067 if (rmesa->radeon.NewGLState)
2068 if (!radeonValidateState( ctx ))
2069 FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE);
2071 has_material = (ctx->Light.Enabled && check_material( ctx ));
2074 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_TRUE );
2077 /* Run the pipeline.
2079 _tnl_run_pipeline( ctx );
2082 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_FALSE );
2086 static void radeonPolygonStipple( struct gl_context *ctx, const GLubyte *mask )
2088 r100ContextPtr r100 = R100_CONTEXT(ctx);
2091 radeon_firevertices(&r100->radeon);
2093 RADEON_STATECHANGE(r100, stp);
2095 /* Must flip pattern upside down.
2097 for ( i = 31 ; i >= 0; i--) {
2098 r100->hw.stp.cmd[3 + i] = ((GLuint *) mask)[i];
2103 /* Initialize the driver's state functions.
2104 * Many of the ctx->Driver functions might have been initialized to
2105 * software defaults in the earlier _mesa_init_driver_functions() call.
2107 void radeonInitStateFuncs( struct gl_context *ctx )
2109 ctx->Driver.UpdateState = radeonInvalidateState;
2110 ctx->Driver.LightingSpaceChange = radeonLightingSpaceChange;
2112 ctx->Driver.DrawBuffer = radeonDrawBuffer;
2113 ctx->Driver.ReadBuffer = radeonReadBuffer;
2114 ctx->Driver.CopyPixels = _mesa_meta_CopyPixels;
2115 ctx->Driver.DrawPixels = _mesa_meta_DrawPixels;
2116 ctx->Driver.ReadPixels = radeonReadPixels;
2118 ctx->Driver.AlphaFunc = radeonAlphaFunc;
2119 ctx->Driver.BlendEquationSeparate = radeonBlendEquationSeparate;
2120 ctx->Driver.BlendFuncSeparate = radeonBlendFuncSeparate;
2121 ctx->Driver.ClipPlane = radeonClipPlane;
2122 ctx->Driver.ColorMask = radeonColorMask;
2123 ctx->Driver.CullFace = radeonCullFace;
2124 ctx->Driver.DepthFunc = radeonDepthFunc;
2125 ctx->Driver.DepthMask = radeonDepthMask;
2126 ctx->Driver.DepthRange = radeonDepthRange;
2127 ctx->Driver.Enable = radeonEnable;
2128 ctx->Driver.Fogfv = radeonFogfv;
2129 ctx->Driver.FrontFace = radeonFrontFace;
2130 ctx->Driver.LightModelfv = radeonLightModelfv;
2131 ctx->Driver.Lightfv = radeonLightfv;
2132 ctx->Driver.LineStipple = radeonLineStipple;
2133 ctx->Driver.LineWidth = radeonLineWidth;
2134 ctx->Driver.LogicOpcode = radeonLogicOpCode;
2135 ctx->Driver.PolygonMode = radeonPolygonMode;
2136 ctx->Driver.PolygonOffset = radeonPolygonOffset;
2137 ctx->Driver.PolygonStipple = radeonPolygonStipple;
2138 ctx->Driver.RenderMode = radeonRenderMode;
2139 ctx->Driver.Scissor = radeonScissor;
2140 ctx->Driver.ShadeModel = radeonShadeModel;
2141 ctx->Driver.StencilFuncSeparate = radeonStencilFuncSeparate;
2142 ctx->Driver.StencilMaskSeparate = radeonStencilMaskSeparate;
2143 ctx->Driver.StencilOpSeparate = radeonStencilOpSeparate;
2144 ctx->Driver.Viewport = radeonViewport;
2146 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange = radeonUpdateMaterial;
2147 TNL_CONTEXT(ctx)->Driver.RunPipeline = radeonWrapRunPipeline;