2 * Copyright (c) 2008 Juan Romero Pardines
3 * Copyright (c) 2008 Mark Kettenis
4 * Copyright (c) 2009 Michael Lorenz
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <sys/param.h>
20 #include <sys/ioctl.h>
22 #include <sys/types.h>
29 #include <machine/sysarch.h>
30 #include <machine/mtrr.h>
32 /* NetBSD 5.x and newer */
33 #define netbsd_set_mtrr(mr, num) _X86_SYSARCH_L(set_mtrr)(mr, num)
35 /* NetBSD 4.x and older */
37 #define netbsd_set_mtrr(mr, num) i386_set_mtrr((mr), (num))
40 #define netbsd_set_mtrr(mr, num) x86_64_set_mtrr((mr), (num))
45 #include <dev/pci/pcidevs.h>
46 #include <dev/pci/pciio.h>
47 #include <dev/pci/pcireg.h>
58 #include <dev/wscons/wsconsio.h>
60 #include "pciaccess.h"
61 #include "pciaccess_private.h"
63 typedef struct _pcibus {
64 int fd; /* /dev/pci* */
65 int num; /* bus number */
66 int maxdevs; /* maximum number of devices */
69 static PciBus buses[32]; /* indexed by pci_device.domain */
70 static int nbuses = 0; /* number of buses found */
73 * NetBSD's userland has a /dev/pci* entry for each bus but userland has no way
74 * to tell if a bus is a subordinate of another one or if it's on a different
75 * host bridge. On some architectures ( macppc for example ) all root buses have
76 * bus number 0 but on sparc64 for example the two roots in an Ultra60 have
77 * different bus numbers - one is 0 and the other 128.
78 * With each /dev/pci* we can map everything on the same root and we can also
79 * see all devices on the same root, trying to do that causes problems though:
80 * - since we can't tell which /dev/pci* is a subordinate we would find some
81 * devices more than once
82 * - we would have to guess subordinate bus numbers which is a waste of time
83 * since we can ask each /dev/pci* for its bus number so we can scan only the
84 * buses we know exist, not all 256 which may exist in each domain.
85 * - some bus_space_mmap() methods may limit mappings to address ranges which
86 * belong to known devices on that bus only.
87 * Each host bridge may or may not have its own IO range, to avoid guesswork
88 * here each /dev/pci* will let userland map its appropriate IO range at
89 * PCI_MAGIC_IO_RANGE if defined in <machine/param.h>
90 * With all this we should be able to use any PCI graphics device on any PCI
91 * bus on any architecture as long as Xorg has a driver, without allowing
92 * arbitrary mappings via /dev/mem and without userland having to know or care
93 * about translating bus addresses to physical addresses or the other way
98 pci_read(int domain, int bus, int dev, int func, uint32_t reg, uint32_t *val)
102 if ((domain < 0) || (domain > nbuses))
105 if (pcibus_conf_read(buses[domain].fd, (unsigned int)bus,
106 (unsigned int)dev, (unsigned int)func, reg, &rval) == -1)
115 pci_write(int domain, int bus, int dev, int func, uint32_t reg, uint32_t val)
118 if ((domain < 0) || (domain > nbuses))
121 return pcibus_conf_write(buses[domain].fd, (unsigned int)bus,
122 (unsigned int)dev, (unsigned int)func, reg, val);
126 pci_nfuncs(int domain, int bus, int dev)
130 if ((domain < 0) || (domain > nbuses))
133 if (pci_read(domain, bus, dev, 0, PCI_BHLC_REG, &hdr) != 0)
136 return (PCI_HDRTYPE_MULTIFN(hdr) ? 8 : 1);
141 pci_device_netbsd_map_range(struct pci_device *dev,
142 struct pci_device_mapping *map)
152 if (map->flags & PCI_DEV_MAP_FLAG_WRITABLE)
154 map->memory = mmap(NULL, (size_t)map->size, prot, MAP_SHARED,
155 buses[dev->domain].fd, (off_t)map->base);
156 if (map->memory == MAP_FAILED)
160 memset(&m, 0, sizeof(m));
162 /* No need to set an MTRR if it's the default mode. */
163 if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
164 (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)) {
166 m.flags = MTRR_VALID | MTRR_PRIVATE;
169 if (map->flags & PCI_DEV_MAP_FLAG_CACHABLE)
170 m.type = MTRR_TYPE_WB;
171 if (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)
172 m.type = MTRR_TYPE_WC;
174 if ((netbsd_set_mtrr(&m, &n)) == -1) {
175 fprintf(stderr, "mtrr set failed: %s\n",
185 pci_device_netbsd_unmap_range(struct pci_device *dev,
186 struct pci_device_mapping *map)
192 memset(&m, 0, sizeof(m));
194 if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
195 (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)) {
199 m.type = MTRR_TYPE_UC;
200 (void)netbsd_set_mtrr(&m, &n);
204 return pci_device_generic_unmap_range(dev, map);
208 pci_device_netbsd_read(struct pci_device *dev, void *data,
209 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read)
215 size_t toread = MIN(size, 4 - (offset & 0x3));
217 reg = (u_int)(offset & ~0x3);
219 if ((pcibus_conf_read(buses[dev->domain].fd,
220 (unsigned int)dev->bus, (unsigned int)dev->dev,
221 (unsigned int)dev->func, reg, &rval)) == -1)
224 rval = htole32(rval);
225 rval >>= ((offset & 0x3) * 8);
227 memcpy(data, &rval, toread);
230 data = (char *)data + toread;
232 *bytes_read += toread;
239 pci_device_netbsd_write(struct pci_device *dev, const void *data,
240 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written)
244 if ((offset % 4) != 0 || (size % 4) != 0)
250 memcpy(&val, data, 4);
252 if ((pcibus_conf_write(buses[dev->domain].fd,
253 (unsigned int)dev->bus, (unsigned int)dev->dev,
254 (unsigned int)dev->func, reg, val)) == -1)
258 data = (const char *)data + 4;
266 #if defined(WSDISPLAYIO_GET_BUSID)
268 pci_device_netbsd_boot_vga(struct pci_device *dev)
271 struct wsdisplayio_bus_id busid;
274 fd = open("/dev/ttyE0", O_RDONLY);
276 fprintf(stderr, "failed to open /dev/ttyE0: %s\n",
281 ret = ioctl(fd, WSDISPLAYIO_GET_BUSID, &busid);
284 fprintf(stderr, "ioctl WSDISPLAYIO_GET_BUSID failed: %s\n",
289 if (busid.bus_type != WSDISPLAYIO_BUS_PCI)
292 if (busid.ubus.pci.domain != dev->domain)
294 if (busid.ubus.pci.bus != dev->bus)
296 if (busid.ubus.pci.device != dev->dev)
298 if (busid.ubus.pci.function != dev->func)
306 pci_system_netbsd_destroy(void)
310 for (i = 0; i < nbuses; i++) {
318 pci_device_netbsd_probe(struct pci_device *device)
320 struct pci_device_private *priv =
321 (struct pci_device_private *)(void *)device;
322 struct pci_mem_region *region;
323 uint64_t reg64, size64;
324 uint32_t bar, reg, size;
325 int bus, dev, func, err, domain;
327 domain = device->domain;
332 /* Enable the device if necessary */
333 err = pci_read(domain, bus, dev, func, PCI_COMMAND_STATUS_REG, ®);
336 if ((reg & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) !=
337 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
338 reg |= PCI_COMMAND_IO_ENABLE |
339 PCI_COMMAND_MEM_ENABLE |
340 PCI_COMMAND_MASTER_ENABLE;
341 err = pci_write(domain, bus, dev, func, PCI_COMMAND_STATUS_REG,
347 err = pci_read(domain, bus, dev, func, PCI_BHLC_REG, ®);
351 priv->header_type = PCI_HDRTYPE_TYPE(reg);
352 if (priv->header_type != 0)
355 region = device->regions;
356 for (bar = PCI_MAPREG_START; bar < PCI_MAPREG_END;
357 bar += sizeof(uint32_t), region++) {
358 err = pci_read(domain, bus, dev, func, bar, ®);
362 /* Probe the size of the region. */
363 err = pci_write(domain, bus, dev, func, bar, (unsigned int)~0);
366 pci_read(domain, bus, dev, func, bar, &size);
367 pci_write(domain, bus, dev, func, bar, reg);
369 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
371 region->base_addr = PCI_MAPREG_IO_ADDR(reg);
372 region->size = PCI_MAPREG_IO_SIZE(size);
374 if (PCI_MAPREG_MEM_PREFETCHABLE(reg))
375 region->is_prefetchable = 1;
376 switch(PCI_MAPREG_MEM_TYPE(reg)) {
377 case PCI_MAPREG_MEM_TYPE_32BIT:
378 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
379 region->base_addr = PCI_MAPREG_MEM_ADDR(reg);
380 region->size = PCI_MAPREG_MEM_SIZE(size);
382 case PCI_MAPREG_MEM_TYPE_64BIT:
388 bar += sizeof(uint32_t);
390 err = pci_read(domain, bus, dev, func, bar, ®);
393 reg64 |= (uint64_t)reg << 32;
395 err = pci_write(domain, bus, dev, func, bar,
399 pci_read(domain, bus, dev, func, bar, &size);
400 pci_write(domain, bus, dev, func, bar,
401 (unsigned int)(reg64 >> 32));
402 size64 |= (uint64_t)size << 32;
405 (unsigned long)PCI_MAPREG_MEM64_ADDR(reg64);
407 (unsigned long)PCI_MAPREG_MEM64_SIZE(size64);
414 /* Probe expansion ROM if present */
415 err = pci_read(domain, bus, dev, func, PCI_MAPREG_ROM, ®);
419 err = pci_write(domain, bus, dev, func, PCI_MAPREG_ROM,
420 (uint32_t)(~PCI_MAPREG_ROM_ENABLE));
423 pci_read(domain, bus, dev, func, PCI_MAPREG_ROM, &size);
424 pci_write(domain, bus, dev, func, PCI_MAPREG_ROM, reg);
425 if ((reg & PCI_MAPREG_MEM_ADDR_MASK) != 0) {
426 priv->rom_base = reg & PCI_MAPREG_MEM_ADDR_MASK;
427 device->rom_size = -(size & PCI_MAPREG_MEM_ADDR_MASK);
435 * Read a VGA rom using the 0xc0000 mapping.
437 * This function should be extended to handle access through PCI resources,
438 * which should be more reliable when available.
441 pci_device_netbsd_read_rom(struct pci_device *dev, void *buffer)
443 struct pci_device_private *priv = (struct pci_device_private *)(void *)dev;
447 uint32_t bios_val, command_val;
450 if (((priv->base.device_class >> 16) & 0xff) != PCI_CLASS_DISPLAY ||
451 ((priv->base.device_class >> 8) & 0xff) != PCI_SUBCLASS_DISPLAY_VGA)
454 if (priv->rom_base == 0) {
455 #if defined(__amd64__) || defined(__i386__)
457 * We need a way to detect when this isn't the console and reject
458 * this request outright.
467 rom_base = priv->rom_base;
468 rom_size = dev->rom_size;
470 if ((pcibus_conf_read(buses[dev->domain].fd, (unsigned int)dev->bus,
471 (unsigned int)dev->dev, (unsigned int)dev->func,
472 PCI_COMMAND_STATUS_REG, &command_val)) == -1)
474 if ((command_val & PCI_COMMAND_MEM_ENABLE) == 0) {
475 if ((pcibus_conf_write(buses[dev->domain].fd,
476 (unsigned int)dev->bus, (unsigned int)dev->dev,
477 (unsigned int)dev->func, PCI_COMMAND_STATUS_REG,
478 command_val | PCI_COMMAND_MEM_ENABLE)) == -1)
481 if ((pcibus_conf_read(buses[dev->domain].fd, (unsigned int)dev->bus,
482 (unsigned int)dev->dev, (unsigned int)dev->func,
483 PCI_MAPREG_ROM, &bios_val)) == -1)
485 if ((bios_val & PCI_MAPREG_ROM_ENABLE) == 0) {
486 if ((pcibus_conf_write(buses[dev->domain].fd,
487 (unsigned int)dev->bus,
488 (unsigned int)dev->dev, (unsigned int)dev->func,
489 PCI_MAPREG_ROM, bios_val | PCI_MAPREG_ROM_ENABLE)) == -1)
494 fprintf(stderr, "Using rom_base = 0x%lx 0x%lx (pci_rom=%d)\n",
495 (long)rom_base, (long)rom_size, pci_rom);
497 bios = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, buses[dev->domain].fd,
499 if (bios == MAP_FAILED) {
504 memcpy(buffer, bios, rom_size);
506 munmap(bios, rom_size);
509 if ((command_val & PCI_COMMAND_MEM_ENABLE) == 0) {
510 if ((pcibus_conf_write(buses[dev->domain].fd,
511 (unsigned int)dev->bus,
512 (unsigned int)dev->dev, (unsigned int)dev->func,
513 PCI_COMMAND_STATUS_REG, command_val)) == -1)
516 if ((bios_val & PCI_MAPREG_ROM_ENABLE) == 0) {
517 if ((pcibus_conf_write(buses[dev->domain].fd,
518 (unsigned int)dev->bus,
519 (unsigned int)dev->dev, (unsigned int)dev->func,
520 PCI_MAPREG_ROM, bios_val)) == -1)
528 static const struct pci_system_methods netbsd_pci_methods = {
529 .destroy = pci_system_netbsd_destroy,
530 .destroy_device = NULL,
531 .read_rom = pci_device_netbsd_read_rom,
532 .probe = pci_device_netbsd_probe,
533 .map_range = pci_device_netbsd_map_range,
534 .unmap_range = pci_device_netbsd_unmap_range,
535 .read = pci_device_netbsd_read,
536 .write = pci_device_netbsd_write,
537 .fill_capabilities = pci_fill_capabilities_generic,
538 #if defined(WSDISPLAYIO_GET_BUSID)
539 .boot_vga = pci_device_netbsd_boot_vga,
546 pci_system_netbsd_create(void)
548 struct pci_device_private *device;
549 int bus, dev, func, ndevs, nfuncs, domain, pcifd;
551 char netbsd_devname[32];
552 struct pciio_businfo businfo;
554 pci_sys = calloc(1, sizeof(struct pci_system));
556 pci_sys->methods = &netbsd_pci_methods;
560 snprintf(netbsd_devname, 32, "/dev/pci%d", nbuses);
561 pcifd = open(netbsd_devname, O_RDWR | O_CLOEXEC);
563 ioctl(pcifd, PCI_IOC_BUSINFO, &businfo);
564 buses[nbuses].fd = pcifd;
565 buses[nbuses].num = bus = businfo.busno;
566 buses[nbuses].maxdevs = businfo.maxdevs;
569 for (dev = 0; dev < businfo.maxdevs; dev++) {
570 nfuncs = pci_nfuncs(domain, bus, dev);
571 for (func = 0; func < nfuncs; func++) {
572 if (pci_read(domain, bus, dev, func, PCI_ID_REG,
575 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
576 PCI_VENDOR(reg) == 0)
582 snprintf(netbsd_devname, 32, "/dev/pci%d", nbuses);
583 pcifd = open(netbsd_devname, O_RDWR);
586 pci_sys->num_devices = ndevs;
587 pci_sys->devices = calloc(ndevs, sizeof(struct pci_device_private));
588 if (pci_sys->devices == NULL) {
591 for (i = 0; i < nbuses; i++)
597 device = pci_sys->devices;
598 for (domain = 0; domain < nbuses; domain++) {
599 bus = buses[domain].num;
600 for (dev = 0; dev < buses[domain].maxdevs; dev++) {
601 nfuncs = pci_nfuncs(domain, bus, dev);
602 for (func = 0; func < nfuncs; func++) {
603 if (pci_read(domain, bus, dev, func,
604 PCI_ID_REG, ®) != 0)
606 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
607 PCI_VENDOR(reg) == 0)
610 device->base.domain = domain;
611 device->base.bus = bus;
612 device->base.dev = dev;
613 device->base.func = func;
614 device->base.vendor_id = PCI_VENDOR(reg);
615 device->base.device_id = PCI_PRODUCT(reg);
617 if (pci_read(domain, bus, dev, func,
618 PCI_CLASS_REG, ®) != 0)
621 device->base.device_class =
622 PCI_INTERFACE(reg) | PCI_CLASS(reg) << 16 |
623 PCI_SUBCLASS(reg) << 8;
624 device->base.revision = PCI_REVISION(reg);
626 if (pci_read(domain, bus, dev, func,
627 PCI_SUBSYS_ID_REG, ®) != 0)
630 device->base.subvendor_id = PCI_VENDOR(reg);
631 device->base.subdevice_id = PCI_PRODUCT(reg);