2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
32 * g1-g3 static parameters (constant)
33 * g16-g24 payload for write message
35 define(`ORIG', `g0.4<2,2,1>UW')
36 define(`ORIGX', `g0.4<0,1,0>UW')
37 define(`ORIGY', `g0.6<0,1,0>UW')
39 define(`ALPHA', `g1.3<0,1,0>UB')
41 define(`Y', `g1.2<0,1,0>UB')
43 define(`CR', `g1.1<0,1,0>UB')
45 define(`CB', `g1.0<0,1,0>UB')
46 define(`CBCR', `g1.0<0,1,0>UW')
50 define(`CBCR_BTI', `2')
54 mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
57 shl(2) g16.0<1>UD ORIG 4:w {align1};
59 mov(1) g16.8<1>UD 0x000f000fUD {align1};
61 mov(4) g17.0<1>UB Y {align1};
62 mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
63 mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
64 mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
65 mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
67 * write(p0, p1, p2, p3)
68 * p0: binding table index
69 * p1: message control, default is 0,
70 * p2: message type, 10 is media_block_write
71 * p3: cache type, 12 is data cache data port 1
73 send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
76 shl(1) g16.0<1>UD ORIGX 3:w {align1};
77 shl(1) g16.4<1>UD ORIGY 3:w {align1};
80 mov(1) g16.8<1>UD 0x00070007UD {align1};
82 mov(4) g17.0<1>UB CB {align1};
83 mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
86 * write(p0, p1, p2, p3)
87 * p0: binding table index
88 * p1: message control, default is 0,
89 * p2: message type, 10 is media_block_write
90 * p3: cache type, 12 is data cache data port 1
92 send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
95 mov(4) g17.0<1>UB CR {align1};
96 mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
99 * write(p0, p1, p2, p3)
100 * p0: binding table index
101 * p1: message control, default is 0,
102 * p2: message type, 10 is media_block_write
103 * p3: cache type, 12 is data cache data port 1
105 send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
108 mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
109 send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};