src/shaders/vme/vme75.inc

   1 /*
   2  * Copyright © <2010>, Intel Corporation.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25 // Modual name: ME_header.inc
  26 //
  27 // Global symbols define
  28 //
  29
  30 /*
  31  * Constant
  32  */
  33 define(`VME_MESSAGE_TYPE_INTER',        `1')
  34 define(`VME_MESSAGE_TYPE_INTRA',        `2')
  35 define(`VME_MESSAGE_TYPE_MIXED',        `3')
  36
  37 define(`VME_SIC_MESSAGE_TYPE',        `1')
  38 define(`VME_IME_MESSAGE_TYPE',        `2')
  39 define(`VME_FBR_MESSAGE_TYPE',        `3')
  40
  41 define(`BLOCK_32X1',                    `0x0000001F')
  42 define(`BLOCK_4X16',                    `0x000F0003')
  43 define(`BLOCK_8X4',                     `0x00070003')
  44
  45 define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
  46 define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
  47 define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
  48
  49 define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
  50 define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
  51 define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
  52 define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
  53
  54 define(`BIND_IDX_VME',                  `0')
  55 define(`BIND_IDX_VME_REF0',             `1')
  56 define(`BIND_IDX_VME_REF1',             `2')
  57 define(`BIND_IDX_OUTPUT',               `3')
  58 define(`BIND_IDX_INEP',                 `4')
  59 define(`BIND_IDX_COST',                 `8')
  60
  61 define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
  62 define(`SUB_PEL_MODE_HALF',             `0x00001000')
  63 define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
  64
  65 define(`INTER_SAD_NONE',                `0x00000000')
  66 define(`INTER_SAD_HAAR',                `0x00200000')
  67
  68 define(`INTRA_SAD_NONE',                `0x00000000')
  69 define(`INTRA_SAD_HAAR',                `0x00800000')
  70
  71 define(`INTER_PART_MASK',               `0x00000000')
  72
  73 define(`SEARCH_CTRL_SINGLE',            `0x00000000')
  74 define(`SEARCH_CTRL_DUAL_START',        `0x00000100')
  75 define(`SEARCH_CTRL_DUAL_RECORD',       `0x00000300')
  76 define(`SEARCH_CTRL_DUAL_REFERENCE',    `0x00000700')
  77
  78 define(`REF_REGION_SIZE',               `0x2830:UW')
  79 define(`MIN_REF_REGION_SIZE',           `0x2020:UW')
  80 define(`DREF_REGION_SIZE',              `0x2020:UW')
  81
  82 define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
  83 define(`MAX_NUM_MV',                    `0x00000020')
  84 define(`FB_PRUNING_ENABLE',             `0x40000000')
  85
  86 define(`SEARCH_PATH_LEN',               `0x00003030')
  87 define(`START_CENTER',                  `0x30000000')
  88
  89 define(`ADAPTIVE_SEARCH_ENABLE',        `0x00000002')
  90 define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
  91
  92 define(`INTER_VME_OUTPUT_IN_OWS',       `10')
  93 define(`INTER_VME_OUTPUT_MV_IN_OWS',    `8')
  94
  95 define(`INTRAMBFLAG_MASK',              `0x00002000')
  96 define(`MVSIZE_UW_BASE',                `0x0040')
  97 define(`MFC_MV32_BIT_SHIFT',            `5')
  98 define(`CBP_DC_YUV_UW',                 `0x000E')
  99
 100 define(`DC_HARR_ENABLE',                `0x0000')
 101 define(`DC_HARR_DISABLE',               `0x0020')
 102
 103 define(`MV32_BIT_MASK',                 `0x0020')
 104 define(`MV32_BIT_SHIFT',                `5')
 105
 106 define(`OBW_CACHE_TYPE',                `10')
 107
 108
 109 define(`OBW_MESSAGE_TYPE',              `8')
 110
 111 define(`OBW_BIND_IDX',                  `BIND_IDX_OUTPUT')
 112
 113 define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
 114 define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
 115 define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
 116 define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
 117 define(`OBW_CONTROL_8',                 `4')    /* 8 OWords */
 118
 119 define(`FBR_BME_ENABLE',                 `0x00000000')
 120 define(`FBR_BME_DISABLE',                `0x00040000')
 121
 122 define(`OBW_WRITE_COMMIT_CATEGORY',     `0')    /* category on Ivybridge */
 123
 124
 125 define(`OBW_HEADER_PRESENT',            `1')
 126
 127 /* GRF registers
 128  * r0 header
 129  * r1~r4 constant buffer (reserved)
 130  * r5 inline data
 131  * r6~r11 reserved
 132  * r12 write back of VME message
 133  * r13 write back of Oword Block Write
 134  */
 135 /*
 136  * GRF 0 -- header
 137  */
 138 define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
 139
 140 /*
 141  * GRF 1~4 -- Constant Buffer (reserved)
 142  */
 143
 144 /*
 145  * GRF 5 -- inline data
 146  */
 147 define(`inline_reg0',           `r5')
 148 define(`w_in_mb_uw',            `inline_reg0.2')
 149 define(`orig_xy_ub',            `inline_reg0.0')
 150 define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */
 151 define(`orig_y_ub',             `inline_reg0.1')
 152 define(`transform_8x8_ub',      `inline_reg0.4')
 153 define(`input_mb_intra_ub',     `inline_reg0.5')
 154 define(`num_macroblocks',       `inline_reg0.6')
 155 define(`quality_level_ub',      `inline_reg0.7')
 156
 157 define(`qp_ub',                 `inline_reg0.8')
 158
 159 /*
 160  * GRF 6~11 -- reserved
 161  */
 162
 163 /*
 164  * GRF 12~15 -- write back for VME message
 165  */
 166 define(`vme_wb',                `r12')
 167 define(`vme_wb0',               `r12')
 168 define(`vme_wb1',               `r13')
 169 define(`vme_wb2',               `r14')
 170 define(`vme_wb3',               `r15')
 171 define(`vme_wb4',               `r16')
 172 define(`vme_wb5',               `r17')
 173 define(`vme_wb6',               `r18')
 174 define(`vme_ime_wb7',           `r19')
 175 define(`vme_ime_wb8',           `r20')
 176 define(`vme_ime_wb9',           `r21')
 177 define(`vme_ime_wb10',          `r22')
 178
 179
 180 /*
 181  * GRF 24 -- write for VME output message
 182  */
 183 define(`obw_wb',                `null<1>:W')
 184 define(`obw_wb_length',         `0')
 185
 186
 187 /*
 188  * GRF 28~30 -- Intra Neighbor Edge Pixels
 189  */
 190 define(`INEP_ROW',              `r28')
 191 define(`INEP_COL0',             `r29')
 192 define(`INEP_COL1',             `r30')
 193
 194 /*
 195  * GRF 48~50 -- Chroma Neighbor Edge Pixels
 196  */
 197 define(`CHROMA_ROW',              `r48')
 198 define(`CHROMA_COL',              `r49')
 199
 200 /*
 201  * temporary registers
 202  */
 203 define(`tmp_reg0',              `r32')
 204 define(`read0_header',          `tmp_reg0')
 205 define(`tmp_reg1',              `r33')
 206 define(`read1_header',          `tmp_reg1')
 207 define(`tmp_reg2',              `r34')
 208 define(`vme_m0',                `tmp_reg2')
 209 define(`tmp_reg3',              `r35')
 210 define(`vme_m1',                `tmp_reg3')
 211 define(`intra_flag',            `vme_m1.28')
 212 define(`intra_part_mask_ub',    `vme_m1.28')
 213 define(`mb_intra_struct_ub',    `vme_m1.29')
 214 define(`tmp_reg4',              `r36')
 215 define(`obw_m0',                `tmp_reg4')
 216 define(`tmp_reg5',              `r37')
 217 define(`obw_m1',                `tmp_reg5')
 218 define(`tmp_reg6',              `r38')
 219 define(`obw_m2',                `tmp_reg6')
 220 define(`tmp_reg7',              `r39')
 221 define(`obw_m3',                `tmp_reg7')
 222 define(`tmp_reg8',              `r40')
 223 define(`obw_m4',                `tmp_reg8')
 224 define(`tmp_reg9',              `r41')
 225 define(`tmp_x_w',               `tmp_reg9.0')
 226 define(`tmp_rega',              `r42')
 227 define(`tmp_ud0',               `tmp_rega.0')
 228 define(`tmp_ud1',               `tmp_rega.4')
 229 define(`tmp_ud2',               `tmp_rega.8')
 230 define(`tmp_ud3',               `tmp_rega.12')
 231 define(`tmp_uw0',               `tmp_rega.0')
 232 define(`tmp_uw1',               `tmp_rega.2')
 233 define(`tmp_uw2',               `tmp_rega.4')
 234 define(`tmp_uw3',               `tmp_rega.6')
 235 define(`tmp_uw4',               `tmp_rega.8')
 236 define(`tmp_uw5',               `tmp_rega.10')
 237 define(`tmp_uw6',               `tmp_rega.12')
 238 define(`tmp_uw7',               `tmp_rega.14')
 239
 240 define(`vme_m2',                `r43')
 241 define(`vme_cost_wb',                `r44')
 242 /*
 243  * MRF registers
 244  */
 245
 246 define(`msg_ind',               `64')
 247 define(`msg_reg0',              `r64')
 248 define(`msg_reg1',              `r65')
 249 define(`msg_reg2',              `r66')
 250 define(`msg_reg3',              `r67')
 251 define(`msg_reg4',              `r68')
 252 define(`msg_reg5',              `r69')
 253 define(`msg_reg6',              `r70')
 254 define(`msg_reg7',              `r71')
 255 define(`msg_reg8',              `r72')
 256 define(`msg_reg9',              `r73')
 257
 258 define(`ts_msg_ind',               `112')
 259 define(`ts_msg_reg0',               `r112')
 260 /*
 261  * VME message payload
 262  */
 263
 264 define(`vme_intra_wb_length',   `1')
 265 define(`vme_wb_length',         `7')
 266 define(`sic_vme_msg_length',    `7')
 267 define(`fbr_vme_msg_length',    `7')
 268 define(`ime_vme_msg_length',    `5')
 269
 270 define(`vme_msg_ind',           `msg_ind')
 271 define(`vme_msg_0',             `msg_reg0')
 272 define(`vme_msg_1',             `msg_reg1')
 273 define(`vme_msg_2',             `msg_reg2')
 274
 275 define(`vme_msg_3',             `msg_reg3')
 276 define(`vme_msg_4',             `msg_reg4')
 277
 278
 279 define(`vme_msg_5',             `msg_reg5')
 280 define(`vme_msg_6',             `msg_reg6')
 281 define(`vme_msg_7',             `msg_reg7')
 282 define(`vme_msg_8',             `msg_reg8')
 283 define(`vme_msg_9',             `msg_reg9')
 284
 285 define(`BIND_IDX_CBCR',                 `6')
 286
 287
 288 define(`LUMA_CHROMA_MODE',      `0x0')
 289 define(`LUMA_INTRA_MODE',       `0x1')
 290 define(`LUMA_INTRA_DISABLE',    `0x2')
 291
 292 define(`RETURN_REG',              `r127.0')
 293 define(`RET_ARG',              `r127.4')
 294
 295 /* Now at most two registers are used for input parameter */
 296 define(`INPUT_ARG0',              `r125')
 297 define(`INPUT_ARG1',              `r126')
 298
 299 /* Two temporal registers are used in the function */
 300 define(`TEMP_VAR0',              `r123')
 301 define(`TEMP_VAR1',              `r124')
 302
 303
 304 define(`OBR_MESSAGE_TYPE',              `0')
 305 define(`OBR_CACHE_TYPE',                `10')
 306 define(`OBR_BIND_IDX',                  `BIND_IDX_OUTPUT')
 307
 308 define(`OBR_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
 309 define(`OBR_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
 310 define(`OBR_CONTROL_2',                 `2')    /* 2 OWords */
 311 define(`OBR_CONTROL_4',                 `3')    /* 4 OWords */
 312 define(`OBR_CONTROL_8',                 `4')    /* 8 OWords */
 313 define(`OBR_WRITE_COMMIT_CATEGORY',     `0')    /* category on SNB+ for Data port */
 314 define(`OBR_HEADER_PRESENT',            `1')
 315
 316 define(`mb_hwdep',           `r5.6')
 317 define(`MB_AVAIL',              `1:d')
 318 define(`MB_PRED_FLAG',          `1:w')
 319
 320 define(`mb_pred_mode',          `r85')
 321 define(`mb_mvp_ref',            `r86')
 322 define(`mba_result',            `r87')
 323 define(`mbb_result',            `r88')
 324 define(`mbc_result',            `r89')
 325 define(`mb_ind',                `90')
 326 define(`mb_msg0',               `r90')
 327 define(`mb_wb',                 `r91')
 328 define(`mb_intra_wb',           `r91')
 329 define(`mb_inter_wb',           `r92')
 330 define(`mb_mv0',                `r93')
 331 define(`mb_mv1',                `r94')
 332 define(`mb_mv2',                `r95')
 333 define(`mb_mv3',                `r96')
 334 define(`mb_ref',                `r97')
 335 define(`mb_ref_win',            `r84')
 336
 337 define(`PRED_L0',               `0x0':uw)
 338 define(`PRED_L1',               `0x1':uw)
 339 define(`PRED_BI',               `0x2':uw)
 340 define(`PRED_DIRECT',           `0x3':uw)
 341 define(`PRED_MASK',             `0x3':uw)
 342
 343 /* The MAX search len per reference is 16 */
 344 define(`DSEARCH_PATH_LEN',               `0x00001212')
 345 define(`BI_WEIGHT',             `0x20':uw)
 346 define(`DSTART_CENTER',                  `0x00000000')
 347 define(`INTER_MASK',                    `0x03')
 348 define(`INTER_16X16MODE',               `0x0')
 349 define(`INTER_16X8MODE',                `0x01')
 350 define(`INTER_8X16MODE',                `0x02')
 351 define(`INTER_8X8MODE',                 `0x03')
 352 define(`INTER_BLOCK0',                  `0x0')
 353 define(`INTER_BLOCK1',                  `0x1')
 354 define(`INTER_BLOCK2',                  `0x2')
 355 define(`INTER_BLOCK3',                  `0x3')
 356 define(`INTER_16X8MODE',                `0x01')
 357 define(`INTER_8X16MODE',                `0x02')
 358
 359 define(`OBR_MESSAGE_FENCE',              `7')
 360 define(`OBR_MF_NOCOMMIT',                `0')
 361 define(`OBR_MF_COMMIT',                  `0x20')
 362
 363 define(`DEFAULT_QUALITY_LEVEL',           `0x01')
 364 define(`HIGH_QUALITY_LEVEL',              `DEFAULT_QUALITY_LEVEL')
 365 define(`LOW_QUALITY_LEVEL',               `0x02')