2 * Copyright (c) 2007, Sun Microsystems, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
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10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 * Solaris devfs interfaces
35 #include <sys/types.h>
43 #include <libdevinfo.h>
44 #include "pci_tools.h"
46 #include "pciaccess.h"
47 #include "pciaccess_private.h"
49 #define PCI_NEXUS_1 "/devices/pci@0,0:reg"
50 #define MAX_DEVICES 256
51 #define CELL_NUMS_1275 (sizeof(pci_regspec_t)/sizeof(uint_t))
53 uint8_t bytes[16 * sizeof (uint32_t)];
57 typedef struct i_devnode {
64 static int root_fd = -1;
65 static int xsvc_fd = -1;
67 * Read config space in native processor endianness. Endian-neutral
68 * processing can then take place. On big endian machines, MSB and LSB
69 * of little endian data end up switched if read as little endian.
70 * They are in correct order if read as big endian.
73 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
75 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
77 #error "ISA is neither __sparc nor __x86"
81 * Identify problematic southbridges. These have device id 0x5249 and
82 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
83 * Values are little endian, so they are reversed for SPARC.
85 * Check for these southbridges on all architectures, as the issue is a
86 * southbridge issue, independent of processor.
88 * If one of these is found during probing, skip probing other devs/funcs on
89 * the rest of the bus, since the southbridge and all devs underneath will
90 * otherwise disappear.
92 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
93 #define U45_SB_DEVID_VID 0xb9104952
94 #define U45_SB_CLASS_RID 0x00000406
96 #define U45_SB_DEVID_VID 0x524910b9
97 #define U45_SB_CLASS_RID 0x06040000
105 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
108 static int pci_device_solx_devfs_probe( struct pci_device * dev );
110 static int pci_device_solx_devfs_map_region( struct pci_device * dev,
111 unsigned region, int write_enable );
113 static int pci_device_solx_devfs_unmap_region( struct pci_device * dev,
116 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
117 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
119 static int pci_device_solx_devfs_write( struct pci_device * dev,
120 const void * data, pciaddr_t offset, pciaddr_t size,
121 pciaddr_t * bytes_wrtten );
124 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys);
127 do_probe(int fd, struct pci_system *pci_sys);
130 pci_system_solx_devfs_destroy( void );
133 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
134 pci_conf_hdr_t *config_hdr_p);
137 pci_system_solx_devfs_create( void );
142 static const struct pci_system_methods solx_devfs_methods = {
143 .destroy = pci_system_solx_devfs_destroy,
144 .destroy_device = NULL,
145 .read_rom = pci_device_solx_devfs_read_rom,
146 .probe = pci_device_solx_devfs_probe,
147 .map_range = pci_device_solx_devfs_map_range,
148 .unmap_range = pci_device_generic_unmap_range,
150 .read = pci_device_solx_devfs_read,
151 .write = pci_device_solx_devfs_write,
153 .fill_capabilities = pci_fill_capabilities_generic
157 * Rlease all the resources
161 pci_system_solx_devfs_destroy( void )
164 * the memory allocated in create routines
165 * will be freed in pci_system_init
166 * It is more reasonable to free them here
180 * Attempt to access PCI subsystem using Solaris's devfs interface.
184 pci_system_solx_devfs_create( void )
191 /* If the directory "/sys/bus/pci/devices" exists,
192 * then the PCI subsystem can be accessed using
195 if ((root_fd = open(PCI_NEXUS_1, O_RDWR)) == -1) {
196 (void) fprintf(stderr,
197 "Could not open nexus node %s: %s\n",
198 PCI_NEXUS_1, strerror(errno));
205 * Only allow MAX_DEVICES exists
206 * I will fix it later to get
207 * the total devices first
209 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
210 pci_sys->methods = &solx_devfs_methods;
211 if ((pci_sys->devices =
213 sizeof (struct pci_device_private))) != NULL) {
214 (void) do_probe(root_fd, pci_sys);
231 * Retrieve first 16 dwords of device's config header, except for the first
232 * dword. First 16 dwords are defined by the PCI specification.
235 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
236 pci_conf_hdr_t *config_hdr_p)
238 pcitool_reg_t cfg_prg;
242 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
244 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
245 cfg_prg.bus_no = bus_no;
246 cfg_prg.dev_no = dev_no;
247 cfg_prg.func_no = func_no;
249 cfg_prg.user_version = PCITOOL_USER_VERSION;
251 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
252 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
253 cfg_prg.offset += sizeof (uint32_t);
255 ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
258 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
266 * Probe device's functions. Modifies many fields in the prg_p.
269 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
271 pci_conf_hdr_t config_hdr;
272 boolean_t multi_function_device;
274 int8_t first_func = 0;
275 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
280 * Loop through at least func=first_func. Continue looping through
281 * functions if there are no errors and the device is a multi-function
284 * (Note, if first_func == 0, header will show whether multifunction
285 * device and set multi_function_device. If first_func != 0, then we
286 * will force the loop as the user wants a specific function to be
289 for (func = first_func, multi_function_device = B_FALSE;
290 ((func <= last_func) &&
291 ((func == first_func) || (multi_function_device)));
293 prg_p->func_no = func;
296 * Four things can happen here:
298 * 1) ioctl comes back as EFAULT and prg_p->status is
299 * PCITOOL_INVALID_ADDRESS. There is no device at this
302 * 2) ioctl comes back successful and the data comes back as
303 * zero. Config space is mapped but no device responded.
305 * 3) ioctl comes back successful and the data comes back as
306 * non-zero. We've found a device.
308 * 4) Some other error occurs in an ioctl.
311 prg_p->status = PCITOOL_SUCCESS;
314 prg_p->user_version = PCITOOL_USER_VERSION;
315 if (((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
316 (prg_p->data == 0xffffffff)) {
319 * Accept errno == EINVAL along with status of
320 * PCITOOL_OUT_OF_RANGE because some systems
321 * don't implement the full range of config space.
322 * Leave the loop quietly in this case.
324 if ((errno == EINVAL) ||
325 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
330 * Exit silently with ENXIO as this means that there are
331 * no devices under the pci root nexus.
333 else if ((errno == ENXIO) &&
334 (prg_p->status == PCITOOL_IO_ERROR)) {
339 * Expect errno == EFAULT along with status of
340 * PCITOOL_INVALID_ADDRESS because there won't be
341 * devices at each stop. Quit on any other error.
343 else if (((errno != EFAULT) ||
344 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
345 (prg_p->data != 0xffffffff)) {
350 * If no function at this location,
351 * just advance to the next function.
358 * Data came back as 0.
359 * Treat as unresponsive device amd check next device.
361 } else if (prg_p->data == 0) {
363 break; /* Func loop. */
365 /* Found something. */
367 config_hdr.dwords[0] = (uint32_t)prg_p->data;
369 /* Get the rest of the PCI header. */
370 if ((rval = get_config_header(fd, prg_p->bus_no,
371 prg_p->dev_no, prg_p->func_no, &config_hdr)) !=
377 * Special case for the type of Southbridge found on
378 * Ultra-45 and other sun4u fire workstations.
380 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
381 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
387 * Found one device with bus numer, device number and
392 * Domain is peer bus??
394 pci_sys->devices[pci_sys->num_devices].base.domain = 0;
395 pci_sys->devices[pci_sys->num_devices].base.bus =
397 pci_sys->devices[pci_sys->num_devices].base.dev =
399 pci_sys->devices[pci_sys->num_devices].base.func = func;
401 * for the format of device_class, see struct pci_device;
403 pci_sys->devices[pci_sys->num_devices].base.device_class =
404 config_hdr.dwords[2]>>8;
405 pci_sys->devices[pci_sys->num_devices].base.revision =
406 (uint8_t)(config_hdr.dwords[2] & 0xff);
407 pci_sys->devices[pci_sys->num_devices].base.vendor_id =
408 (uint16_t)(config_hdr.dwords[0] & 0xffff);
409 pci_sys->devices[pci_sys->num_devices].base.device_id =
410 (uint16_t)((config_hdr.dwords[0]>>16) & 0xffff);
411 pci_sys->devices[pci_sys->num_devices].base.subvendor_id =
412 (uint16_t)(config_hdr.dwords[11] & 0xffff);
413 pci_sys->devices[pci_sys->num_devices].base.subdevice_id =
414 (uint16_t)((config_hdr.dwords[11]>>16) & 0xffff);
415 pci_sys->devices[pci_sys->num_devices].header_type =
416 (uint8_t)(((config_hdr.dwords[3])&0xff0000)>>16);
418 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
419 prg_p->bus_no, prg_p->dev_no, func);
422 pci_sys->num_devices++;
425 * Accomodate devices which state their
426 * multi-functionality only in their function 0 config
427 * space. Note multi-functionality throughout probing
428 * of all of this device's functions.
430 if (config_hdr.bytes[PCI_CONF_HEADER] &
432 multi_function_device = B_TRUE;
442 * Probe a given nexus config space for devices.
444 * fd is the file descriptor of the nexus.
445 * input_args contains commandline options as specified by the user.
448 do_probe(int fd, struct pci_system *pci_sys)
453 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
454 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
455 uint8_t first_bus = 0;
456 uint8_t first_dev = 0;
459 prg.barnum = 0; /* Config space. */
461 /* Must read in 4-byte quantities. */
462 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
467 * Loop through all valid bus / dev / func combinations to check for
468 * all devices, with the following exceptions:
470 * When nothing is found at function 0 of a bus / dev combination, skip
471 * the other functions of that bus / dev combination.
473 * When a found device's function 0 is probed and it is determined that
474 * it is not a multifunction device, skip probing of that device's
477 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
478 prg.bus_no = (uint8_t)bus;
479 for (dev = first_dev;
480 ((dev <= last_dev) && (rval == 0)); dev++) {
482 rval = probe_dev(fd, &prg, pci_sys);
486 * Ultra-45 southbridge workaround:
487 * ECANCELED tells to skip to the next bus.
489 if (rval == ECANCELED) {
493 if (pci_sys->num_devices > MAX_DEVICES) {
494 (void) fprintf(stderr, "pci devices reach maximu number\n");
501 find_target_node(di_node_t node, void *arg)
505 uint32_t busno, funcno, devno;
506 i_devnode_t *devnode;
507 void *prop = DI_PROP_NIL;
510 devnode = (i_devnode_t *)arg;
513 * Test the property funtions, only for testing
516 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
517 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
518 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
520 if (!strcmp(di_prop_name(prop), "reg")) {
521 len = di_prop_ints(prop, ®buf);
523 for (i = 0; i < len; i++) {
524 fprintf(stderr, "0x%0x.", regbuf[i]);
526 fprintf(stderr, "\n");
528 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
531 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg",
536 fprintf(stderr, "error = %x\n", errno);
537 fprintf(stderr, "can not find assigned-address\n");
539 return (DI_WALK_CONTINUE);
541 busno = PCI_REG_BUS_G(regbuf[0]);
542 devno = PCI_REG_DEV_G(regbuf[0]);
543 funcno = PCI_REG_FUNC_G(regbuf[0]);
545 if ((busno == devnode->bus) &&
546 (devno == devnode->dev) &&
547 (funcno == devnode->func)) {
548 devnode->node = node;
550 return (DI_WALK_TERMINATE);
553 return (DI_WALK_CONTINUE);
560 pci_device_solx_devfs_probe( struct pci_device * dev )
572 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
573 args.node = DI_NODE_NIL;
575 struct pci_device_private *priv =
576 (struct pci_device_private *) dev;
579 (uint16_t)config[0] + ((uint16_t)config[1] << 8);
581 (uint16_t)config[2] + ((uint16_t)config[3] << 8);
582 dev->device_class = (uint32_t)config[9] +
583 ((uint32_t)config[10] << 8) +
584 ((uint16_t)config[11] << 16);
586 * device class code is already there.
587 * see probe_dev function.
589 dev->revision = config[8];
591 (uint16_t)config[44] + ((uint16_t)config[45] << 8);
593 (uint16_t)config[46] + ((uint16_t)config[47] << 8);
594 dev->irq = config[60];
596 priv->header_type = config[14];
598 * starting to find if it is MEM/MEM64/IO
601 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
602 (void) fprintf(stderr, "di_init failed: $s\n",
608 args.func = dev->func;
609 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
610 (void *)&args, find_target_node);
614 if (args.node != DI_NODE_NIL) {
616 * It will success for sure, because it was
617 * successfully called in find_target_node
619 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
620 "assigned-addresses",
630 * how to find the size of rom???
631 * if the device has expansion rom,
632 * it must be listed in the last
633 * cells because solaris find probe
634 * the base address from offset 0x10
635 * to 0x30h. So only check the last
638 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
639 if (PCI_REG_REG_G(reg->pci_phys_hi) ==
642 * rom can only be 32 bits
644 dev->rom_size = reg->pci_size_low;
645 len = len - CELL_NUMS_1275;
649 * size default to 64K and base address
652 dev->rom_size = 0x10000;
656 * solaris has its own BAR index. To be sure that
657 * Xorg has the same BAR number as solaris. ????
659 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
660 int ent = i/CELL_NUMS_1275;
662 reg = (pci_regspec_t *)®buf[i];
665 * non relocatable resource is excluded
666 * such like 0xa0000, 0x3b0. If it is met,
667 * the loop is broken;
669 if (!PCI_REG_REG_G(reg->pci_phys_hi))
673 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
674 dev->regions[ent].is_prefetchable = 1;
677 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
679 dev->regions[ent].is_IO = 1;
684 dev->regions[ent].is_64 = 1;
688 * We split the shift count 32 into two 16 to
689 * avoid the complaining of the compiler
691 dev->regions[ent].base_addr = reg->pci_phys_low +
692 ((reg->pci_phys_mid << 16) << 16);
693 dev->regions[ent].size = reg->pci_size_low +
694 ((reg->pci_size_hi << 16) << 16);
702 * Solaris version: read the ROM data
705 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
707 void *prom = MAP_FAILED;
710 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
711 (void) fprintf(stderr, "can not open xsvc driver\n");
717 prom = mmap(NULL, dev->rom_size,
718 PROT_READ, MAP_SHARED,
721 if (prom == MAP_FAILED) {
722 (void) fprintf(stderr, "map rom base =0xC0000 failed");
725 (void) bcopy(prom, buffer, dev->rom_size);
729 * Still used xsvc to do the user space mapping
736 * solaris version: Read the configurations space of the devices
739 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
740 pciaddr_t offset, pciaddr_t size,
741 pciaddr_t * bytes_read )
743 pcitool_reg_t cfg_prg;
747 cfg_prg.offset = offset;
748 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
749 cfg_prg.bus_no = dev->bus;
750 cfg_prg.dev_no = dev->dev;
751 cfg_prg.func_no = dev->func;
753 cfg_prg.user_version = PCITOOL_USER_VERSION;
756 for (i = 0; i < size; i = i + PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) {
758 cfg_prg.offset = offset + i;
759 if ((err = ioctl(root_fd, PCITOOL_DEVICE_GET_REG,
761 fprintf(stderr, "read bdf<%x,%x,%x,%x> config space failure\n",
766 fprintf(stderr, "Failure cause = %x\n", err);
770 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
772 * DWORDS Offset or bytes Offset ??
784 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
785 pciaddr_t offset, pciaddr_t size,
786 pciaddr_t * bytes_written )
788 pcitool_reg_t cfg_prg;
793 if ( bytes_written != NULL ) {
797 cfg_prg.offset = offset;
800 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
803 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
806 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
809 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
815 cfg_prg.bus_no = dev->bus;
816 cfg_prg.dev_no = dev->dev;
817 cfg_prg.func_no = dev->func;
819 cfg_prg.user_version = PCITOOL_USER_VERSION;
820 cfg_prg.data = *((uint64_t *)data);
822 * Check if this device is bridge device.
823 * If it is, it is also a nexus node???
824 * It seems that there is no explicit
825 * PCI nexus device for X86, so not applicable
826 * from pcitool_bus_reg_ops in pci_tools.c
828 cmd = PCITOOL_DEVICE_SET_REG;
830 if ((err = ioctl(root_fd, cmd, &cfg_prg)) != 0) {
833 *bytes_written = size;
840 * Map a memory region for a device using /dev/xsvc.
842 * \param dev Device whose memory region is to be mapped.
843 * \param map Parameters of the mapping that is to be created.
846 * Zero on success or an \c errno value on failure.
849 pci_device_solx_devfs_map_range(struct pci_device *dev,
850 struct pci_device_mapping *map)
852 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
853 ? (PROT_READ | PROT_WRITE) : PROT_READ;
858 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
859 (void) fprintf(stderr, "can not open xsvc driver\n");
864 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvs_fd,
866 if (map->memory == MAP_FAILED) {
869 (void) fprintf(stderr, "map rom region =%x failed",