2 * (C) Copyright IBM Corporation 2006
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
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10 * the Software is furnished to do so, subject to the following conditions:
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53 * Solaris devfs interfaces
62 #include <sys/types.h>
70 #include <libdevinfo.h>
71 #include "pci_tools.h"
73 #include "pciaccess.h"
74 #include "pciaccess_private.h"
76 #define PCI_NEXUS_1 "/devices/pci@0,0:reg"
77 #define MAX_DEVICES 256
78 #define CELL_NUMS_1275 (sizeof(pci_regspec_t)/sizeof(uint_t))
80 uint8_t bytes[16 * sizeof (uint32_t)];
84 typedef struct i_devnode {
91 static int root_fd = -1;
92 static int xsvc_fd = -1;
94 * Read config space in native processor endianness. Endian-neutral
95 * processing can then take place. On big endian machines, MSB and LSB
96 * of little endian data end up switched if read as little endian.
97 * They are in correct order if read as big endian.
100 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
102 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
104 #error "ISA is neither __sparc nor __x86"
108 * Identify problematic southbridges. These have device id 0x5249 and
109 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
110 * Values are little endian, so they are reversed for SPARC.
112 * Check for these southbridges on all architectures, as the issue is a
113 * southbridge issue, independent of processor.
115 * If one of these is found during probing, skip probing other devs/funcs on
116 * the rest of the bus, since the southbridge and all devs underneath will
117 * otherwise disappear.
119 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
120 #define U45_SB_DEVID_VID 0xb9104952
121 #define U45_SB_CLASS_RID 0x00000406
123 #define U45_SB_DEVID_VID 0x524910b9
124 #define U45_SB_CLASS_RID 0x06040000
130 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
131 struct pci_device_mapping *map);
133 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
136 static int pci_device_solx_devfs_probe( struct pci_device * dev );
138 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
139 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
141 static int pci_device_solx_devfs_write( struct pci_device * dev,
142 const void * data, pciaddr_t offset, pciaddr_t size,
143 pciaddr_t * bytes_written );
146 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys);
149 do_probe(int fd, struct pci_system *pci_sys);
152 pci_system_solx_devfs_destroy( void );
155 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
156 pci_conf_hdr_t *config_hdr_p);
159 pci_system_solx_devfs_create( void );
164 static const struct pci_system_methods solx_devfs_methods = {
165 .destroy = pci_system_solx_devfs_destroy,
166 .destroy_device = NULL,
167 .read_rom = pci_device_solx_devfs_read_rom,
168 .probe = pci_device_solx_devfs_probe,
169 .map_range = pci_device_solx_devfs_map_range,
170 .unmap_range = pci_device_generic_unmap_range,
172 .read = pci_device_solx_devfs_read,
173 .write = pci_device_solx_devfs_write,
175 .fill_capabilities = pci_fill_capabilities_generic
179 * Release all the resources
183 pci_system_solx_devfs_destroy( void )
186 * the memory allocated in create routines
187 * will be freed in pci_system_init
188 * It is more reasonable to free them here
202 * Attempt to access PCI subsystem using Solaris's devfs interface.
206 pci_system_solx_devfs_create( void )
213 /* If the PCI nexus device "/devices/pci@0,0:reg" exists,
214 * then the PCI subsystem can be accessed using
217 if ((root_fd = open(PCI_NEXUS_1, O_RDWR)) == -1) {
218 (void) fprintf(stderr,
219 "Could not open nexus node %s: %s\n",
220 PCI_NEXUS_1, strerror(errno));
227 * Only allow MAX_DEVICES exists
228 * I will fix it later to get
229 * the total devices first
231 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
232 pci_sys->methods = &solx_devfs_methods;
233 if ((pci_sys->devices =
235 sizeof (struct pci_device_private))) != NULL) {
236 (void) do_probe(root_fd, pci_sys);
253 * Retrieve first 16 dwords of device's config header, except for the first
254 * dword. First 16 dwords are defined by the PCI specification.
257 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
258 pci_conf_hdr_t *config_hdr_p)
260 pcitool_reg_t cfg_prg;
264 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
266 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
267 cfg_prg.bus_no = bus_no;
268 cfg_prg.dev_no = dev_no;
269 cfg_prg.func_no = func_no;
271 cfg_prg.user_version = PCITOOL_USER_VERSION;
273 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
274 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
275 cfg_prg.offset += sizeof (uint32_t);
277 ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
280 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
288 * Probe device's functions. Modifies many fields in the prg_p.
291 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
293 pci_conf_hdr_t config_hdr;
294 boolean_t multi_function_device;
296 int8_t first_func = 0;
297 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
302 * Loop through at least func=first_func. Continue looping through
303 * functions if there are no errors and the device is a multi-function
306 * (Note, if first_func == 0, header will show whether multifunction
307 * device and set multi_function_device. If first_func != 0, then we
308 * will force the loop as the user wants a specific function to be
311 for (func = first_func, multi_function_device = B_FALSE;
312 ((func <= last_func) &&
313 ((func == first_func) || (multi_function_device)));
315 prg_p->func_no = func;
318 * Four things can happen here:
320 * 1) ioctl comes back as EFAULT and prg_p->status is
321 * PCITOOL_INVALID_ADDRESS. There is no device at this
324 * 2) ioctl comes back successful and the data comes back as
325 * zero. Config space is mapped but no device responded.
327 * 3) ioctl comes back successful and the data comes back as
328 * non-zero. We've found a device.
330 * 4) Some other error occurs in an ioctl.
333 prg_p->status = PCITOOL_SUCCESS;
336 prg_p->user_version = PCITOOL_USER_VERSION;
337 if (((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
338 (prg_p->data == 0xffffffff)) {
341 * Accept errno == EINVAL along with status of
342 * PCITOOL_OUT_OF_RANGE because some systems
343 * don't implement the full range of config space.
344 * Leave the loop quietly in this case.
346 if ((errno == EINVAL) ||
347 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
352 * Exit silently with ENXIO as this means that there are
353 * no devices under the pci root nexus.
355 else if ((errno == ENXIO) &&
356 (prg_p->status == PCITOOL_IO_ERROR)) {
361 * Expect errno == EFAULT along with status of
362 * PCITOOL_INVALID_ADDRESS because there won't be
363 * devices at each stop. Quit on any other error.
365 else if (((errno != EFAULT) ||
366 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
367 (prg_p->data != 0xffffffff)) {
372 * If no function at this location,
373 * just advance to the next function.
380 * Data came back as 0.
381 * Treat as unresponsive device and check next device.
383 } else if (prg_p->data == 0) {
385 break; /* Func loop. */
387 /* Found something. */
389 config_hdr.dwords[0] = (uint32_t)prg_p->data;
391 /* Get the rest of the PCI header. */
392 if ((rval = get_config_header(fd, prg_p->bus_no,
393 prg_p->dev_no, prg_p->func_no, &config_hdr)) !=
399 * Special case for the type of Southbridge found on
400 * Ultra-45 and other sun4u fire workstations.
402 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
403 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
409 * Found one device with bus number, device number and
414 * Domain is peer bus??
416 pci_sys->devices[pci_sys->num_devices].base.domain = 0;
417 pci_sys->devices[pci_sys->num_devices].base.bus =
419 pci_sys->devices[pci_sys->num_devices].base.dev =
421 pci_sys->devices[pci_sys->num_devices].base.func = func;
423 * for the format of device_class, see struct pci_device;
425 pci_sys->devices[pci_sys->num_devices].base.device_class =
426 config_hdr.dwords[2]>>8;
427 pci_sys->devices[pci_sys->num_devices].base.revision =
428 (uint8_t)(config_hdr.dwords[2] & 0xff);
429 pci_sys->devices[pci_sys->num_devices].base.vendor_id =
430 (uint16_t)(config_hdr.dwords[0] & 0xffff);
431 pci_sys->devices[pci_sys->num_devices].base.device_id =
432 (uint16_t)((config_hdr.dwords[0]>>16) & 0xffff);
433 pci_sys->devices[pci_sys->num_devices].base.subvendor_id =
434 (uint16_t)(config_hdr.dwords[11] & 0xffff);
435 pci_sys->devices[pci_sys->num_devices].base.subdevice_id =
436 (uint16_t)((config_hdr.dwords[11]>>16) & 0xffff);
437 pci_sys->devices[pci_sys->num_devices].header_type =
438 (uint8_t)(((config_hdr.dwords[3])&0xff0000)>>16);
440 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
441 prg_p->bus_no, prg_p->dev_no, func);
444 pci_sys->num_devices++;
447 * Accommodate devices which state their
448 * multi-functionality only in their function 0 config
449 * space. Note multi-functionality throughout probing
450 * of all of this device's functions.
452 if (config_hdr.bytes[PCI_CONF_HEADER] &
454 multi_function_device = B_TRUE;
464 * Probe a given nexus config space for devices.
466 * fd is the file descriptor of the nexus.
467 * input_args contains commandline options as specified by the user.
470 do_probe(int fd, struct pci_system *pci_sys)
475 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
476 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
477 uint8_t first_bus = 0;
478 uint8_t first_dev = 0;
481 prg.barnum = 0; /* Config space. */
483 /* Must read in 4-byte quantities. */
484 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
489 * Loop through all valid bus / dev / func combinations to check for
490 * all devices, with the following exceptions:
492 * When nothing is found at function 0 of a bus / dev combination, skip
493 * the other functions of that bus / dev combination.
495 * When a found device's function 0 is probed and it is determined that
496 * it is not a multifunction device, skip probing of that device's
499 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
500 prg.bus_no = (uint8_t)bus;
501 for (dev = first_dev;
502 ((dev <= last_dev) && (rval == 0)); dev++) {
504 rval = probe_dev(fd, &prg, pci_sys);
508 * Ultra-45 southbridge workaround:
509 * ECANCELED tells to skip to the next bus.
511 if (rval == ECANCELED) {
515 if (pci_sys->num_devices > MAX_DEVICES) {
516 (void) fprintf(stderr, "pci devices reach maximum number\n");
523 find_target_node(di_node_t node, void *arg)
527 uint32_t busno, funcno, devno;
528 i_devnode_t *devnode;
529 void *prop = DI_PROP_NIL;
532 devnode = (i_devnode_t *)arg;
535 * Test the property functions, only for testing
538 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
539 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
540 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
542 if (!strcmp(di_prop_name(prop), "reg")) {
543 len = di_prop_ints(prop, ®buf);
545 for (i = 0; i < len; i++) {
546 fprintf(stderr, "0x%0x.", regbuf[i]);
548 fprintf(stderr, "\n");
550 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
553 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg",
558 fprintf(stderr, "error = %x\n", errno);
559 fprintf(stderr, "can not find assigned-address\n");
561 return (DI_WALK_CONTINUE);
563 busno = PCI_REG_BUS_G(regbuf[0]);
564 devno = PCI_REG_DEV_G(regbuf[0]);
565 funcno = PCI_REG_FUNC_G(regbuf[0]);
567 if ((busno == devnode->bus) &&
568 (devno == devnode->dev) &&
569 (funcno == devnode->func)) {
570 devnode->node = node;
572 return (DI_WALK_TERMINATE);
575 return (DI_WALK_CONTINUE);
582 pci_device_solx_devfs_probe( struct pci_device * dev )
594 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
595 args.node = DI_NODE_NIL;
597 struct pci_device_private *priv =
598 (struct pci_device_private *) dev;
601 (uint16_t)config[0] + ((uint16_t)config[1] << 8);
603 (uint16_t)config[2] + ((uint16_t)config[3] << 8);
604 dev->device_class = (uint32_t)config[9] +
605 ((uint32_t)config[10] << 8) +
606 ((uint16_t)config[11] << 16);
608 * device class code is already there.
609 * see probe_dev function.
611 dev->revision = config[8];
613 (uint16_t)config[44] + ((uint16_t)config[45] << 8);
615 (uint16_t)config[46] + ((uint16_t)config[47] << 8);
616 dev->irq = config[60];
618 priv->header_type = config[14];
620 * starting to find if it is MEM/MEM64/IO
623 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
624 (void) fprintf(stderr, "di_init failed: %s\n",
630 args.func = dev->func;
631 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
632 (void *)&args, find_target_node);
636 if (args.node != DI_NODE_NIL) {
638 * It will success for sure, because it was
639 * successfully called in find_target_node
641 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
642 "assigned-addresses",
652 * how to find the size of rom???
653 * if the device has expansion rom,
654 * it must be listed in the last
655 * cells because solaris find probe
656 * the base address from offset 0x10
657 * to 0x30h. So only check the last
660 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
661 if (PCI_REG_REG_G(reg->pci_phys_hi) ==
664 * rom can only be 32 bits
666 dev->rom_size = reg->pci_size_low;
667 len = len - CELL_NUMS_1275;
671 * size default to 64K and base address
674 dev->rom_size = 0x10000;
678 * solaris has its own BAR index. To be sure that
679 * Xorg has the same BAR number as solaris. ????
681 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
682 int ent = i/CELL_NUMS_1275;
684 reg = (pci_regspec_t *)®buf[i];
687 * non relocatable resource is excluded
688 * such like 0xa0000, 0x3b0. If it is met,
689 * the loop is broken;
691 if (!PCI_REG_REG_G(reg->pci_phys_hi))
695 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
696 dev->regions[ent].is_prefetchable = 1;
699 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
701 dev->regions[ent].is_IO = 1;
706 dev->regions[ent].is_64 = 1;
710 * We split the shift count 32 into two 16 to
711 * avoid the complaining of the compiler
713 dev->regions[ent].base_addr = reg->pci_phys_low +
714 ((reg->pci_phys_mid << 16) << 16);
715 dev->regions[ent].size = reg->pci_size_low +
716 ((reg->pci_size_hi << 16) << 16);
724 * Solaris version: read the ROM data
727 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
729 void *prom = MAP_FAILED;
732 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
733 (void) fprintf(stderr, "can not open xsvc driver\n");
739 prom = mmap(NULL, dev->rom_size,
740 PROT_READ, MAP_SHARED,
743 if (prom == MAP_FAILED) {
744 (void) fprintf(stderr, "map rom base =0xC0000 failed");
747 (void) bcopy(prom, buffer, dev->rom_size);
751 * Still used xsvc to do the user space mapping
758 * solaris version: Read the configurations space of the devices
761 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
762 pciaddr_t offset, pciaddr_t size,
763 pciaddr_t * bytes_read )
765 pcitool_reg_t cfg_prg;
769 cfg_prg.offset = offset;
770 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
771 cfg_prg.bus_no = dev->bus;
772 cfg_prg.dev_no = dev->dev;
773 cfg_prg.func_no = dev->func;
775 cfg_prg.user_version = PCITOOL_USER_VERSION;
778 for (i = 0; i < size; i = i + PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) {
780 cfg_prg.offset = offset + i;
781 if ((err = ioctl(root_fd, PCITOOL_DEVICE_GET_REG,
783 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n",
788 fprintf(stderr, "Failure cause = %x\n", err);
792 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
794 * DWORDS Offset or bytes Offset ??
806 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
807 pciaddr_t offset, pciaddr_t size,
808 pciaddr_t * bytes_written )
810 pcitool_reg_t cfg_prg;
815 if ( bytes_written != NULL ) {
819 cfg_prg.offset = offset;
822 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
825 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
828 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
831 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
837 cfg_prg.bus_no = dev->bus;
838 cfg_prg.dev_no = dev->dev;
839 cfg_prg.func_no = dev->func;
841 cfg_prg.user_version = PCITOOL_USER_VERSION;
842 cfg_prg.data = *((uint64_t *)data);
844 * Check if this device is bridge device.
845 * If it is, it is also a nexus node???
846 * It seems that there is no explicit
847 * PCI nexus device for X86, so not applicable
848 * from pcitool_bus_reg_ops in pci_tools.c
850 cmd = PCITOOL_DEVICE_SET_REG;
852 if ((err = ioctl(root_fd, cmd, &cfg_prg)) != 0) {
855 *bytes_written = size;
862 * Map a memory region for a device using /dev/xsvc.
864 * \param dev Device whose memory region is to be mapped.
865 * \param map Parameters of the mapping that is to be created.
868 * Zero on success or an \c errno value on failure.
871 pci_device_solx_devfs_map_range(struct pci_device *dev,
872 struct pci_device_mapping *map)
874 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
875 ? (PROT_READ | PROT_WRITE) : PROT_READ;
880 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
881 (void) fprintf(stderr, "can not open xsvc driver\n");
886 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd,
888 if (map->memory == MAP_FAILED) {
891 (void) fprintf(stderr, "map rom region =%llx failed",