2 * (C) Copyright IBM Corporation 2006
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
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10 * the Software is furnished to do so, subject to the following conditions:
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22 * DEALINGS IN THE SOFTWARE.
25 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
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29 * "Software"), to deal in the Software without restriction, including
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50 * of the copyright holder.
53 * Solaris devfs interfaces
60 #include <sys/types.h>
68 #include <libdevinfo.h>
69 #include "pci_tools.h"
71 #include "pciaccess.h"
72 #include "pciaccess_private.h"
74 #define MAX_DEVICES 256
75 #define CELL_NUMS_1275 (sizeof(pci_regspec_t)/sizeof(uint_t))
78 uint8_t bytes[16 * sizeof (uint32_t)];
82 typedef struct i_devnode {
89 typedef struct nexus {
95 static nexus_t *nexus_list = NULL;
96 static int num_domains = 0;
97 static int xsvc_fd = -1;
100 * Read config space in native processor endianness. Endian-neutral
101 * processing can then take place. On big endian machines, MSB and LSB
102 * of little endian data end up switched if read as little endian.
103 * They are in correct order if read as big endian.
106 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
108 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
110 # error "ISA is neither __sparc nor __x86"
114 * Identify problematic southbridges. These have device id 0x5249 and
115 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
116 * Values are little endian, so they are reversed for SPARC.
118 * Check for these southbridges on all architectures, as the issue is a
119 * southbridge issue, independent of processor.
121 * If one of these is found during probing, skip probing other devs/funcs on
122 * the rest of the bus, since the southbridge and all devs underneath will
123 * otherwise disappear.
125 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
126 # define U45_SB_DEVID_VID 0xb9104952
127 # define U45_SB_CLASS_RID 0x00000406
129 # define U45_SB_DEVID_VID 0x524910b9
130 # define U45_SB_CLASS_RID 0x06040000
136 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
137 struct pci_device_mapping *map);
139 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
142 static int pci_device_solx_devfs_probe( struct pci_device * dev );
144 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
145 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
147 static int pci_device_solx_devfs_write( struct pci_device * dev,
148 const void * data, pciaddr_t offset, pciaddr_t size,
149 pciaddr_t * bytes_written );
151 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p,
152 struct pci_system *pci_sys);
154 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys);
156 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg);
158 static void pci_system_solx_devfs_destroy( void );
160 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no,
161 uint8_t func_no, pci_conf_hdr_t *config_hdr_p);
163 int pci_system_solx_devfs_create( void );
165 static const struct pci_system_methods solx_devfs_methods = {
166 .destroy = pci_system_solx_devfs_destroy,
167 .destroy_device = NULL,
168 .read_rom = pci_device_solx_devfs_read_rom,
169 .probe = pci_device_solx_devfs_probe,
170 .map_range = pci_device_solx_devfs_map_range,
171 .unmap_range = pci_device_generic_unmap_range,
173 .read = pci_device_solx_devfs_read,
174 .write = pci_device_solx_devfs_write,
176 .fill_capabilities = pci_fill_capabilities_generic
180 find_nexus_for_domain( int domain )
184 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) {
185 if (nexus->domain == domain) {
193 get_config_hdr_value(pci_conf_hdr_t *config_hdr_p, uint16_t offset,
199 value = (value << 8) + config_hdr_p->bytes[offset + size];
205 #define GET_CONFIG_VAL_8(offset) \
206 (config_hdr.bytes[offset])
207 #define GET_CONFIG_VAL_16(offset) \
208 (uint16_t)get_config_hdr_value(&config_hdr, offset, 2)
209 #define GET_CONFIG_VAL_32(offset) \
210 (uint32_t)get_config_hdr_value(&config_hdr, offset, 4)
213 * Release all the resources
217 pci_system_solx_devfs_destroy( void )
220 * the memory allocated in create routines
221 * will be freed in pci_system_init
222 * It is more reasonable to free them here
224 nexus_t *nexus, *next;
226 for (nexus = nexus_list ; nexus != NULL ; nexus = next) {
240 * Attempt to access PCI subsystem using Solaris's devfs interface.
244 pci_system_solx_devfs_create( void )
250 if (nexus_list != NULL) {
255 * Only allow MAX_DEVICES exists
256 * I will fix it later to get
257 * the total devices first
259 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
260 pci_sys->methods = &solx_devfs_methods;
261 if ((pci_sys->devices =
262 calloc(MAX_DEVICES, sizeof (struct pci_device_private)))
264 if ((di_node = di_init("/", DINFOCPYALL))
267 (void) fprintf(stderr, "di_init() failed: %s\n",
270 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys,
283 if (pci_sys != NULL) {
284 free(pci_sys->devices);
294 * Retrieve first 16 dwords of device's config header, except for the first
295 * dword. First 16 dwords are defined by the PCI specification.
298 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
299 pci_conf_hdr_t *config_hdr_p)
301 pcitool_reg_t cfg_prg;
305 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
307 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
308 cfg_prg.bus_no = bus_no;
309 cfg_prg.dev_no = dev_no;
310 cfg_prg.func_no = func_no;
312 cfg_prg.user_version = PCITOOL_USER_VERSION;
314 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
315 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
316 cfg_prg.offset += sizeof (uint32_t);
317 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
320 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
328 * Probe device's functions. Modifies many fields in the prg_p.
331 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
333 pci_conf_hdr_t config_hdr;
334 boolean_t multi_function_device;
336 int8_t first_func = 0;
337 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
339 struct pci_device * pci_base;
342 * Loop through at least func=first_func. Continue looping through
343 * functions if there are no errors and the device is a multi-function
346 * (Note, if first_func == 0, header will show whether multifunction
347 * device and set multi_function_device. If first_func != 0, then we
348 * will force the loop as the user wants a specific function to be
351 for (func = first_func, multi_function_device = B_FALSE;
352 ((func <= last_func) &&
353 ((func == first_func) || (multi_function_device)));
355 prg_p->func_no = func;
358 * Four things can happen here:
360 * 1) ioctl comes back as EFAULT and prg_p->status is
361 * PCITOOL_INVALID_ADDRESS. There is no device at this location.
363 * 2) ioctl comes back successful and the data comes back as
364 * zero. Config space is mapped but no device responded.
366 * 3) ioctl comes back successful and the data comes back as
367 * non-zero. We've found a device.
369 * 4) Some other error occurs in an ioctl.
372 prg_p->status = PCITOOL_SUCCESS;
375 prg_p->user_version = PCITOOL_USER_VERSION;
377 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
378 (prg_p->data == 0xffffffff)) {
381 * Accept errno == EINVAL along with status of
382 * PCITOOL_OUT_OF_RANGE because some systems
383 * don't implement the full range of config space.
384 * Leave the loop quietly in this case.
386 if ((errno == EINVAL) ||
387 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
392 * Exit silently with ENXIO as this means that there are
393 * no devices under the pci root nexus.
395 else if ((errno == ENXIO) &&
396 (prg_p->status == PCITOOL_IO_ERROR)) {
401 * Expect errno == EFAULT along with status of
402 * PCITOOL_INVALID_ADDRESS because there won't be
403 * devices at each stop. Quit on any other error.
405 else if (((errno != EFAULT) ||
406 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
407 (prg_p->data != 0xffffffff)) {
412 * If no function at this location,
413 * just advance to the next function.
420 * Data came back as 0.
421 * Treat as unresponsive device and check next device.
423 } else if (prg_p->data == 0) {
425 break; /* Func loop. */
427 /* Found something. */
429 config_hdr.dwords[0] = (uint32_t)prg_p->data;
431 /* Get the rest of the PCI header. */
432 if ((rval = get_config_header(nexus->fd, prg_p->bus_no,
433 prg_p->dev_no, prg_p->func_no,
434 &config_hdr)) != 0) {
439 * Special case for the type of Southbridge found on
440 * Ultra-45 and other sun4u fire workstations.
442 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
443 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
449 * Found one device with bus number, device number and
453 pci_base = &pci_sys->devices[pci_sys->num_devices].base;
456 * Domain is peer bus??
458 pci_base->domain = nexus->domain;
459 pci_base->bus = prg_p->bus_no;
460 pci_base->dev = prg_p->dev_no;
461 pci_base->func = func;
464 * for the format of device_class, see struct pci_device;
467 pci_base->device_class =
468 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) |
469 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) |
470 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS);
472 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID);
473 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID);
474 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID);
475 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID);
476 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID);
478 pci_sys->devices[pci_sys->num_devices].header_type
479 = GET_CONFIG_VAL_8(PCI_CONF_HEADER);
482 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
483 prg_p->bus_no, prg_p->dev_no, func);
486 pci_sys->num_devices++;
489 * Accommodate devices which state their
490 * multi-functionality only in their function 0 config
491 * space. Note multi-functionality throughout probing
492 * of all of this device's functions.
494 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) {
495 multi_function_device = B_TRUE;
504 * This function is called from di_walk_minor() when any PROBE is processed
507 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg)
509 struct pci_system *pci_sys = (struct pci_system *) arg;
513 char nexus_path[MAXPATHLEN];
515 nexus = calloc(1, sizeof(nexus_t));
517 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n",
519 return DI_WALK_TERMINATE;
522 nexus_name = di_devfs_minor_path(minor);
523 if (nexus_name == NULL) {
524 (void) fprintf(stderr, "Error getting nexus path: %s\n",
527 return (DI_WALK_CONTINUE);
530 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name);
532 if ((fd = open(nexus_path, O_RDWR)) >= 0) {
534 nexus->domain = num_domains++;
535 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) {
536 (void) fprintf(stderr, "Error probing node %s: %s\n",
537 nexus_path, strerror(errno));
541 nexus->next = nexus_list;
545 (void) fprintf(stderr, "Error opening %s: %s\n",
546 nexus_path, strerror(errno));
549 di_devfs_path_free(nexus_name);
551 return DI_WALK_CONTINUE;
557 * Probe a given nexus config space for devices.
559 * fd is the file descriptor of the nexus.
560 * input_args contains commandline options as specified by the user.
563 do_probe(nexus_t *nexus, struct pci_system *pci_sys)
568 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
569 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
570 uint8_t first_bus = 0;
571 uint8_t first_dev = 0;
574 prg.barnum = 0; /* Config space. */
576 /* Must read in 4-byte quantities. */
577 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
582 * Loop through all valid bus / dev / func combinations to check for
583 * all devices, with the following exceptions:
585 * When nothing is found at function 0 of a bus / dev combination, skip
586 * the other functions of that bus / dev combination.
588 * When a found device's function 0 is probed and it is determined that
589 * it is not a multifunction device, skip probing of that device's
592 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
593 prg.bus_no = (uint8_t)bus;
595 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) {
597 rval = probe_dev(nexus, &prg, pci_sys);
601 * Ultra-45 southbridge workaround:
602 * ECANCELED tells to skip to the next bus.
604 if (rval == ECANCELED) {
608 if (pci_sys->num_devices > MAX_DEVICES) {
609 (void) fprintf(stderr, "pci devices reach maximum number\n");
616 find_target_node(di_node_t node, void *arg)
620 uint32_t busno, funcno, devno;
621 i_devnode_t *devnode;
622 void *prop = DI_PROP_NIL;
625 devnode = (i_devnode_t *)arg;
628 * Test the property functions, only for testing
631 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
632 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
633 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
635 if (!strcmp(di_prop_name(prop), "reg")) {
636 len = di_prop_ints(prop, ®buf);
638 for (i = 0; i < len; i++) {
639 fprintf(stderr, "0x%0x.", regbuf[i]);
641 fprintf(stderr, "\n");
643 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
646 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf);
650 fprintf(stderr, "error = %x\n", errno);
651 fprintf(stderr, "can not find assigned-address\n");
653 return (DI_WALK_CONTINUE);
656 busno = PCI_REG_BUS_G(regbuf[0]);
657 devno = PCI_REG_DEV_G(regbuf[0]);
658 funcno = PCI_REG_FUNC_G(regbuf[0]);
660 if ((busno == devnode->bus) &&
661 (devno == devnode->dev) &&
662 (funcno == devnode->func)) {
663 devnode->node = node;
665 return (DI_WALK_TERMINATE);
668 return (DI_WALK_CONTINUE);
675 pci_device_solx_devfs_probe( struct pci_device * dev )
687 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
688 args.node = DI_NODE_NIL;
691 struct pci_device_private *priv =
692 (struct pci_device_private *) dev;
694 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8);
695 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8);
696 dev->device_class = (uint32_t)config[9] +
697 ((uint32_t)config[10] << 8) +
698 ((uint16_t)config[11] << 16);
701 * device class code is already there.
702 * see probe_dev function.
704 dev->revision = config[8];
705 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8);
706 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8);
707 dev->irq = config[60];
709 priv->header_type = config[14];
711 * starting to find if it is MEM/MEM64/IO
714 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
715 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno));
720 args.func = dev->func;
721 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
722 (void *)&args, find_target_node);
726 if (args.node != DI_NODE_NIL) {
728 * It will success for sure, because it was
729 * successfully called in find_target_node
731 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
732 "assigned-addresses",
742 * how to find the size of rom???
743 * if the device has expansion rom,
744 * it must be listed in the last
745 * cells because solaris find probe
746 * the base address from offset 0x10
747 * to 0x30h. So only check the last
750 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
751 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) {
753 * rom can only be 32 bits
755 dev->rom_size = reg->pci_size_low;
756 len = len - CELL_NUMS_1275;
760 * size default to 64K and base address
763 dev->rom_size = 0x10000;
767 * solaris has its own BAR index. To be sure that
768 * Xorg has the same BAR number as solaris. ????
770 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
771 int ent = i/CELL_NUMS_1275;
773 reg = (pci_regspec_t *)®buf[i];
776 * non relocatable resource is excluded
777 * such like 0xa0000, 0x3b0. If it is met,
778 * the loop is broken;
780 if (!PCI_REG_REG_G(reg->pci_phys_hi))
783 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
784 dev->regions[ent].is_prefetchable = 1;
787 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
789 dev->regions[ent].is_IO = 1;
794 dev->regions[ent].is_64 = 1;
799 * We split the shift count 32 into two 16 to
800 * avoid the complaining of the compiler
802 dev->regions[ent].base_addr = reg->pci_phys_low +
803 ((reg->pci_phys_mid << 16) << 16);
804 dev->regions[ent].size = reg->pci_size_low +
805 ((reg->pci_size_hi << 16) << 16);
812 * Solaris version: read the ROM data
815 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
817 void *prom = MAP_FAILED;
820 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
821 (void) fprintf(stderr, "can not open xsvc driver\n");
827 prom = mmap(NULL, dev->rom_size,
828 PROT_READ, MAP_SHARED,
831 if (prom == MAP_FAILED) {
832 (void) fprintf(stderr, "map rom base =0xC0000 failed");
835 (void) bcopy(prom, buffer, dev->rom_size);
838 * Still used xsvc to do the user space mapping
844 * solaris version: Read the configurations space of the devices
847 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
848 pciaddr_t offset, pciaddr_t size,
849 pciaddr_t * bytes_read )
851 pcitool_reg_t cfg_prg;
854 nexus_t *nexus = find_nexus_for_domain(dev->domain);
858 if ( nexus == NULL ) {
862 cfg_prg.offset = offset;
863 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
864 cfg_prg.bus_no = dev->bus;
865 cfg_prg.dev_no = dev->dev;
866 cfg_prg.func_no = dev->func;
868 cfg_prg.user_version = PCITOOL_USER_VERSION;
870 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1))
872 cfg_prg.offset = offset + i;
874 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
875 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n",
880 fprintf(stderr, "Failure cause = %x\n", err);
884 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
886 * DWORDS Offset or bytes Offset ??
898 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
899 pciaddr_t offset, pciaddr_t size,
900 pciaddr_t * bytes_written )
902 pcitool_reg_t cfg_prg;
905 nexus_t *nexus = find_nexus_for_domain(dev->domain);
907 if ( bytes_written != NULL ) {
911 if ( nexus == NULL ) {
915 cfg_prg.offset = offset;
918 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
921 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
924 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
927 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
932 cfg_prg.bus_no = dev->bus;
933 cfg_prg.dev_no = dev->dev;
934 cfg_prg.func_no = dev->func;
936 cfg_prg.user_version = PCITOOL_USER_VERSION;
937 cfg_prg.data = *((uint64_t *)data);
940 * Check if this device is bridge device.
941 * If it is, it is also a nexus node???
942 * It seems that there is no explicit
943 * PCI nexus device for X86, so not applicable
944 * from pcitool_bus_reg_ops in pci_tools.c
946 cmd = PCITOOL_DEVICE_SET_REG;
948 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) {
951 *bytes_written = size;
958 * Map a memory region for a device using /dev/xsvc.
960 * \param dev Device whose memory region is to be mapped.
961 * \param map Parameters of the mapping that is to be created.
964 * Zero on success or an \c errno value on failure.
967 pci_device_solx_devfs_map_range(struct pci_device *dev,
968 struct pci_device_mapping *map)
970 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
971 ? (PROT_READ | PROT_WRITE) : PROT_READ;
975 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
976 (void) fprintf(stderr, "can not open xsvc driver\n");
981 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base);
982 if (map->memory == MAP_FAILED) {
985 (void) fprintf(stderr, "map rom region =%llx failed", map->base);