2 * Copyright (c) 2007, Sun Microsystems, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
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10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 * Solaris devfs interfaces
35 #include <sys/types.h>
43 #include <libdevinfo.h>
44 #include "pci_tools.h"
46 #include "pciaccess.h"
47 #include "pciaccess_private.h"
49 #define PCI_NEXUS_1 "/devices/pci@0,0:reg"
50 #define MAX_DEVICES 256
51 #define CELL_NUMS_1275 (sizeof(pci_regspec_t)/sizeof(uint_t))
53 uint8_t bytes[16 * sizeof (uint32_t)];
57 typedef struct i_devnode {
64 static int root_fd = -1;
65 static int xsvc_fd = -1;
67 * Read config space in native processor endianness. Endian-neutral
68 * processing can then take place. On big endian machines, MSB and LSB
69 * of little endian data end up switched if read as little endian.
70 * They are in correct order if read as big endian.
73 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
75 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
77 #error "ISA is neither __sparc nor __x86"
81 * Identify problematic southbridges. These have device id 0x5249 and
82 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
83 * Values are little endian, so they are reversed for SPARC.
85 * Check for these southbridges on all architectures, as the issue is a
86 * southbridge issue, independent of processor.
88 * If one of these is found during probing, skip probing other devs/funcs on
89 * the rest of the bus, since the southbridge and all devs underneath will
90 * otherwise disappear.
92 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
93 #define U45_SB_DEVID_VID 0xb9104952
94 #define U45_SB_CLASS_RID 0x00000406
96 #define U45_SB_DEVID_VID 0x524910b9
97 #define U45_SB_CLASS_RID 0x06040000
103 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
104 struct pci_device_mapping *map);
106 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
109 static int pci_device_solx_devfs_probe( struct pci_device * dev );
111 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
112 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
114 static int pci_device_solx_devfs_write( struct pci_device * dev,
115 const void * data, pciaddr_t offset, pciaddr_t size,
116 pciaddr_t * bytes_written );
119 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys);
122 do_probe(int fd, struct pci_system *pci_sys);
125 pci_system_solx_devfs_destroy( void );
128 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
129 pci_conf_hdr_t *config_hdr_p);
132 pci_system_solx_devfs_create( void );
137 static const struct pci_system_methods solx_devfs_methods = {
138 .destroy = pci_system_solx_devfs_destroy,
139 .destroy_device = NULL,
140 .read_rom = pci_device_solx_devfs_read_rom,
141 .probe = pci_device_solx_devfs_probe,
142 .map_range = pci_device_solx_devfs_map_range,
143 .unmap_range = pci_device_generic_unmap_range,
145 .read = pci_device_solx_devfs_read,
146 .write = pci_device_solx_devfs_write,
148 .fill_capabilities = pci_fill_capabilities_generic
152 * Release all the resources
156 pci_system_solx_devfs_destroy( void )
159 * the memory allocated in create routines
160 * will be freed in pci_system_init
161 * It is more reasonable to free them here
175 * Attempt to access PCI subsystem using Solaris's devfs interface.
179 pci_system_solx_devfs_create( void )
186 /* If the directory "/sys/bus/pci/devices" exists,
187 * then the PCI subsystem can be accessed using
190 if ((root_fd = open(PCI_NEXUS_1, O_RDWR)) == -1) {
191 (void) fprintf(stderr,
192 "Could not open nexus node %s: %s\n",
193 PCI_NEXUS_1, strerror(errno));
200 * Only allow MAX_DEVICES exists
201 * I will fix it later to get
202 * the total devices first
204 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
205 pci_sys->methods = &solx_devfs_methods;
206 if ((pci_sys->devices =
208 sizeof (struct pci_device_private))) != NULL) {
209 (void) do_probe(root_fd, pci_sys);
226 * Retrieve first 16 dwords of device's config header, except for the first
227 * dword. First 16 dwords are defined by the PCI specification.
230 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
231 pci_conf_hdr_t *config_hdr_p)
233 pcitool_reg_t cfg_prg;
237 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
239 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
240 cfg_prg.bus_no = bus_no;
241 cfg_prg.dev_no = dev_no;
242 cfg_prg.func_no = func_no;
244 cfg_prg.user_version = PCITOOL_USER_VERSION;
246 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
247 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
248 cfg_prg.offset += sizeof (uint32_t);
250 ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
253 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
261 * Probe device's functions. Modifies many fields in the prg_p.
264 probe_dev(int fd, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
266 pci_conf_hdr_t config_hdr;
267 boolean_t multi_function_device;
269 int8_t first_func = 0;
270 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
275 * Loop through at least func=first_func. Continue looping through
276 * functions if there are no errors and the device is a multi-function
279 * (Note, if first_func == 0, header will show whether multifunction
280 * device and set multi_function_device. If first_func != 0, then we
281 * will force the loop as the user wants a specific function to be
284 for (func = first_func, multi_function_device = B_FALSE;
285 ((func <= last_func) &&
286 ((func == first_func) || (multi_function_device)));
288 prg_p->func_no = func;
291 * Four things can happen here:
293 * 1) ioctl comes back as EFAULT and prg_p->status is
294 * PCITOOL_INVALID_ADDRESS. There is no device at this
297 * 2) ioctl comes back successful and the data comes back as
298 * zero. Config space is mapped but no device responded.
300 * 3) ioctl comes back successful and the data comes back as
301 * non-zero. We've found a device.
303 * 4) Some other error occurs in an ioctl.
306 prg_p->status = PCITOOL_SUCCESS;
309 prg_p->user_version = PCITOOL_USER_VERSION;
310 if (((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
311 (prg_p->data == 0xffffffff)) {
314 * Accept errno == EINVAL along with status of
315 * PCITOOL_OUT_OF_RANGE because some systems
316 * don't implement the full range of config space.
317 * Leave the loop quietly in this case.
319 if ((errno == EINVAL) ||
320 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
325 * Exit silently with ENXIO as this means that there are
326 * no devices under the pci root nexus.
328 else if ((errno == ENXIO) &&
329 (prg_p->status == PCITOOL_IO_ERROR)) {
334 * Expect errno == EFAULT along with status of
335 * PCITOOL_INVALID_ADDRESS because there won't be
336 * devices at each stop. Quit on any other error.
338 else if (((errno != EFAULT) ||
339 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
340 (prg_p->data != 0xffffffff)) {
345 * If no function at this location,
346 * just advance to the next function.
353 * Data came back as 0.
354 * Treat as unresponsive device and check next device.
356 } else if (prg_p->data == 0) {
358 break; /* Func loop. */
360 /* Found something. */
362 config_hdr.dwords[0] = (uint32_t)prg_p->data;
364 /* Get the rest of the PCI header. */
365 if ((rval = get_config_header(fd, prg_p->bus_no,
366 prg_p->dev_no, prg_p->func_no, &config_hdr)) !=
372 * Special case for the type of Southbridge found on
373 * Ultra-45 and other sun4u fire workstations.
375 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
376 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
382 * Found one device with bus number, device number and
387 * Domain is peer bus??
389 pci_sys->devices[pci_sys->num_devices].base.domain = 0;
390 pci_sys->devices[pci_sys->num_devices].base.bus =
392 pci_sys->devices[pci_sys->num_devices].base.dev =
394 pci_sys->devices[pci_sys->num_devices].base.func = func;
396 * for the format of device_class, see struct pci_device;
398 pci_sys->devices[pci_sys->num_devices].base.device_class =
399 config_hdr.dwords[2]>>8;
400 pci_sys->devices[pci_sys->num_devices].base.revision =
401 (uint8_t)(config_hdr.dwords[2] & 0xff);
402 pci_sys->devices[pci_sys->num_devices].base.vendor_id =
403 (uint16_t)(config_hdr.dwords[0] & 0xffff);
404 pci_sys->devices[pci_sys->num_devices].base.device_id =
405 (uint16_t)((config_hdr.dwords[0]>>16) & 0xffff);
406 pci_sys->devices[pci_sys->num_devices].base.subvendor_id =
407 (uint16_t)(config_hdr.dwords[11] & 0xffff);
408 pci_sys->devices[pci_sys->num_devices].base.subdevice_id =
409 (uint16_t)((config_hdr.dwords[11]>>16) & 0xffff);
410 pci_sys->devices[pci_sys->num_devices].header_type =
411 (uint8_t)(((config_hdr.dwords[3])&0xff0000)>>16);
413 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
414 prg_p->bus_no, prg_p->dev_no, func);
417 pci_sys->num_devices++;
420 * Accommodate devices which state their
421 * multi-functionality only in their function 0 config
422 * space. Note multi-functionality throughout probing
423 * of all of this device's functions.
425 if (config_hdr.bytes[PCI_CONF_HEADER] &
427 multi_function_device = B_TRUE;
437 * Probe a given nexus config space for devices.
439 * fd is the file descriptor of the nexus.
440 * input_args contains commandline options as specified by the user.
443 do_probe(int fd, struct pci_system *pci_sys)
448 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
449 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
450 uint8_t first_bus = 0;
451 uint8_t first_dev = 0;
454 prg.barnum = 0; /* Config space. */
456 /* Must read in 4-byte quantities. */
457 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
462 * Loop through all valid bus / dev / func combinations to check for
463 * all devices, with the following exceptions:
465 * When nothing is found at function 0 of a bus / dev combination, skip
466 * the other functions of that bus / dev combination.
468 * When a found device's function 0 is probed and it is determined that
469 * it is not a multifunction device, skip probing of that device's
472 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
473 prg.bus_no = (uint8_t)bus;
474 for (dev = first_dev;
475 ((dev <= last_dev) && (rval == 0)); dev++) {
477 rval = probe_dev(fd, &prg, pci_sys);
481 * Ultra-45 southbridge workaround:
482 * ECANCELED tells to skip to the next bus.
484 if (rval == ECANCELED) {
488 if (pci_sys->num_devices > MAX_DEVICES) {
489 (void) fprintf(stderr, "pci devices reach maximum number\n");
496 find_target_node(di_node_t node, void *arg)
500 uint32_t busno, funcno, devno;
501 i_devnode_t *devnode;
502 void *prop = DI_PROP_NIL;
505 devnode = (i_devnode_t *)arg;
508 * Test the property functions, only for testing
511 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
512 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
513 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
515 if (!strcmp(di_prop_name(prop), "reg")) {
516 len = di_prop_ints(prop, ®buf);
518 for (i = 0; i < len; i++) {
519 fprintf(stderr, "0x%0x.", regbuf[i]);
521 fprintf(stderr, "\n");
523 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
526 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg",
531 fprintf(stderr, "error = %x\n", errno);
532 fprintf(stderr, "can not find assigned-address\n");
534 return (DI_WALK_CONTINUE);
536 busno = PCI_REG_BUS_G(regbuf[0]);
537 devno = PCI_REG_DEV_G(regbuf[0]);
538 funcno = PCI_REG_FUNC_G(regbuf[0]);
540 if ((busno == devnode->bus) &&
541 (devno == devnode->dev) &&
542 (funcno == devnode->func)) {
543 devnode->node = node;
545 return (DI_WALK_TERMINATE);
548 return (DI_WALK_CONTINUE);
555 pci_device_solx_devfs_probe( struct pci_device * dev )
567 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
568 args.node = DI_NODE_NIL;
570 struct pci_device_private *priv =
571 (struct pci_device_private *) dev;
574 (uint16_t)config[0] + ((uint16_t)config[1] << 8);
576 (uint16_t)config[2] + ((uint16_t)config[3] << 8);
577 dev->device_class = (uint32_t)config[9] +
578 ((uint32_t)config[10] << 8) +
579 ((uint16_t)config[11] << 16);
581 * device class code is already there.
582 * see probe_dev function.
584 dev->revision = config[8];
586 (uint16_t)config[44] + ((uint16_t)config[45] << 8);
588 (uint16_t)config[46] + ((uint16_t)config[47] << 8);
589 dev->irq = config[60];
591 priv->header_type = config[14];
593 * starting to find if it is MEM/MEM64/IO
596 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
597 (void) fprintf(stderr, "di_init failed: %s\n",
603 args.func = dev->func;
604 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
605 (void *)&args, find_target_node);
609 if (args.node != DI_NODE_NIL) {
611 * It will success for sure, because it was
612 * successfully called in find_target_node
614 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
615 "assigned-addresses",
625 * how to find the size of rom???
626 * if the device has expansion rom,
627 * it must be listed in the last
628 * cells because solaris find probe
629 * the base address from offset 0x10
630 * to 0x30h. So only check the last
633 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
634 if (PCI_REG_REG_G(reg->pci_phys_hi) ==
637 * rom can only be 32 bits
639 dev->rom_size = reg->pci_size_low;
640 len = len - CELL_NUMS_1275;
644 * size default to 64K and base address
647 dev->rom_size = 0x10000;
651 * solaris has its own BAR index. To be sure that
652 * Xorg has the same BAR number as solaris. ????
654 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
655 int ent = i/CELL_NUMS_1275;
657 reg = (pci_regspec_t *)®buf[i];
660 * non relocatable resource is excluded
661 * such like 0xa0000, 0x3b0. If it is met,
662 * the loop is broken;
664 if (!PCI_REG_REG_G(reg->pci_phys_hi))
668 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
669 dev->regions[ent].is_prefetchable = 1;
672 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
674 dev->regions[ent].is_IO = 1;
679 dev->regions[ent].is_64 = 1;
683 * We split the shift count 32 into two 16 to
684 * avoid the complaining of the compiler
686 dev->regions[ent].base_addr = reg->pci_phys_low +
687 ((reg->pci_phys_mid << 16) << 16);
688 dev->regions[ent].size = reg->pci_size_low +
689 ((reg->pci_size_hi << 16) << 16);
697 * Solaris version: read the ROM data
700 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
702 void *prom = MAP_FAILED;
705 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
706 (void) fprintf(stderr, "can not open xsvc driver\n");
712 prom = mmap(NULL, dev->rom_size,
713 PROT_READ, MAP_SHARED,
716 if (prom == MAP_FAILED) {
717 (void) fprintf(stderr, "map rom base =0xC0000 failed");
720 (void) bcopy(prom, buffer, dev->rom_size);
724 * Still used xsvc to do the user space mapping
731 * solaris version: Read the configurations space of the devices
734 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
735 pciaddr_t offset, pciaddr_t size,
736 pciaddr_t * bytes_read )
738 pcitool_reg_t cfg_prg;
742 cfg_prg.offset = offset;
743 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
744 cfg_prg.bus_no = dev->bus;
745 cfg_prg.dev_no = dev->dev;
746 cfg_prg.func_no = dev->func;
748 cfg_prg.user_version = PCITOOL_USER_VERSION;
751 for (i = 0; i < size; i = i + PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) {
753 cfg_prg.offset = offset + i;
754 if ((err = ioctl(root_fd, PCITOOL_DEVICE_GET_REG,
756 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n",
761 fprintf(stderr, "Failure cause = %x\n", err);
765 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
767 * DWORDS Offset or bytes Offset ??
779 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
780 pciaddr_t offset, pciaddr_t size,
781 pciaddr_t * bytes_written )
783 pcitool_reg_t cfg_prg;
788 if ( bytes_written != NULL ) {
792 cfg_prg.offset = offset;
795 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
798 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
801 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
804 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
810 cfg_prg.bus_no = dev->bus;
811 cfg_prg.dev_no = dev->dev;
812 cfg_prg.func_no = dev->func;
814 cfg_prg.user_version = PCITOOL_USER_VERSION;
815 cfg_prg.data = *((uint64_t *)data);
817 * Check if this device is bridge device.
818 * If it is, it is also a nexus node???
819 * It seems that there is no explicit
820 * PCI nexus device for X86, so not applicable
821 * from pcitool_bus_reg_ops in pci_tools.c
823 cmd = PCITOOL_DEVICE_SET_REG;
825 if ((err = ioctl(root_fd, cmd, &cfg_prg)) != 0) {
828 *bytes_written = size;
835 * Map a memory region for a device using /dev/xsvc.
837 * \param dev Device whose memory region is to be mapped.
838 * \param map Parameters of the mapping that is to be created.
841 * Zero on success or an \c errno value on failure.
844 pci_device_solx_devfs_map_range(struct pci_device *dev,
845 struct pci_device_mapping *map)
847 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
848 ? (PROT_READ | PROT_WRITE) : PROT_READ;
853 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
854 (void) fprintf(stderr, "can not open xsvc driver\n");
859 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd,
861 if (map->memory == MAP_FAILED) {
864 (void) fprintf(stderr, "map rom region =%llx failed",