1 /* $OpenBSD: octeonreg.h,v 1.15 2009/10/26 18:00:06 miod Exp $ */
4 * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com).
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #define OCTEON_UART0_BASE 0x1180000000800ULL
30 #define OCTEON_UART1_BASE 0x1180000000C00ULL
32 #define CIU_INT_WORKQ0 0
33 #define CIU_INT_WORKQ1 1
34 #define CIU_INT_WORKQ2 2
35 #define CIU_INT_WORKQ3 3
36 #define CIU_INT_WORKQ4 4
37 #define CIU_INT_WORKQ5 5
38 #define CIU_INT_WORKQ6 6
39 #define CIU_INT_WORKQ7 7
40 #define CIU_INT_WORKQ8 8
41 #define CIU_INT_WORKQ9 9
42 #define CIU_INT_WORKQ10 10
43 #define CIU_INT_WORKQ11 11
44 #define CIU_INT_WORKQ12 12
45 #define CIU_INT_WORKQ13 13
46 #define CIU_INT_WORKQ14 14
47 #define CIU_INT_WORKQ15 15
48 #define CIU_INT_GPIO0 16
49 #define CIU_INT_GPIO1 17
50 #define CIU_INT_GPIO2 18
51 #define CIU_INT_GPIO3 19
52 #define CIU_INT_GPIO4 20
53 #define CIU_INT_GPIO5 21
54 #define CIU_INT_GPIO6 22
55 #define CIU_INT_GPIO7 23
56 #define CIU_INT_GPIO8 24
57 #define CIU_INT_GPIO9 25
58 #define CIU_INT_GPIO10 26
59 #define CIU_INT_GPIO11 27
60 #define CIU_INT_GPIO12 28
61 #define CIU_INT_GPIO13 29
62 #define CIU_INT_GPIO14 30
63 #define CIU_INT_GPIO15 31
64 #define CIU_INT_MBOX0 32
65 #define CIU_INT_MBOX1 33
66 #define CIU_INT_MBOX(x) (CIU_INT_MBOX0 + (x))
67 #define CIU_INT_UART0 34
68 #define CIU_INT_UART1 35
69 #define CIU_INT_PCI_INTA 36
70 #define CIU_INT_PCI_INTB 37
71 #define CIU_INT_PCI_INTC 38
72 #define CIU_INT_PCI_INTD 39
73 #define CIU_INT_PCI_MSIA 40
74 #define CIU_INT_PCI_MSIB 41
75 #define CIU_INT_PCI_MSIC 42
76 #define CIU_INT_PCI_MSID 43
78 #define CIU_INT_TWSI 45
79 #define CIU_INT_RML 46
80 #define CIU_INT_TRACE 47
81 #define CIU_INT_GMX_DRP0 48
82 #define CIU_INT_GMX_DRP1 49
83 #define CIU_INT_IPD_DRP 50
84 #define CIU_INT_KEY_ZERO 51
85 #define CIU_INT_TIMER0 52
86 #define CIU_INT_TIMER1 53
87 #define CIU_INT_TIMER2 54
88 #define CIU_INT_TIMER3 55
89 #define CIU_INT_USB 56
90 #define CIU_INT_PCM 57
91 #define CIU_INT_MPI 58
92 #define CIU_INT_TWSI2 59
93 #define CIU_INT_POWIQ 60
94 #define CIU_INT_IPDPPTHR 61
95 #define CIU_INT_MII0 62
96 #define CIU_INT_BOOTDMA 63
98 #define OCTEON_CIU_BASE 0x1070000000000ULL
99 #define OCTEON_CIU_SIZE 0xC10
100 #define CIU_INT0_SUM0 0x00000000
101 #define CIU_INT1_SUM0 0x00000008
102 #define CIU_INT2_SUM0 0x00000010
103 #define CIU_INT3_SUM0 0x00000018
104 #define CIU_INTx_SUM0(x) (CIU_INT0_SUM0 + ((x) * 8))
105 #define CIU_INT32_SUM0 0x00000100
106 #define CIU_INT32_SUM1 0x00000108
108 #define CIU_INT0_EN0 0x00000200
109 #define CIU_INT1_EN0 0x00000210
110 #define CIU_INT2_EN0 0x00000220
111 #define CIU_INT3_EN0 0x00000230
112 #define CIU_INTx_EN0(x) (CIU_INT0_EN0 + ((x) * 8))
113 #define CIU_INT32_EN0 0x00000400
115 #define CIU_INT0_EN1 0x00000208
116 #define CIU_INT1_EN1 0x00000218
117 #define CIU_INT2_EN1 0x00000228
118 #define CIU_INT3_EN1 0x00000238
119 #define CIU_INTx_EN1(x) (CIU_INT0_EN1 + ((x) * 8))
120 #define CIU_INT32_EN1 0x00000408
122 #define CIU_TIM0 0x00000480
123 #define CIU_TIM1 0x00000488
124 #define CIU_TIM2 0x00000490
125 #define CIU_TIM3 0x00000498
126 #define CIU_WDOG0 0x00000500
127 #define CIU_WDOG1 0x00000508
128 #define CIU_PP_POKE0 0x00000580
129 #define CIU_PP_POKE1 0x00000588
130 #define CIU_MBOX_SET0 0x00000600
131 #define CIU_MBOX_SET1 0x00000608
132 #define CIU_MBOX_SET(x) (CIU_MBOX_SET0 + ((x) * 8))
133 #define CIU_MBOX_CLR0 0x00000680
134 #define CIU_MBOX_CLR1 0x00000688
135 #define CIU_MBOX_CLR(x) (CIU_MBOX_CLR0 + ((x) * 8))
136 #define CIU_PP_RST 0x00000700
137 #define CIU_PP_DBG 0x00000708
138 #define CIU_GSTOP 0x00000710
139 #define CIU_NMI 0x00000718
140 #define CIU_DINT 0x00000720
141 #define CIU_FUSE 0x00000728
142 #define CIU_BIST 0x00000730
143 #define CIU_SOFT_BIST 0x00000738
144 #define CIU_SOFT_RST 0x00000740
145 #define CIU_SOFT_PRST 0x00000748
146 #define CIU_PCI_INTA 0x00000750
147 #define CIU_INT0_SUM4 0x00000C00
148 #define CIU_INT1_SUM4 0x00000C08
151 #define CIU_INT0_EN4_0 0x00000C80
152 #define CIU_INT1_EN4_0 0x00000C90
153 #define CIU_INTx_EN4_0(x) (CIU_INT0_EN4_0 + ((x) * 8))
155 #define CIU_INT0_EN4_1 0x00000C88
156 #define CIU_INT1_EN4_1 0x00000C98
157 #define CIU_INTx_EN4_1(x) (CIU_INT0_EN4_1 + ((x) * 8))