2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
38 static const uint32_t push_constant_opcodes[] = {
39 [MESA_SHADER_VERTEX] = 21,
40 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
41 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
42 [MESA_SHADER_GEOMETRY] = 22,
43 [MESA_SHADER_FRAGMENT] = 23,
44 [MESA_SHADER_COMPUTE] = 0,
47 VkShaderStageFlags flushed = 0;
49 anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
50 if (stage == MESA_SHADER_COMPUTE)
53 struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
55 if (state.offset == 0)
58 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
59 ._3DCommandSubOpcode = push_constant_opcodes[stage],
61 .PointerToConstantBuffer0 = { .offset = state.offset },
62 .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
65 flushed |= mesa_to_vk_shader_stage(stage);
68 cmd_buffer->state.push_constants_dirty &= ~flushed;
75 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
76 uint32_t count, const VkViewport *viewports)
78 struct anv_state sf_clip_state =
79 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
80 struct anv_state cc_state =
81 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
83 for (uint32_t i = 0; i < count; i++) {
84 const VkViewport *vp = &viewports[i];
86 /* The gen7 state struct has just the matrix and guardband fields, the
87 * gen8 struct adds the min/max viewport fields. */
88 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
89 .ViewportMatrixElementm00 = vp->width / 2,
90 .ViewportMatrixElementm11 = vp->height / 2,
91 .ViewportMatrixElementm22 = (vp->maxDepth - vp->minDepth) / 2,
92 .ViewportMatrixElementm30 = vp->x + vp->width / 2,
93 .ViewportMatrixElementm31 = vp->y + vp->height / 2,
94 .ViewportMatrixElementm32 = (vp->maxDepth + vp->minDepth) / 2,
95 .XMinClipGuardband = -1.0f,
96 .XMaxClipGuardband = 1.0f,
97 .YMinClipGuardband = -1.0f,
98 .YMaxClipGuardband = 1.0f,
99 .XMinViewPort = vp->x,
100 .XMaxViewPort = vp->x + vp->width - 1,
101 .YMinViewPort = vp->y,
102 .YMaxViewPort = vp->y + vp->height - 1,
105 struct GENX(CC_VIEWPORT) cc_viewport = {
106 .MinimumDepth = vp->minDepth,
107 .MaximumDepth = vp->maxDepth
110 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
112 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
115 if (!cmd_buffer->device->info.has_llc) {
116 anv_state_clflush(sf_clip_state);
117 anv_state_clflush(cc_state);
120 anv_batch_emit(&cmd_buffer->batch,
121 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
122 .CCViewportPointer = cc_state.offset);
123 anv_batch_emit(&cmd_buffer->batch,
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
125 .SFClipViewportPointer = sf_clip_state.offset);
129 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
131 if (cmd_buffer->state.dynamic.viewport.count > 0) {
132 emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
133 cmd_buffer->state.dynamic.viewport.viewports);
135 /* If viewport count is 0, this is taken to mean "use the default" */
136 emit_viewport_state(cmd_buffer, 1,
140 .width = cmd_buffer->state.framebuffer->width,
141 .height = cmd_buffer->state.framebuffer->height,
150 flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer)
152 if (cmd_buffer->state.current_pipeline != _3D) {
153 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
157 .PipelineSelection = _3D);
158 cmd_buffer->state.current_pipeline = _3D;
163 cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
165 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
168 uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
170 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
172 flush_pipeline_select_3d(cmd_buffer);
175 const uint32_t num_buffers = __builtin_popcount(vb_emit);
176 const uint32_t num_dwords = 1 + num_buffers * 4;
178 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
179 GENX(3DSTATE_VERTEX_BUFFERS));
181 for_each_bit(vb, vb_emit) {
182 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
183 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
185 struct GENX(VERTEX_BUFFER_STATE) state = {
186 .VertexBufferIndex = vb,
187 .MemoryObjectControlState = GENX(MOCS),
188 .AddressModifyEnable = true,
189 .BufferPitch = pipeline->binding_stride[vb],
190 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
191 .BufferSize = buffer->size - offset
194 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
199 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
200 /* If somebody compiled a pipeline after starting a command buffer the
201 * scratch bo may have grown since we started this cmd buffer (and
202 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
203 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
204 if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
205 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
207 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
210 /* We emit the binding tables and sampler tables first, then emit push
211 * constants and then finally emit binding table and sampler table
212 * pointers. It has to happen in this order, since emitting the binding
213 * tables may change the push constants (in case of storage images). After
214 * emitting push constants, on SKL+ we have to emit the corresponding
215 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
218 if (cmd_buffer->state.descriptors_dirty)
219 dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
221 if (cmd_buffer->state.push_constants_dirty)
222 dirty |= cmd_buffer_flush_push_constants(cmd_buffer);
225 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
227 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
228 gen8_cmd_buffer_emit_viewport(cmd_buffer);
230 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
231 gen7_cmd_buffer_emit_scissor(cmd_buffer);
233 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
234 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
235 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
236 struct GENX(3DSTATE_SF) sf = {
237 GENX(3DSTATE_SF_header),
238 .LineWidth = cmd_buffer->state.dynamic.line_width,
240 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
242 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
245 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
246 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
247 bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
248 cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
250 uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
251 struct GENX(3DSTATE_RASTER) raster = {
252 GENX(3DSTATE_RASTER_header),
253 .GlobalDepthOffsetEnableSolid = enable_bias,
254 .GlobalDepthOffsetEnableWireframe = enable_bias,
255 .GlobalDepthOffsetEnablePoint = enable_bias,
256 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
257 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
258 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
260 GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
261 anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
262 pipeline->gen8.raster);
265 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
266 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
267 * across different state packets for gen8 and gen9. We handle that by
268 * using a big old #if switch here.
271 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
272 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
273 struct anv_state cc_state =
274 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
275 GEN8_COLOR_CALC_STATE_length * 4,
277 struct GEN8_COLOR_CALC_STATE cc = {
278 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
279 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
280 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
281 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
282 .StencilReferenceValue =
283 cmd_buffer->state.dynamic.stencil_reference.front,
284 .BackFaceStencilReferenceValue =
285 cmd_buffer->state.dynamic.stencil_reference.back,
287 GEN8_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
289 if (!cmd_buffer->device->info.has_llc)
290 anv_state_clflush(cc_state);
292 anv_batch_emit(&cmd_buffer->batch,
293 GEN8_3DSTATE_CC_STATE_POINTERS,
294 .ColorCalcStatePointer = cc_state.offset,
295 .ColorCalcStatePointerValid = true);
298 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
299 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
300 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
301 uint32_t wm_depth_stencil_dw[GEN8_3DSTATE_WM_DEPTH_STENCIL_length];
303 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
304 GEN8_3DSTATE_WM_DEPTH_STENCIL_header,
306 /* Is this what we need to do? */
307 .StencilBufferWriteEnable =
308 cmd_buffer->state.dynamic.stencil_write_mask.front != 0,
311 cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
313 cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
315 .BackfaceStencilTestMask =
316 cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
317 .BackfaceStencilWriteMask =
318 cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
320 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, wm_depth_stencil_dw,
323 anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
324 pipeline->gen8.wm_depth_stencil);
327 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
328 struct anv_state cc_state =
329 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
330 GEN9_COLOR_CALC_STATE_length * 4,
332 struct GEN9_COLOR_CALC_STATE cc = {
333 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
334 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
335 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
336 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
338 GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
340 if (!cmd_buffer->device->info.has_llc)
341 anv_state_clflush(cc_state);
343 anv_batch_emit(&cmd_buffer->batch,
344 GEN9_3DSTATE_CC_STATE_POINTERS,
345 .ColorCalcStatePointer = cc_state.offset,
346 .ColorCalcStatePointerValid = true);
349 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
350 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
351 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
352 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
353 uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
354 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
355 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
356 GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
358 .StencilBufferWriteEnable = d->stencil_write_mask.front != 0,
360 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
361 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
363 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
364 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
366 .StencilReferenceValue = d->stencil_reference.front,
367 .BackfaceStencilReferenceValue = d->stencil_reference.back
369 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
371 anv_batch_emit_merge(&cmd_buffer->batch, dwords,
372 pipeline->gen9.wm_depth_stencil);
376 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
377 ANV_CMD_DIRTY_INDEX_BUFFER)) {
378 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
379 .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
380 .CutIndex = cmd_buffer->state.restart_index,
384 cmd_buffer->state.vb_dirty &= ~vb_emit;
385 cmd_buffer->state.dirty = 0;
389 VkCommandBuffer commandBuffer,
390 uint32_t vertexCount,
391 uint32_t instanceCount,
392 uint32_t firstVertex,
393 uint32_t firstInstance)
395 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
397 cmd_buffer_flush_state(cmd_buffer);
399 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
400 .VertexAccessType = SEQUENTIAL,
401 .VertexCountPerInstance = vertexCount,
402 .StartVertexLocation = firstVertex,
403 .InstanceCount = instanceCount,
404 .StartInstanceLocation = firstInstance,
405 .BaseVertexLocation = 0);
408 void genX(CmdDrawIndexed)(
409 VkCommandBuffer commandBuffer,
411 uint32_t instanceCount,
413 int32_t vertexOffset,
414 uint32_t firstInstance)
416 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
418 cmd_buffer_flush_state(cmd_buffer);
420 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
421 .VertexAccessType = RANDOM,
422 .VertexCountPerInstance = indexCount,
423 .StartVertexLocation = firstIndex,
424 .InstanceCount = instanceCount,
425 .StartInstanceLocation = firstInstance,
426 .BaseVertexLocation = vertexOffset);
430 emit_lrm(struct anv_batch *batch,
431 uint32_t reg, struct anv_bo *bo, uint32_t offset)
433 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
434 .RegisterAddress = reg,
435 .MemoryAddress = { bo, offset });
439 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
441 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
442 .RegisterOffset = reg,
446 /* Auto-Draw / Indirect Registers */
447 #define GEN7_3DPRIM_END_OFFSET 0x2420
448 #define GEN7_3DPRIM_START_VERTEX 0x2430
449 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
450 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
451 #define GEN7_3DPRIM_START_INSTANCE 0x243C
452 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
454 void genX(CmdDrawIndirect)(
455 VkCommandBuffer commandBuffer,
461 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
462 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
463 struct anv_bo *bo = buffer->bo;
464 uint32_t bo_offset = buffer->offset + offset;
466 cmd_buffer_flush_state(cmd_buffer);
468 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
469 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
470 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
471 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
472 emit_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
474 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
475 .IndirectParameterEnable = true,
476 .VertexAccessType = SEQUENTIAL);
479 void genX(CmdBindIndexBuffer)(
480 VkCommandBuffer commandBuffer,
483 VkIndexType indexType)
485 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
486 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
488 static const uint32_t vk_to_gen_index_type[] = {
489 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
490 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
493 static const uint32_t restart_index_for_type[] = {
494 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
495 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
498 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
500 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
501 .IndexFormat = vk_to_gen_index_type[indexType],
502 .MemoryObjectControlState = GENX(MOCS),
503 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
504 .BufferSize = buffer->size - offset);
506 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
510 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
512 struct anv_device *device = cmd_buffer->device;
513 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
514 struct anv_state surfaces = { 0, }, samplers = { 0, };
517 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
518 MESA_SHADER_COMPUTE, &samplers);
519 if (result != VK_SUCCESS)
521 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
522 MESA_SHADER_COMPUTE, &surfaces);
523 if (result != VK_SUCCESS)
526 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
528 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
529 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
531 unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
532 unsigned push_constant_data_size =
533 (prog_data->nr_params + local_id_dwords) * 4;
534 unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
535 unsigned push_constant_regs = reg_aligned_constant_size / 32;
537 if (push_state.alloc_size) {
538 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
539 .CURBETotalDataLength = push_state.alloc_size,
540 .CURBEDataStartAddress = push_state.offset);
543 struct anv_state state =
544 anv_state_pool_emit(&device->dynamic_state_pool,
545 GENX(INTERFACE_DESCRIPTOR_DATA), 64,
546 .KernelStartPointer = pipeline->cs_simd,
547 .KernelStartPointerHigh = 0,
548 .BindingTablePointer = surfaces.offset,
549 .BindingTableEntryCount = 0,
550 .SamplerStatePointer = samplers.offset,
552 .ConstantIndirectURBEntryReadLength = push_constant_regs,
553 .ConstantURBEntryReadOffset = 0,
554 .BarrierEnable = cs_prog_data->uses_barrier,
555 .NumberofThreadsinGPGPUThreadGroup =
556 pipeline->cs_thread_width_max);
558 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
559 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
560 .InterfaceDescriptorTotalLength = size,
561 .InterfaceDescriptorDataStartAddress = state.offset);
567 cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
569 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
572 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
574 if (cmd_buffer->state.current_pipeline != GPGPU) {
575 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
579 .PipelineSelection = GPGPU);
580 cmd_buffer->state.current_pipeline = GPGPU;
583 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
584 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
586 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
587 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
588 result = flush_compute_descriptor_set(cmd_buffer);
589 assert(result == VK_SUCCESS);
590 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
593 cmd_buffer->state.compute_dirty = 0;
596 void genX(CmdDrawIndexedIndirect)(
597 VkCommandBuffer commandBuffer,
603 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
604 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
605 struct anv_bo *bo = buffer->bo;
606 uint32_t bo_offset = buffer->offset + offset;
608 cmd_buffer_flush_state(cmd_buffer);
610 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
611 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
612 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
613 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
614 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
616 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
617 .IndirectParameterEnable = true,
618 .VertexAccessType = RANDOM);
621 void genX(CmdDispatch)(
622 VkCommandBuffer commandBuffer,
627 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
628 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
629 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
631 if (prog_data->uses_num_work_groups) {
632 struct anv_state state =
633 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
634 uint32_t *sizes = state.map;
638 if (!cmd_buffer->device->info.has_llc)
639 anv_state_clflush(state);
640 cmd_buffer->state.num_workgroups_offset = state.offset;
641 cmd_buffer->state.num_workgroups_bo =
642 &cmd_buffer->device->dynamic_state_block_pool.bo;
645 cmd_buffer_flush_compute_state(cmd_buffer);
647 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
648 .SIMDSize = prog_data->simd_size / 16,
649 .ThreadDepthCounterMaximum = 0,
650 .ThreadHeightCounterMaximum = 0,
651 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
652 .ThreadGroupIDXDimension = x,
653 .ThreadGroupIDYDimension = y,
654 .ThreadGroupIDZDimension = z,
655 .RightExecutionMask = pipeline->cs_right_mask,
656 .BottomExecutionMask = 0xffffffff);
658 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
661 #define GPGPU_DISPATCHDIMX 0x2500
662 #define GPGPU_DISPATCHDIMY 0x2504
663 #define GPGPU_DISPATCHDIMZ 0x2508
665 void genX(CmdDispatchIndirect)(
666 VkCommandBuffer commandBuffer,
670 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
671 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
672 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
673 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
674 struct anv_bo *bo = buffer->bo;
675 uint32_t bo_offset = buffer->offset + offset;
677 if (prog_data->uses_num_work_groups) {
678 cmd_buffer->state.num_workgroups_offset = bo_offset;
679 cmd_buffer->state.num_workgroups_bo = bo;
682 cmd_buffer_flush_compute_state(cmd_buffer);
684 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
685 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
686 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
688 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
689 .IndirectParameterEnable = true,
690 .SIMDSize = prog_data->simd_size / 16,
691 .ThreadDepthCounterMaximum = 0,
692 .ThreadHeightCounterMaximum = 0,
693 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
694 .RightExecutionMask = pipeline->cs_right_mask,
695 .BottomExecutionMask = 0xffffffff);
697 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
701 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
703 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
704 const struct anv_image_view *iview =
705 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
706 const struct anv_image *image = iview ? iview->image : NULL;
708 /* XXX: isl needs to grow depth format support */
709 const struct anv_format *anv_format =
710 iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
712 const bool has_depth = iview && anv_format->depth_format;
713 const bool has_stencil = iview && anv_format->has_stencil;
715 /* FIXME: Implement the PMA stall W/A */
716 /* FIXME: Width and Height are wrong */
718 /* Emit 3DSTATE_DEPTH_BUFFER */
720 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
721 .SurfaceType = SURFTYPE_2D,
722 .DepthWriteEnable = anv_format->depth_format,
723 .StencilWriteEnable = has_stencil,
724 .HierarchicalDepthBufferEnable = false,
725 .SurfaceFormat = anv_format->depth_format,
726 .SurfacePitch = image->depth_surface.isl.row_pitch - 1,
727 .SurfaceBaseAddress = {
729 .offset = image->depth_surface.offset,
731 .Height = fb->height - 1,
732 .Width = fb->width - 1,
735 .MinimumArrayElement = 0,
736 .DepthBufferObjectControlState = GENX(MOCS),
737 .RenderTargetViewExtent = 1 - 1,
738 .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2);
740 /* Even when no depth buffer is present, the hardware requires that
741 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
743 * If a null depth buffer is bound, the driver must instead bind depth as:
744 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
745 * 3DSTATE_DEPTH.Width = 1
746 * 3DSTATE_DEPTH.Height = 1
747 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
748 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
749 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
750 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
751 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
753 * The PRM is wrong, though. The width and height must be programmed to
754 * actual framebuffer's width and height, even when neither depth buffer
755 * nor stencil buffer is present.
757 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
758 .SurfaceType = SURFTYPE_2D,
759 .SurfaceFormat = D16_UNORM,
760 .Width = fb->width - 1,
761 .Height = fb->height - 1,
762 .StencilWriteEnable = has_stencil);
765 /* Emit 3DSTATE_STENCIL_BUFFER */
767 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
768 .StencilBufferEnable = true,
769 .StencilBufferObjectControlState = GENX(MOCS),
771 /* Stencil buffers have strange pitch. The PRM says:
773 * The pitch must be set to 2x the value computed based on width,
774 * as the stencil buffer is stored with two rows interleaved.
776 .SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
778 .SurfaceBaseAddress = {
780 .offset = image->offset + image->stencil_surface.offset,
782 .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2);
784 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
787 /* Disable hierarchial depth buffers. */
788 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
790 /* Clear the clear params. */
791 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
795 * @see anv_cmd_buffer_set_subpass()
798 genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
799 struct anv_subpass *subpass)
801 cmd_buffer->state.subpass = subpass;
803 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
805 cmd_buffer_emit_depth_stencil(cmd_buffer);
808 void genX(CmdBeginRenderPass)(
809 VkCommandBuffer commandBuffer,
810 const VkRenderPassBeginInfo* pRenderPassBegin,
811 VkSubpassContents contents)
813 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
814 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
815 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
817 cmd_buffer->state.framebuffer = framebuffer;
818 cmd_buffer->state.pass = pass;
819 anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
821 flush_pipeline_select_3d(cmd_buffer);
823 const VkRect2D *render_area = &pRenderPassBegin->renderArea;
825 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
826 .ClippedDrawingRectangleYMin = render_area->offset.y,
827 .ClippedDrawingRectangleXMin = render_area->offset.x,
828 .ClippedDrawingRectangleYMax =
829 render_area->offset.y + render_area->extent.height - 1,
830 .ClippedDrawingRectangleXMax =
831 render_area->offset.x + render_area->extent.width - 1,
832 .DrawingRectangleOriginY = 0,
833 .DrawingRectangleOriginX = 0);
835 genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
836 anv_cmd_buffer_clear_subpass(cmd_buffer);
839 void genX(CmdNextSubpass)(
840 VkCommandBuffer commandBuffer,
841 VkSubpassContents contents)
843 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
845 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
847 genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
848 anv_cmd_buffer_clear_subpass(cmd_buffer);
851 void genX(CmdEndRenderPass)(
852 VkCommandBuffer commandBuffer)
854 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
856 /* Emit a flushing pipe control at the end of a pass. This is kind of a
857 * hack but it ensures that render targets always actually get written.
858 * Eventually, we should do flushing based on image format transitions
859 * or something of that nature.
861 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
862 .PostSyncOperation = NoWrite,
863 .RenderTargetCacheFlushEnable = true,
864 .InstructionCacheInvalidateEnable = true,
865 .DepthCacheFlushEnable = true,
866 .VFCacheInvalidationEnable = true,
867 .TextureCacheInvalidationEnable = true,
868 .CommandStreamerStallEnable = true);
872 emit_ps_depth_count(struct anv_batch *batch,
873 struct anv_bo *bo, uint32_t offset)
875 anv_batch_emit(batch, GENX(PIPE_CONTROL),
876 .DestinationAddressType = DAT_PPGTT,
877 .PostSyncOperation = WritePSDepthCount,
878 .DepthStallEnable = true,
879 .Address = { bo, offset });
883 emit_query_availability(struct anv_batch *batch,
884 struct anv_bo *bo, uint32_t offset)
886 anv_batch_emit(batch, GENX(PIPE_CONTROL),
887 .DestinationAddressType = DAT_PPGTT,
888 .PostSyncOperation = WriteImmediateData,
889 .Address = { bo, offset },
893 void genX(CmdBeginQuery)(
894 VkCommandBuffer commandBuffer,
895 VkQueryPool queryPool,
897 VkQueryControlFlags flags)
899 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
900 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
902 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
903 * that the pipelining of the depth write breaks. What we see is that
904 * samples from the render pass clear leaks into the first query
905 * immediately after the clear. Doing a pipecontrol with a post-sync
906 * operation and DepthStallEnable seems to work around the issue.
908 if (cmd_buffer->state.need_query_wa) {
909 cmd_buffer->state.need_query_wa = false;
910 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
911 .DepthCacheFlushEnable = true,
912 .DepthStallEnable = true);
915 switch (pool->type) {
916 case VK_QUERY_TYPE_OCCLUSION:
917 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
918 query * sizeof(struct anv_query_pool_slot));
921 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
927 void genX(CmdEndQuery)(
928 VkCommandBuffer commandBuffer,
929 VkQueryPool queryPool,
932 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
933 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
935 switch (pool->type) {
936 case VK_QUERY_TYPE_OCCLUSION:
937 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
938 query * sizeof(struct anv_query_pool_slot) + 8);
940 emit_query_availability(&cmd_buffer->batch, &pool->bo,
941 query * sizeof(struct anv_query_pool_slot) + 16);
944 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
950 #define TIMESTAMP 0x2358
952 void genX(CmdWriteTimestamp)(
953 VkCommandBuffer commandBuffer,
954 VkPipelineStageFlagBits pipelineStage,
955 VkQueryPool queryPool,
958 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
959 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
960 uint32_t offset = query * sizeof(struct anv_query_pool_slot);
962 assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
964 switch (pipelineStage) {
965 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
966 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
967 .RegisterAddress = TIMESTAMP,
968 .MemoryAddress = { &pool->bo, offset });
969 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
970 .RegisterAddress = TIMESTAMP + 4,
971 .MemoryAddress = { &pool->bo, offset + 4 });
975 /* Everything else is bottom-of-pipe */
976 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
977 .DestinationAddressType = DAT_PPGTT,
978 .PostSyncOperation = WriteTimestamp,
979 .Address = { &pool->bo, offset });
983 emit_query_availability(&cmd_buffer->batch, &pool->bo, query + 16);
986 #define alu_opcode(v) __gen_field((v), 20, 31)
987 #define alu_operand1(v) __gen_field((v), 10, 19)
988 #define alu_operand2(v) __gen_field((v), 0, 9)
989 #define alu(opcode, operand1, operand2) \
990 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
992 #define OPCODE_NOOP 0x000
993 #define OPCODE_LOAD 0x080
994 #define OPCODE_LOADINV 0x480
995 #define OPCODE_LOAD0 0x081
996 #define OPCODE_LOAD1 0x481
997 #define OPCODE_ADD 0x100
998 #define OPCODE_SUB 0x101
999 #define OPCODE_AND 0x102
1000 #define OPCODE_OR 0x103
1001 #define OPCODE_XOR 0x104
1002 #define OPCODE_STORE 0x180
1003 #define OPCODE_STOREINV 0x580
1005 #define OPERAND_R0 0x00
1006 #define OPERAND_R1 0x01
1007 #define OPERAND_R2 0x02
1008 #define OPERAND_R3 0x03
1009 #define OPERAND_R4 0x04
1010 #define OPERAND_SRCA 0x20
1011 #define OPERAND_SRCB 0x21
1012 #define OPERAND_ACCU 0x31
1013 #define OPERAND_ZF 0x32
1014 #define OPERAND_CF 0x33
1016 #define CS_GPR(n) (0x2600 + (n) * 8)
1019 emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
1020 struct anv_bo *bo, uint32_t offset)
1022 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
1023 .RegisterAddress = reg,
1024 .MemoryAddress = { bo, offset });
1025 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
1026 .RegisterAddress = reg + 4,
1027 .MemoryAddress = { bo, offset + 4 });
1031 store_query_result(struct anv_batch *batch, uint32_t reg,
1032 struct anv_bo *bo, uint32_t offset, VkQueryResultFlags flags)
1034 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
1035 .RegisterAddress = reg,
1036 .MemoryAddress = { bo, offset });
1038 if (flags & VK_QUERY_RESULT_64_BIT)
1039 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
1040 .RegisterAddress = reg + 4,
1041 .MemoryAddress = { bo, offset + 4 });
1044 void genX(CmdCopyQueryPoolResults)(
1045 VkCommandBuffer commandBuffer,
1046 VkQueryPool queryPool,
1047 uint32_t firstQuery,
1048 uint32_t queryCount,
1049 VkBuffer destBuffer,
1050 VkDeviceSize destOffset,
1051 VkDeviceSize destStride,
1052 VkQueryResultFlags flags)
1054 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1055 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
1056 ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
1057 uint32_t slot_offset, dst_offset;
1059 if (flags & VK_QUERY_RESULT_WAIT_BIT)
1060 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1061 .CommandStreamerStallEnable = true,
1062 .StallAtPixelScoreboard = true);
1064 dst_offset = buffer->offset + destOffset;
1065 for (uint32_t i = 0; i < queryCount; i++) {
1067 slot_offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot);
1068 switch (pool->type) {
1069 case VK_QUERY_TYPE_OCCLUSION:
1070 emit_load_alu_reg_u64(&cmd_buffer->batch,
1071 CS_GPR(0), &pool->bo, slot_offset);
1072 emit_load_alu_reg_u64(&cmd_buffer->batch,
1073 CS_GPR(1), &pool->bo, slot_offset + 8);
1075 /* FIXME: We need to clamp the result for 32 bit. */
1077 uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(MI_MATH));
1078 dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
1079 dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
1080 dw[3] = alu(OPCODE_SUB, 0, 0);
1081 dw[4] = alu(OPCODE_STORE, OPERAND_R2, OPERAND_ACCU);
1084 case VK_QUERY_TYPE_TIMESTAMP:
1085 emit_load_alu_reg_u64(&cmd_buffer->batch,
1086 CS_GPR(2), &pool->bo, slot_offset);
1090 unreachable("unhandled query type");
1093 store_query_result(&cmd_buffer->batch,
1094 CS_GPR(2), buffer->bo, dst_offset, flags);
1096 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1097 emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
1098 &pool->bo, slot_offset + 16);
1099 if (flags & VK_QUERY_RESULT_64_BIT)
1100 store_query_result(&cmd_buffer->batch,
1101 CS_GPR(0), buffer->bo, dst_offset + 8, flags);
1103 store_query_result(&cmd_buffer->batch,
1104 CS_GPR(0), buffer->bo, dst_offset + 4, flags);
1107 dst_offset += destStride;
1111 void genX(CmdSetEvent)(
1112 VkCommandBuffer commandBuffer,
1114 VkPipelineStageFlags stageMask)
1116 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1117 ANV_FROM_HANDLE(anv_event, event, _event);
1119 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1120 .DestinationAddressType = DAT_PPGTT,
1121 .PostSyncOperation = WriteImmediateData,
1123 &cmd_buffer->device->dynamic_state_block_pool.bo,
1126 .ImmediateData = VK_EVENT_SET);
1129 void genX(CmdResetEvent)(
1130 VkCommandBuffer commandBuffer,
1132 VkPipelineStageFlags stageMask)
1134 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1135 ANV_FROM_HANDLE(anv_event, event, _event);
1137 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1138 .DestinationAddressType = DAT_PPGTT,
1139 .PostSyncOperation = WriteImmediateData,
1141 &cmd_buffer->device->dynamic_state_block_pool.bo,
1144 .ImmediateData = VK_EVENT_RESET);
1147 void genX(CmdWaitEvents)(
1148 VkCommandBuffer commandBuffer,
1149 uint32_t eventCount,
1150 const VkEvent* pEvents,
1151 VkPipelineStageFlags srcStageMask,
1152 VkPipelineStageFlags destStageMask,
1153 uint32_t memoryBarrierCount,
1154 const VkMemoryBarrier* pMemoryBarriers,
1155 uint32_t bufferMemoryBarrierCount,
1156 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
1157 uint32_t imageMemoryBarrierCount,
1158 const VkImageMemoryBarrier* pImageMemoryBarriers)
1160 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1161 for (uint32_t i = 0; i < eventCount; i++) {
1162 ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
1164 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT),
1165 .WaitMode = PollingMode,
1166 .CompareOperation = SAD_EQUAL_SDD,
1167 .SemaphoreDataDword = VK_EVENT_SET,
1168 .SemaphoreAddress = {
1169 &cmd_buffer->device->dynamic_state_block_pool.bo,
1174 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
1175 false, /* byRegion */
1176 memoryBarrierCount, pMemoryBarriers,
1177 bufferMemoryBarrierCount, pBufferMemoryBarriers,
1178 imageMemoryBarrierCount, pImageMemoryBarriers);