2 * Copyright (c) 2009, 2012 Samuel Thibault
3 * Heavily inspired from the freebsd, netbsd, and openbsd backends
4 * (C) Copyright Eric Anholt 2006
5 * (C) Copyright IBM Corporation 2006
6 * Copyright (c) 2008 Juan Romero Pardines
7 * Copyright (c) 2008 Mark Kettenis
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
34 #include "pciaccess.h"
35 #include "pciaccess_private.h"
44 if (!ioperm(0, 0xffff, 1))
52 if (!ioperm(0, 0xffff, 0))
57 #elif defined(__GLIBC__)
77 #elif defined(__CYGWIN__)
81 /* WinIo declarations */
83 typedef struct tagPhysStruct {
84 DWORD64 dwPhysMemSizeInBytes;
85 DWORD64 pvPhysAddress;
86 DWORD64 PhysicalMemoryHandle;
88 DWORD64 pvPhysSection;
91 typedef bool (_stdcall* INITIALIZEWINIO)(void);
92 typedef void (_stdcall* SHUTDOWNWINIO)(void);
93 typedef bool (_stdcall* GETPORTVAL)(WORD,PDWORD,BYTE);
94 typedef bool (_stdcall* SETPORTVAL)(WORD,DWORD,BYTE);
95 typedef PBYTE (_stdcall* MAPPHYSTOLIN)(tagPhysStruct*);
96 typedef bool (_stdcall* UNMAPPHYSMEM)(tagPhysStruct*);
98 SHUTDOWNWINIO ShutdownWinIo;
99 GETPORTVAL GetPortVal;
100 SETPORTVAL SetPortVal;
101 INITIALIZEWINIO InitializeWinIo;
102 MAPPHYSTOLIN MapPhysToLin;
103 UNMAPPHYSMEM UnmapPhysicalMemory;
110 if ((GetVersion() & 0x80000000) == 0) {
111 /* running on NT, try WinIo version 3 (32 or 64 bits) */
113 lib = LoadLibrary("WinIo64.dll");
115 lib = LoadLibrary("WinIo32.dll");
120 fprintf(stderr, "Failed to load WinIo library.\n");
124 #define GETPROC(n, d) \
125 n = (d) GetProcAddress(lib, #n); \
127 fprintf(stderr, "Failed to load " #n " function.\n"); \
131 GETPROC(InitializeWinIo, INITIALIZEWINIO);
132 GETPROC(ShutdownWinIo, SHUTDOWNWINIO);
133 GETPROC(GetPortVal, GETPORTVAL);
134 GETPROC(SetPortVal, SETPORTVAL);
135 GETPROC(MapPhysToLin, MAPPHYSTOLIN);
136 GETPROC(UnmapPhysicalMemory, UNMAPPHYSMEM);
140 if (!InitializeWinIo()) {
141 fprintf(stderr, "Failed to initialize WinIo.\n"
142 "NOTE: WinIo.dll and WinIo.sys must be in the same directory as the executable!\n");
156 static inline uint8_t
161 if (GetPortVal(port, &pv, 1))
166 static inline uint16_t
171 if (GetPortVal(port, &pv, 2))
176 static inline uint32_t
181 if (GetPortVal(port, &pv, 4))
187 outb(uint8_t value, uint16_t port)
189 SetPortVal(port, value, 1);
193 outw(uint16_t value, uint16_t port)
195 SetPortVal(port, value, 2);
199 outl(uint32_t value, uint16_t port)
201 SetPortVal(port, value, 4);
206 #error How to enable IO ports on this system?
210 #define PCI_VENDOR(reg) ((reg) & 0xFFFF)
211 #define PCI_VENDOR_INVALID 0xFFFF
213 #define PCI_VENDOR_ID 0x00
214 #define PCI_SUB_VENDOR_ID 0x2c
215 #define PCI_VENDOR_ID_COMPAQ 0x0e11
216 #define PCI_VENDOR_ID_INTEL 0x8086
218 #define PCI_DEVICE(reg) (((reg) >> 16) & 0xFFFF)
219 #define PCI_DEVICE_INVALID 0xFFFF
221 #define PCI_CLASS 0x08
222 #define PCI_CLASS_DEVICE 0x0a
223 #define PCI_CLASS_DISPLAY_VGA 0x0300
224 #define PCI_CLASS_BRIDGE_HOST 0x0600
226 #define PCIC_DISPLAY 0x03
227 #define PCIS_DISPLAY_VGA 0x00
229 #define PCI_HDRTYPE 0x0E
232 struct pci_system_x86 {
233 struct pci_system system;
234 int (*read)(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, void *data, unsigned size);
235 int (*write)(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, const void *data, unsigned size);
239 pci_system_x86_conf1_probe(void)
246 outl(0x80000000, 0xCF8);
247 if (inl(0xCF8) == 0x80000000)
255 pci_system_x86_conf1_read(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, void *data, unsigned size)
257 unsigned addr = 0xCFC + (reg & 3);
261 if (bus >= 0x100 || dev >= 32 || func >= 8 || reg >= 0x100 || size > 4 || size == 3)
265 outl(0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3), 0xCF8);
266 /* NOTE: x86 is already LE */
274 uint16_t *val = data;
279 uint32_t *val = data;
290 pci_system_x86_conf1_write(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, const void *data, unsigned size)
292 unsigned addr = 0xCFC + (reg & 3);
296 if (bus >= 0x100 || dev >= 32 || func >= 8 || reg >= 0x100 || size > 4 || size == 3)
300 outl(0x80000000 | (bus << 16) | (dev << 11) | (func << 8) | (reg & ~3), 0xCF8);
301 /* NOTE: x86 is already LE */
304 const uint8_t *val = data;
309 const uint16_t *val = data;
314 const uint32_t *val = data;
325 pci_system_x86_conf2_probe(void)
330 if (inb(0xCF8) == 0 && inb(0xCFA) == 0)
337 pci_system_x86_conf2_read(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, void *data, unsigned size)
339 unsigned addr = 0xC000 | dev << 8 | reg;
342 if (bus >= 0x100 || dev >= 16 || func >= 8 || reg >= 0x100)
345 outb((func << 1) | 0xF0, 0xCF8);
347 /* NOTE: x86 is already LE */
355 uint16_t *val = data;
360 uint32_t *val = data;
374 pci_system_x86_conf2_write(unsigned bus, unsigned dev, unsigned func, pciaddr_t reg, const void *data, unsigned size)
376 unsigned addr = 0xC000 | dev << 8 | reg;
379 if (bus >= 0x100 || dev >= 16 || func >= 8 || reg >= 0x100)
382 outb((func << 1) | 0xF0, 0xCF8);
384 /* NOTE: x86 is already LE */
387 const uint8_t *val = data;
392 const uint16_t *val = data;
397 const uint32_t *val = data;
410 /* Check that this really looks like a PCI configuration. */
412 pci_system_x86_check(struct pci_system_x86 *pci_sys_x86)
415 uint16_t class, vendor;
417 /* Look on bus 0 for a device that is a host bridge, a VGA card,
418 * or an intel or compaq device. */
420 for (dev = 0; dev < 32; dev++) {
421 if (pci_sys_x86->read(0, dev, 0, PCI_CLASS_DEVICE, &class, sizeof(class)))
423 if (class == PCI_CLASS_BRIDGE_HOST || class == PCI_CLASS_DISPLAY_VGA)
425 if (pci_sys_x86->read(0, dev, 0, PCI_VENDOR_ID, &vendor, sizeof(vendor)))
427 if (vendor == PCI_VENDOR_ID_INTEL || class == PCI_VENDOR_ID_COMPAQ)
435 pci_nfuncs(struct pci_system_x86 *pci_sys_x86, int bus, int dev)
440 err = pci_sys_x86->read(bus, dev, 0, PCI_HDRTYPE, &hdr, sizeof(hdr));
445 return hdr & 0x80 ? 8 : 1;
449 * Read a VGA rom using the 0xc0000 mapping.
452 pci_device_x86_read_rom(struct pci_device *dev, void *buffer)
457 if ((dev->device_class & 0x00ffff00) !=
458 ((PCIC_DISPLAY << 16) | ( PCIS_DISPLAY_VGA << 8))) {
462 memfd = open("/dev/mem", O_RDONLY | O_CLOEXEC);
466 bios = mmap(NULL, dev->rom_size, PROT_READ, 0, memfd, 0xc0000);
467 if (bios == MAP_FAILED) {
472 memcpy(buffer, bios, dev->rom_size);
474 munmap(bios, dev->rom_size);
480 /** Returns the number of regions (base address registers) the device has */
482 pci_device_x86_get_num_regions(uint8_t header_type)
484 switch (header_type & 0x7f) {
492 fprintf(stderr,"unknown header type %02x\n", header_type);
497 /** Masks out the flag bigs of the base address register value */
499 get_map_base( uint32_t val )
507 /** Returns the size of a region based on the all-ones test value */
509 get_test_val_size( uint32_t testval )
516 /* Mask out the flag bits */
517 testval = get_map_base( testval );
521 while ((testval & 1) == 0) {
530 pci_device_x86_probe(struct pci_device *dev)
532 uint8_t irq, hdrtype;
535 /* Many of the fields were filled in during initial device enumeration.
536 * At this point, we need to fill in regions, rom_size, and irq.
539 err = pci_device_cfg_read_u8(dev, &irq, PCI_IRQ);
544 err = pci_device_cfg_read_u8(dev, &hdrtype, PCI_HDRTYPE);
549 for (i = 0; i < pci_device_x86_get_num_regions(hdrtype); i++, bar += 4) {
550 uint32_t addr, testval;
552 /* Get the base address */
553 err = pci_device_cfg_read_u32(dev, &addr, bar);
557 /* Test write all ones to the register, then restore it. */
558 err = pci_device_cfg_write_u32(dev, 0xffffffff, bar);
561 pci_device_cfg_read_u32(dev, &testval, bar);
562 err = pci_device_cfg_write_u32(dev, addr, bar);
565 dev->regions[i].is_IO = 1;
567 dev->regions[i].is_64 = 1;
569 dev->regions[i].is_prefetchable = 1;
572 dev->regions[i].size = get_test_val_size(testval);
574 /* Set the base address value */
575 if (dev->regions[i].is_64) {
578 err = pci_device_cfg_read_u32(dev, &top, bar + 4);
582 dev->regions[i].base_addr = ((uint64_t)top << 32) |
587 dev->regions[i].base_addr = get_map_base(addr);
591 /* If it's a VGA device, set up the rom size for read_rom using the
594 if ((dev->device_class & 0x00ffff00) ==
595 ((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8)))
597 dev->rom_size = 64 * 1024;
603 #if defined(__CYGWIN__)
606 pci_device_x86_map_range(struct pci_device *dev,
607 struct pci_device_mapping *map)
611 phys.pvPhysAddress = (DWORD64)(DWORD32)map->base;
612 phys.dwPhysMemSizeInBytes = map->size;
614 map->memory = (PDWORD)MapPhysToLin(&phys);
615 if (map->memory == NULL)
622 pci_device_x86_unmap_range(struct pci_device *dev,
623 struct pci_device_mapping *map)
627 phys.pvPhysAddress = (DWORD64)(DWORD32)map->base;
628 phys.dwPhysMemSizeInBytes = map->size;
630 if (!UnmapPhysicalMemory(&phys))
639 pci_device_x86_map_range(struct pci_device *dev,
640 struct pci_device_mapping *map)
642 int memfd = open("/dev/mem", O_RDWR | O_CLOEXEC);
643 int prot = PROT_READ;
648 if (map->flags & PCI_DEV_MAP_FLAG_WRITABLE)
651 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, memfd, map->base);
653 if (map->memory == MAP_FAILED)
660 pci_device_x86_unmap_range(struct pci_device *dev,
661 struct pci_device_mapping *map)
663 return pci_device_generic_unmap_range(dev, map);
669 pci_device_x86_read(struct pci_device *dev, void *data,
670 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read)
672 struct pci_system_x86 *pci_sys_x86 = (struct pci_system_x86 *) pci_sys;
677 int toread = 1 << (ffs(0x4 + (offset & 0x03)) - 1);
681 err = pci_sys_x86->read(dev->bus, dev->dev, dev->func, offset, data, toread);
686 data = (char*)data + toread;
688 *bytes_read += toread;
694 pci_device_x86_write(struct pci_device *dev, const void *data,
695 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written)
697 struct pci_system_x86 *pci_sys_x86 = (struct pci_system_x86 *) pci_sys;
705 if (towrite > 4 - (offset & 0x3))
706 towrite = 4 - (offset & 0x3);
708 err = pci_sys_x86->write(dev->bus, dev->dev, dev->func, offset, data, towrite);
713 data = (const char*)data + towrite;
715 *bytes_written += towrite;
721 pci_system_x86_destroy(void)
726 static struct pci_io_handle *
727 pci_device_x86_open_legacy_io(struct pci_io_handle *ret,
728 struct pci_device *dev, pciaddr_t base, pciaddr_t size)
740 pci_device_x86_close_io(struct pci_device *dev, struct pci_io_handle *handle)
742 /* Like in the Linux case, do not disable I/O, as it may be opened several
743 * times, and closed fewer times. */
744 /* x86_disable_io(); */
748 pci_device_x86_read32(struct pci_io_handle *handle, uint32_t reg)
750 return inl(reg + handle->base);
754 pci_device_x86_read16(struct pci_io_handle *handle, uint32_t reg)
756 return inw(reg + handle->base);
760 pci_device_x86_read8(struct pci_io_handle *handle, uint32_t reg)
762 return inb(reg + handle->base);
766 pci_device_x86_write32(struct pci_io_handle *handle, uint32_t reg,
769 outl(data, reg + handle->base);
773 pci_device_x86_write16(struct pci_io_handle *handle, uint32_t reg,
776 outw(data, reg + handle->base);
780 pci_device_x86_write8(struct pci_io_handle *handle, uint32_t reg,
783 outb(data, reg + handle->base);
787 pci_device_x86_map_legacy(struct pci_device *dev, pciaddr_t base,
788 pciaddr_t size, unsigned map_flags, void **addr)
790 struct pci_device_mapping map;
795 map.flags = map_flags;
796 err = pci_device_x86_map_range(dev, &map);
803 pci_device_x86_unmap_legacy(struct pci_device *dev, void *addr,
806 struct pci_device_mapping map;
812 return pci_device_x86_unmap_range(dev, &map);
815 static const struct pci_system_methods x86_pci_methods = {
816 .destroy = pci_system_x86_destroy,
817 .read_rom = pci_device_x86_read_rom,
818 .probe = pci_device_x86_probe,
819 .map_range = pci_device_x86_map_range,
820 .unmap_range = pci_device_x86_unmap_range,
821 .read = pci_device_x86_read,
822 .write = pci_device_x86_write,
823 .fill_capabilities = pci_fill_capabilities_generic,
824 .open_legacy_io = pci_device_x86_open_legacy_io,
825 .close_io = pci_device_x86_close_io,
826 .read32 = pci_device_x86_read32,
827 .read16 = pci_device_x86_read16,
828 .read8 = pci_device_x86_read8,
829 .write32 = pci_device_x86_write32,
830 .write16 = pci_device_x86_write16,
831 .write8 = pci_device_x86_write8,
832 .map_legacy = pci_device_x86_map_legacy,
833 .unmap_legacy = pci_device_x86_unmap_legacy,
836 static int pci_probe(struct pci_system_x86 *pci_sys_x86)
838 if (pci_system_x86_conf1_probe() == 0) {
839 pci_sys_x86->read = pci_system_x86_conf1_read;
840 pci_sys_x86->write = pci_system_x86_conf1_write;
841 if (pci_system_x86_check(pci_sys_x86) == 0)
845 if (pci_system_x86_conf2_probe() == 0) {
846 pci_sys_x86->read = pci_system_x86_conf2_read;
847 pci_sys_x86->write = pci_system_x86_conf2_write;
848 if (pci_system_x86_check(pci_sys_x86) == 0)
856 pci_system_x86_create(void)
858 struct pci_device_private *device;
859 int ret, bus, dev, ndevs, func, nfuncs;
860 struct pci_system_x86 *pci_sys_x86;
863 ret = x86_enable_io();
867 pci_sys_x86 = calloc(1, sizeof(struct pci_system_x86));
868 if (pci_sys_x86 == NULL) {
872 pci_sys = &pci_sys_x86->system;
874 ret = pci_probe(pci_sys_x86);
882 pci_sys->methods = &x86_pci_methods;
885 for (bus = 0; bus < 256; bus++) {
886 for (dev = 0; dev < 32; dev++) {
887 nfuncs = pci_nfuncs(pci_sys_x86, bus, dev);
888 for (func = 0; func < nfuncs; func++) {
889 if (pci_sys_x86->read(bus, dev, func, PCI_VENDOR_ID, ®, sizeof(reg)) != 0)
891 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
892 PCI_VENDOR(reg) == 0)
899 pci_sys->num_devices = ndevs;
900 pci_sys->devices = calloc(ndevs, sizeof(struct pci_device_private));
901 if (pci_sys->devices == NULL) {
908 device = pci_sys->devices;
909 for (bus = 0; bus < 256; bus++) {
910 for (dev = 0; dev < 32; dev++) {
911 nfuncs = pci_nfuncs(pci_sys_x86, bus, dev);
912 for (func = 0; func < nfuncs; func++) {
913 if (pci_sys_x86->read(bus, dev, func, PCI_VENDOR_ID, ®, sizeof(reg)) != 0)
915 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
916 PCI_VENDOR(reg) == 0)
918 device->base.domain = 0;
919 device->base.bus = bus;
920 device->base.dev = dev;
921 device->base.func = func;
922 device->base.vendor_id = PCI_VENDOR(reg);
923 device->base.device_id = PCI_DEVICE(reg);
925 if (pci_sys_x86->read(bus, dev, func, PCI_CLASS, ®, sizeof(reg)) != 0)
927 device->base.device_class = reg >> 8;
928 device->base.revision = reg & 0xFF;
930 if (pci_sys_x86->read(bus, dev, func, PCI_SUB_VENDOR_ID, ®, sizeof(reg)) != 0)
932 device->base.subvendor_id = PCI_VENDOR(reg);
933 device->base.subdevice_id = PCI_DEVICE(reg);