stack/hcic/hcicmds.cc

   1 /******************************************************************************
   2 *
   3 *  Copyright (C) 1999-2012 Broadcom Corporation
   4 *
   5 *  Licensed under the Apache License, Version 2.0 (the "License");
   6 *  you may not use this file except in compliance with the License.
   7 *  You may obtain a copy of the License at:
   8 *
   9 *  http://www.apache.org/licenses/LICENSE-2.0
  10 *
  11 *  Unless required by applicable law or agreed to in writing, software
  12 *  distributed under the License is distributed on an "AS IS" BASIS,
  13 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14 *  See the License for the specific language governing permissions and
  15 *  limitations under the License.
  16 *
  17 ******************************************************************************/
  18
  19 /******************************************************************************
  20  *
  21  *  This file contains function of the HCIC unit to format and send HCI
  22  *  commands.
  23  *
  24  ******************************************************************************/
  25
  26 #include "bt_common.h"
  27 #include "bt_target.h"
  28 #include "btu.h"
  29 #include "hcidefs.h"
  30 #include "hcimsgs.h"
  31
  32 #include <base/bind.h>
  33 #include <stddef.h>
  34 #include <string.h>
  35
  36 #include "btm_int.h" /* Included for UIPC_* macro definitions */
  37
  38 void btsnd_hcic_inquiry(const LAP inq_lap, uint8_t duration,
  39                         uint8_t response_cnt) {
  40   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
  41   uint8_t* pp = (uint8_t*)(p + 1);
  42
  43   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQUIRY;
  44   p->offset = 0;
  45
  46   UINT16_TO_STREAM(pp, HCI_INQUIRY);
  47   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_INQUIRY);
  48
  49   LAP_TO_STREAM(pp, inq_lap);
  50   UINT8_TO_STREAM(pp, duration);
  51   UINT8_TO_STREAM(pp, response_cnt);
  52
  53   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
  54 }
  55
  56 void btsnd_hcic_inq_cancel(void) {
  57   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
  58   uint8_t* pp = (uint8_t*)(p + 1);
  59
  60   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQ_CANCEL;
  61   p->offset = 0;
  62   UINT16_TO_STREAM(pp, HCI_INQUIRY_CANCEL);
  63   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_INQ_CANCEL);
  64
  65   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
  66 }
  67
  68 void btsnd_hcic_per_inq_mode(uint16_t max_period, uint16_t min_period,
  69                              const LAP inq_lap, uint8_t duration,
  70                              uint8_t response_cnt) {
  71   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
  72   uint8_t* pp = (uint8_t*)(p + 1);
  73
  74   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PER_INQ_MODE;
  75   p->offset = 0;
  76
  77   UINT16_TO_STREAM(pp, HCI_PERIODIC_INQUIRY_MODE);
  78   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PER_INQ_MODE);
  79
  80   UINT16_TO_STREAM(pp, max_period);
  81   UINT16_TO_STREAM(pp, min_period);
  82   LAP_TO_STREAM(pp, inq_lap);
  83   UINT8_TO_STREAM(pp, duration);
  84   UINT8_TO_STREAM(pp, response_cnt);
  85
  86   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
  87 }
  88
  89 void btsnd_hcic_exit_per_inq(void) {
  90   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
  91   uint8_t* pp = (uint8_t*)(p + 1);
  92
  93   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXIT_PER_INQ;
  94   p->offset = 0;
  95   UINT16_TO_STREAM(pp, HCI_EXIT_PERIODIC_INQUIRY_MODE);
  96   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXIT_PER_INQ);
  97
  98   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
  99 }
 100
 101 void btsnd_hcic_create_conn(const RawAddress& dest, uint16_t packet_types,
 102                             uint8_t page_scan_rep_mode, uint8_t page_scan_mode,
 103                             uint16_t clock_offset, uint8_t allow_switch) {
 104   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 105   uint8_t* pp = (uint8_t*)(p + 1);
 106
 107 #ifndef BT_10A
 108   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN;
 109 #else
 110   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN - 1;
 111 #endif
 112   p->offset = 0;
 113
 114   UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION);
 115 #ifndef BT_10A
 116   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN);
 117 #else
 118   UINT8_TO_STREAM(pp, (HCIC_PARAM_SIZE_CREATE_CONN - 1));
 119 #endif
 120   BDADDR_TO_STREAM(pp, dest);
 121   UINT16_TO_STREAM(pp, packet_types);
 122   UINT8_TO_STREAM(pp, page_scan_rep_mode);
 123   UINT8_TO_STREAM(pp, page_scan_mode);
 124   UINT16_TO_STREAM(pp, clock_offset);
 125 #if !defined(BT_10A)
 126   UINT8_TO_STREAM(pp, allow_switch);
 127 #endif
 128   btm_acl_paging(p, dest);
 129 }
 130
 131 void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) {
 132   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 133   uint8_t* pp = (uint8_t*)(p + 1);
 134
 135   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT;
 136   p->offset = 0;
 137
 138   UINT16_TO_STREAM(pp, HCI_DISCONNECT);
 139   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT);
 140   UINT16_TO_STREAM(pp, handle);
 141   UINT8_TO_STREAM(pp, reason);
 142
 143   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 144 }
 145
 146 #if (BTM_SCO_INCLUDED == TRUE)
 147 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) {
 148   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 149   uint8_t* pp = (uint8_t*)(p + 1);
 150
 151   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN;
 152   p->offset = 0;
 153
 154   UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION);
 155   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN);
 156
 157   UINT16_TO_STREAM(pp, handle);
 158   UINT16_TO_STREAM(pp, packet_types);
 159
 160   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 161 }
 162 #endif /* BTM_SCO_INCLUDED */
 163
 164 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) {
 165   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 166   uint8_t* pp = (uint8_t*)(p + 1);
 167
 168   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL;
 169   p->offset = 0;
 170
 171   UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL);
 172   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL);
 173
 174   BDADDR_TO_STREAM(pp, dest);
 175
 176   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 177 }
 178
 179 void btsnd_hcic_accept_conn(const RawAddress& dest, uint8_t role) {
 180   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 181   uint8_t* pp = (uint8_t*)(p + 1);
 182
 183   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN;
 184   p->offset = 0;
 185
 186   UINT16_TO_STREAM(pp, HCI_ACCEPT_CONNECTION_REQUEST);
 187   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_CONN);
 188   BDADDR_TO_STREAM(pp, dest);
 189   UINT8_TO_STREAM(pp, role);
 190
 191   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 192 }
 193
 194 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) {
 195   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 196   uint8_t* pp = (uint8_t*)(p + 1);
 197
 198   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN;
 199   p->offset = 0;
 200
 201   UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST);
 202   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN);
 203
 204   BDADDR_TO_STREAM(pp, dest);
 205   UINT8_TO_STREAM(pp, reason);
 206
 207   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 208 }
 209
 210 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr,
 211                                    LINK_KEY link_key) {
 212   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 213   uint8_t* pp = (uint8_t*)(p + 1);
 214
 215   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY;
 216   p->offset = 0;
 217
 218   UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY);
 219   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY);
 220
 221   BDADDR_TO_STREAM(pp, bd_addr);
 222   ARRAY16_TO_STREAM(pp, link_key);
 223
 224   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 225 }
 226
 227 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) {
 228   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 229   uint8_t* pp = (uint8_t*)(p + 1);
 230
 231   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY;
 232   p->offset = 0;
 233
 234   UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY);
 235   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY);
 236
 237   BDADDR_TO_STREAM(pp, bd_addr);
 238
 239   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 240 }
 241
 242 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr,
 243                                    uint8_t pin_code_len, PIN_CODE pin_code) {
 244   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 245   uint8_t* pp = (uint8_t*)(p + 1);
 246   int i;
 247
 248   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY;
 249   p->offset = 0;
 250
 251   UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY);
 252   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY);
 253
 254   BDADDR_TO_STREAM(pp, bd_addr);
 255   UINT8_TO_STREAM(pp, pin_code_len);
 256
 257   for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++;
 258
 259   for (; i < PIN_CODE_LEN; i++) *pp++ = 0;
 260
 261   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 262 }
 263
 264 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) {
 265   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 266   uint8_t* pp = (uint8_t*)(p + 1);
 267
 268   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY;
 269   p->offset = 0;
 270
 271   UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY);
 272   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY);
 273
 274   BDADDR_TO_STREAM(pp, bd_addr);
 275
 276   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 277 }
 278
 279 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) {
 280   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 281   uint8_t* pp = (uint8_t*)(p + 1);
 282
 283   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE;
 284   p->offset = 0;
 285
 286   UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE);
 287   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE);
 288
 289   UINT16_TO_STREAM(pp, handle);
 290   UINT16_TO_STREAM(pp, packet_types);
 291
 292   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 293 }
 294
 295 void btsnd_hcic_auth_request(uint16_t handle) {
 296   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 297   uint8_t* pp = (uint8_t*)(p + 1);
 298
 299   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 300   p->offset = 0;
 301
 302   UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED);
 303   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 304
 305   UINT16_TO_STREAM(pp, handle);
 306
 307   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 308 }
 309
 310 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) {
 311   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 312   uint8_t* pp = (uint8_t*)(p + 1);
 313
 314   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT;
 315   p->offset = 0;
 316
 317   UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION);
 318   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT);
 319
 320   UINT16_TO_STREAM(pp, handle);
 321   UINT8_TO_STREAM(pp, enable);
 322
 323   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 324 }
 325
 326 void btsnd_hcic_rmt_name_req(const RawAddress& bd_addr,
 327                              uint8_t page_scan_rep_mode, uint8_t page_scan_mode,
 328                              uint16_t clock_offset) {
 329   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 330   uint8_t* pp = (uint8_t*)(p + 1);
 331
 332   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ;
 333   p->offset = 0;
 334
 335   UINT16_TO_STREAM(pp, HCI_RMT_NAME_REQUEST);
 336   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_NAME_REQ);
 337
 338   BDADDR_TO_STREAM(pp, bd_addr);
 339   UINT8_TO_STREAM(pp, page_scan_rep_mode);
 340   UINT8_TO_STREAM(pp, page_scan_mode);
 341   UINT16_TO_STREAM(pp, clock_offset);
 342
 343   btm_acl_paging(p, bd_addr);
 344 }
 345
 346 void btsnd_hcic_rmt_name_req_cancel(const RawAddress& bd_addr) {
 347   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 348   uint8_t* pp = (uint8_t*)(p + 1);
 349
 350   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL;
 351   p->offset = 0;
 352
 353   UINT16_TO_STREAM(pp, HCI_RMT_NAME_REQUEST_CANCEL);
 354   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL);
 355
 356   BDADDR_TO_STREAM(pp, bd_addr);
 357
 358   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 359 }
 360
 361 void btsnd_hcic_rmt_features_req(uint16_t handle) {
 362   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 363   uint8_t* pp = (uint8_t*)(p + 1);
 364
 365   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 366   p->offset = 0;
 367
 368   UINT16_TO_STREAM(pp, HCI_READ_RMT_FEATURES);
 369   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 370
 371   UINT16_TO_STREAM(pp, handle);
 372
 373   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 374 }
 375
 376 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) {
 377   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 378   uint8_t* pp = (uint8_t*)(p + 1);
 379
 380   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES;
 381   p->offset = 0;
 382
 383   UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES);
 384   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES);
 385
 386   UINT16_TO_STREAM(pp, handle);
 387   UINT8_TO_STREAM(pp, page_num);
 388
 389   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 390 }
 391
 392 void btsnd_hcic_rmt_ver_req(uint16_t handle) {
 393   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 394   uint8_t* pp = (uint8_t*)(p + 1);
 395
 396   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 397   p->offset = 0;
 398
 399   UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO);
 400   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 401
 402   UINT16_TO_STREAM(pp, handle);
 403
 404   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 405 }
 406
 407 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) {
 408   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 409   uint8_t* pp = (uint8_t*)(p + 1);
 410
 411   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 412   p->offset = 0;
 413
 414   UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET);
 415   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 416
 417   UINT16_TO_STREAM(pp, handle);
 418
 419   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 420 }
 421
 422 void btsnd_hcic_read_lmp_handle(uint16_t handle) {
 423   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 424   uint8_t* pp = (uint8_t*)(p + 1);
 425
 426   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 427   p->offset = 0;
 428
 429   UINT16_TO_STREAM(pp, HCI_READ_LMP_HANDLE);
 430   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 431
 432   UINT16_TO_STREAM(pp, handle);
 433
 434   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 435 }
 436
 437 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth,
 438                                 uint32_t receive_bandwidth,
 439                                 uint16_t max_latency, uint16_t voice,
 440                                 uint8_t retrans_effort, uint16_t packet_types) {
 441   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 442   uint8_t* pp = (uint8_t*)(p + 1);
 443
 444   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO;
 445   p->offset = 0;
 446
 447   UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION);
 448   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO);
 449
 450   UINT16_TO_STREAM(pp, handle);
 451   UINT32_TO_STREAM(pp, transmit_bandwidth);
 452   UINT32_TO_STREAM(pp, receive_bandwidth);
 453   UINT16_TO_STREAM(pp, max_latency);
 454   UINT16_TO_STREAM(pp, voice);
 455   UINT8_TO_STREAM(pp, retrans_effort);
 456   UINT16_TO_STREAM(pp, packet_types);
 457
 458   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 459 }
 460
 461 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr,
 462                                  uint32_t transmit_bandwidth,
 463                                  uint32_t receive_bandwidth,
 464                                  uint16_t max_latency, uint16_t content_fmt,
 465                                  uint8_t retrans_effort,
 466                                  uint16_t packet_types) {
 467   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 468   uint8_t* pp = (uint8_t*)(p + 1);
 469
 470   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO;
 471   p->offset = 0;
 472
 473   UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION);
 474   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO);
 475
 476   BDADDR_TO_STREAM(pp, bd_addr);
 477   UINT32_TO_STREAM(pp, transmit_bandwidth);
 478   UINT32_TO_STREAM(pp, receive_bandwidth);
 479   UINT16_TO_STREAM(pp, max_latency);
 480   UINT16_TO_STREAM(pp, content_fmt);
 481   UINT8_TO_STREAM(pp, retrans_effort);
 482   UINT16_TO_STREAM(pp, packet_types);
 483
 484   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 485 }
 486
 487 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) {
 488   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 489   uint8_t* pp = (uint8_t*)(p + 1);
 490
 491   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO;
 492   p->offset = 0;
 493
 494   UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION);
 495   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO);
 496
 497   BDADDR_TO_STREAM(pp, bd_addr);
 498   UINT8_TO_STREAM(pp, reason);
 499
 500   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 501 }
 502
 503 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period,
 504                           uint16_t min_hold_period) {
 505   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 506   uint8_t* pp = (uint8_t*)(p + 1);
 507
 508   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE;
 509   p->offset = 0;
 510
 511   UINT16_TO_STREAM(pp, HCI_HOLD_MODE);
 512   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE);
 513
 514   UINT16_TO_STREAM(pp, handle);
 515   UINT16_TO_STREAM(pp, max_hold_period);
 516   UINT16_TO_STREAM(pp, min_hold_period);
 517
 518   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 519 }
 520
 521 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period,
 522                            uint16_t min_sniff_period, uint16_t sniff_attempt,
 523                            uint16_t sniff_timeout) {
 524   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 525   uint8_t* pp = (uint8_t*)(p + 1);
 526
 527   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE;
 528   p->offset = 0;
 529
 530   UINT16_TO_STREAM(pp, HCI_SNIFF_MODE);
 531   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE);
 532
 533   UINT16_TO_STREAM(pp, handle);
 534   UINT16_TO_STREAM(pp, max_sniff_period);
 535   UINT16_TO_STREAM(pp, min_sniff_period);
 536   UINT16_TO_STREAM(pp, sniff_attempt);
 537   UINT16_TO_STREAM(pp, sniff_timeout);
 538
 539   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 540 }
 541
 542 void btsnd_hcic_exit_sniff_mode(uint16_t handle) {
 543   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 544   uint8_t* pp = (uint8_t*)(p + 1);
 545
 546   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 547   p->offset = 0;
 548
 549   UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE);
 550   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 551
 552   UINT16_TO_STREAM(pp, handle);
 553
 554   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 555 }
 556
 557 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval,
 558                           uint16_t beacon_min_interval) {
 559   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 560   uint8_t* pp = (uint8_t*)(p + 1);
 561
 562   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE;
 563   p->offset = 0;
 564
 565   UINT16_TO_STREAM(pp, HCI_PARK_MODE);
 566   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE);
 567
 568   UINT16_TO_STREAM(pp, handle);
 569   UINT16_TO_STREAM(pp, beacon_max_interval);
 570   UINT16_TO_STREAM(pp, beacon_min_interval);
 571
 572   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 573 }
 574
 575 void btsnd_hcic_exit_park_mode(uint16_t handle) {
 576   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 577   uint8_t* pp = (uint8_t*)(p + 1);
 578
 579   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
 580   p->offset = 0;
 581
 582   UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE);
 583   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
 584
 585   UINT16_TO_STREAM(pp, handle);
 586
 587   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 588 }
 589
 590 void btsnd_hcic_qos_setup(uint16_t handle, uint8_t flags, uint8_t service_type,
 591                           uint32_t token_rate, uint32_t peak, uint32_t latency,
 592                           uint32_t delay_var) {
 593   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 594   uint8_t* pp = (uint8_t*)(p + 1);
 595
 596   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_QOS_SETUP;
 597   p->offset = 0;
 598
 599   UINT16_TO_STREAM(pp, HCI_QOS_SETUP);
 600   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_QOS_SETUP);
 601
 602   UINT16_TO_STREAM(pp, handle);
 603   UINT8_TO_STREAM(pp, flags);
 604   UINT8_TO_STREAM(pp, service_type);
 605   UINT32_TO_STREAM(pp, token_rate);
 606   UINT32_TO_STREAM(pp, peak);
 607   UINT32_TO_STREAM(pp, latency);
 608   UINT32_TO_STREAM(pp, delay_var);
 609
 610   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 611 }
 612
 613 void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) {
 614   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 615   uint8_t* pp = (uint8_t*)(p + 1);
 616
 617   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE;
 618   p->offset = 0;
 619
 620   UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE);
 621   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE);
 622
 623   BDADDR_TO_STREAM(pp, bd_addr);
 624   UINT8_TO_STREAM(pp, role);
 625
 626   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 627 }
 628
 629 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) {
 630   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 631   uint8_t* pp = (uint8_t*)(p + 1);
 632
 633   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET;
 634   p->offset = 0;
 635   UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS);
 636   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET);
 637
 638   UINT16_TO_STREAM(pp, handle);
 639   UINT16_TO_STREAM(pp, settings);
 640
 641   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 642 }
 643
 644 void btsnd_hcic_write_def_policy_set(uint16_t settings) {
 645   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 646   uint8_t* pp = (uint8_t*)(p + 1);
 647
 648   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET;
 649   p->offset = 0;
 650   UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS);
 651   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET);
 652
 653   UINT16_TO_STREAM(pp, settings);
 654
 655   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 656 }
 657
 658 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type,
 659                                  uint8_t* filt_cond, uint8_t filt_cond_len) {
 660   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 661   uint8_t* pp = (uint8_t*)(p + 1);
 662
 663   p->offset = 0;
 664
 665   UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER);
 666
 667   if (filt_type) {
 668     p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len);
 669     UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len));
 670
 671     UINT8_TO_STREAM(pp, filt_type);
 672     UINT8_TO_STREAM(pp, filt_cond_type);
 673
 674     if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) {
 675       DEVCLASS_TO_STREAM(pp, filt_cond);
 676       filt_cond += DEV_CLASS_LEN;
 677       DEVCLASS_TO_STREAM(pp, filt_cond);
 678       filt_cond += DEV_CLASS_LEN;
 679
 680       filt_cond_len -= (2 * DEV_CLASS_LEN);
 681     } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) {
 682       BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond));
 683       filt_cond += BD_ADDR_LEN;
 684
 685       filt_cond_len -= BD_ADDR_LEN;
 686     }
 687
 688     if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len);
 689   } else {
 690     p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1);
 691     UINT8_TO_STREAM(pp, 1);
 692
 693     UINT8_TO_STREAM(pp, filt_type);
 694   }
 695
 696   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 697 }
 698
 699 void btsnd_hcic_write_pin_type(uint8_t type) {
 700   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 701   uint8_t* pp = (uint8_t*)(p + 1);
 702
 703   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
 704   p->offset = 0;
 705
 706   UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE);
 707   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
 708
 709   UINT8_TO_STREAM(pp, type);
 710
 711   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 712 }
 713
 714 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr,
 715                                   bool delete_all_flag) {
 716   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 717   uint8_t* pp = (uint8_t*)(p + 1);
 718
 719   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY;
 720   p->offset = 0;
 721
 722   UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY);
 723   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY);
 724
 725   BDADDR_TO_STREAM(pp, bd_addr);
 726   UINT8_TO_STREAM(pp, delete_all_flag);
 727
 728   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 729 }
 730
 731 void btsnd_hcic_change_name(BD_NAME name) {
 732   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 733   uint8_t* pp = (uint8_t*)(p + 1);
 734   uint16_t len = strlen((char*)name) + 1;
 735
 736   memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME);
 737
 738   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME;
 739   p->offset = 0;
 740
 741   UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME);
 742   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME);
 743
 744   if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME;
 745
 746   ARRAY_TO_STREAM(pp, name, len);
 747
 748   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 749 }
 750
 751 void btsnd_hcic_read_name(void) {
 752   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 753   uint8_t* pp = (uint8_t*)(p + 1);
 754
 755   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
 756   p->offset = 0;
 757
 758   UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME);
 759   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
 760
 761   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 762 }
 763
 764 void btsnd_hcic_write_page_tout(uint16_t timeout) {
 765   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 766   uint8_t* pp = (uint8_t*)(p + 1);
 767
 768   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
 769   p->offset = 0;
 770
 771   UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT);
 772   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
 773
 774   UINT16_TO_STREAM(pp, timeout);
 775
 776   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 777 }
 778
 779 void btsnd_hcic_write_scan_enable(uint8_t flag) {
 780   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 781   uint8_t* pp = (uint8_t*)(p + 1);
 782
 783   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
 784   p->offset = 0;
 785
 786   UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE);
 787   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
 788
 789   UINT8_TO_STREAM(pp, flag);
 790
 791   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 792 }
 793
 794 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) {
 795   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 796   uint8_t* pp = (uint8_t*)(p + 1);
 797
 798   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG;
 799   p->offset = 0;
 800
 801   UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG);
 802   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG);
 803
 804   UINT16_TO_STREAM(pp, interval);
 805   UINT16_TO_STREAM(pp, window);
 806
 807   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 808 }
 809
 810 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) {
 811   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 812   uint8_t* pp = (uint8_t*)(p + 1);
 813
 814   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG;
 815   p->offset = 0;
 816
 817   UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG);
 818   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG);
 819
 820   UINT16_TO_STREAM(pp, interval);
 821   UINT16_TO_STREAM(pp, window);
 822
 823   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 824 }
 825
 826 void btsnd_hcic_write_auth_enable(uint8_t flag) {
 827   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 828   uint8_t* pp = (uint8_t*)(p + 1);
 829
 830   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
 831   p->offset = 0;
 832
 833   UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE);
 834   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
 835
 836   UINT8_TO_STREAM(pp, flag);
 837
 838   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 839 }
 840
 841 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) {
 842   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 843   uint8_t* pp = (uint8_t*)(p + 1);
 844
 845   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3;
 846   p->offset = 0;
 847
 848   UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE);
 849   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3);
 850
 851   DEVCLASS_TO_STREAM(pp, dev_class);
 852
 853   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 854 }
 855
 856 void btsnd_hcic_write_voice_settings(uint16_t flags) {
 857   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 858   uint8_t* pp = (uint8_t*)(p + 1);
 859
 860   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
 861   p->offset = 0;
 862
 863   UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS);
 864   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
 865
 866   UINT16_TO_STREAM(pp, flags);
 867
 868   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 869 }
 870
 871 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) {
 872   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 873   uint8_t* pp = (uint8_t*)(p + 1);
 874
 875   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT;
 876   p->offset = 0;
 877
 878   UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
 879   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
 880
 881   UINT16_TO_STREAM(pp, handle);
 882   UINT16_TO_STREAM(pp, tout);
 883
 884   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 885 }
 886
 887 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) {
 888   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 889   uint8_t* pp = (uint8_t*)(p + 1);
 890
 891   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER;
 892   p->offset = 0;
 893
 894   UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL);
 895   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER);
 896
 897   UINT16_TO_STREAM(pp, handle);
 898   UINT8_TO_STREAM(pp, type);
 899
 900   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 901 }
 902
 903 void btsnd_hcic_host_num_xmitted_pkts(uint8_t num_handles, uint16_t* handle,
 904                                       uint16_t* num_pkts) {
 905   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 906   uint8_t* pp = (uint8_t*)(p + 1);
 907
 908   p->len = HCIC_PREAMBLE_SIZE + 1 + (num_handles * 4);
 909   p->offset = 0;
 910
 911   UINT16_TO_STREAM(pp, HCI_HOST_NUM_PACKETS_DONE);
 912   UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE);
 913
 914   UINT8_TO_STREAM(pp, num_handles);
 915
 916   for (int i = 0; i < num_handles; i++) {
 917     UINT16_TO_STREAM(pp, handle[i]);
 918     UINT16_TO_STREAM(pp, num_pkts[i]);
 919   }
 920
 921   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 922 }
 923
 924 void btsnd_hcic_write_link_super_tout(uint8_t local_controller_id,
 925                                       uint16_t handle, uint16_t timeout) {
 926   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 927   uint8_t* pp = (uint8_t*)(p + 1);
 928
 929   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT;
 930   p->offset = 0;
 931
 932   UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT);
 933   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT);
 934
 935   UINT16_TO_STREAM(pp, handle);
 936   UINT16_TO_STREAM(pp, timeout);
 937
 938   btu_hcif_send_cmd(local_controller_id, p);
 939 }
 940
 941 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) {
 942   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 943   uint8_t* pp = (uint8_t*)(p + 1);
 944
 945   p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac);
 946   p->offset = 0;
 947
 948   UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP);
 949   UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE);
 950
 951   UINT8_TO_STREAM(pp, num_cur_iac);
 952
 953   for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]);
 954
 955   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 956 }
 957
 958 /******************************************
 959  *    Lisbon Features
 960  ******************************************/
 961 #if (BTM_SSR_INCLUDED == TRUE)
 962
 963 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat,
 964                                uint16_t min_remote_lat,
 965                                uint16_t min_local_lat) {
 966   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
 967   uint8_t* pp = (uint8_t*)(p + 1);
 968
 969   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE;
 970   p->offset = 0;
 971
 972   UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE);
 973   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE);
 974
 975   UINT16_TO_STREAM(pp, handle);
 976   UINT16_TO_STREAM(pp, max_lat);
 977   UINT16_TO_STREAM(pp, min_remote_lat);
 978   UINT16_TO_STREAM(pp, min_local_lat);
 979
 980   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 981 }
 982 #endif /* BTM_SSR_INCLUDED */
 983
 984 /**** Extended Inquiry Response Commands ****/
 985 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) {
 986   BT_HDR* p = (BT_HDR*)buffer;
 987   uint8_t* pp = (uint8_t*)(p + 1);
 988
 989   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP;
 990   p->offset = 0;
 991
 992   UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE);
 993   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP);
 994
 995   UINT8_TO_STREAM(pp, fec_req);
 996
 997   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
 998 }
 999
1000 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability,
1001                                  uint8_t oob_present, uint8_t auth_req) {
1002   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1003   uint8_t* pp = (uint8_t*)(p + 1);
1004
1005   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP;
1006   p->offset = 0;
1007
1008   UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY);
1009   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP);
1010
1011   BDADDR_TO_STREAM(pp, bd_addr);
1012   UINT8_TO_STREAM(pp, capability);
1013   UINT8_TO_STREAM(pp, oob_present);
1014   UINT8_TO_STREAM(pp, auth_req);
1015
1016   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1017 }
1018
1019 void btsnd_hcic_enhanced_set_up_synchronous_connection(
1020     uint16_t conn_handle, enh_esco_params_t* p_params) {
1021   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1022   uint8_t* pp = (uint8_t*)(p + 1);
1023
1024   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN;
1025   p->offset = 0;
1026
1027   UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION);
1028   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN);
1029
1030   UINT16_TO_STREAM(pp, conn_handle);
1031   UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1032   UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1033   UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1034   UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1035   UINT16_TO_STREAM(pp,
1036                    p_params->transmit_coding_format.vendor_specific_codec_id);
1037   UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1038   UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1039   UINT16_TO_STREAM(pp,
1040                    p_params->receive_coding_format.vendor_specific_codec_id);
1041   UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1042   UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1043   UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1044   UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1045   UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1046   UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1047   UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1048   UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1049   UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1050   UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1051   UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1052   UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1053   UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1054   UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1055   UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1056   UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1057   UINT8_TO_STREAM(pp, p_params->input_data_path);
1058   UINT8_TO_STREAM(pp, p_params->output_data_path);
1059   UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1060   UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1061   UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1062   UINT16_TO_STREAM(pp, p_params->packet_types);
1063   UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1064
1065   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1066 }
1067
1068 void btsnd_hcic_enhanced_accept_synchronous_connection(
1069     const RawAddress& bd_addr, enh_esco_params_t* p_params) {
1070   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1071   uint8_t* pp = (uint8_t*)(p + 1);
1072
1073   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN;
1074   p->offset = 0;
1075
1076   UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION);
1077   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN);
1078
1079   BDADDR_TO_STREAM(pp, bd_addr);
1080   UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1081   UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1082   UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1083   UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1084   UINT16_TO_STREAM(pp,
1085                    p_params->transmit_coding_format.vendor_specific_codec_id);
1086   UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1087   UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1088   UINT16_TO_STREAM(pp,
1089                    p_params->receive_coding_format.vendor_specific_codec_id);
1090   UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1091   UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1092   UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1093   UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1094   UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1095   UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1096   UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1097   UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1098   UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1099   UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1100   UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1101   UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1102   UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1103   UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1104   UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1105   UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1106   UINT8_TO_STREAM(pp, p_params->input_data_path);
1107   UINT8_TO_STREAM(pp, p_params->output_data_path);
1108   UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1109   UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1110   UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1111   UINT16_TO_STREAM(pp, p_params->packet_types);
1112   UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1113
1114   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1115 }
1116
1117 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr,
1118                                      uint8_t err_code) {
1119   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1120   uint8_t* pp = (uint8_t*)(p + 1);
1121
1122   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY;
1123   p->offset = 0;
1124
1125   UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY);
1126   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY);
1127
1128   BDADDR_TO_STREAM(pp, bd_addr);
1129   UINT8_TO_STREAM(pp, err_code);
1130
1131   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1132 }
1133
1134 void btsnd_hcic_read_local_oob_data(void) {
1135   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1136   uint8_t* pp = (uint8_t*)(p + 1);
1137
1138   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB;
1139   p->offset = 0;
1140
1141   UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA);
1142   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB);
1143
1144   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1145 }
1146
1147 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) {
1148   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1149   uint8_t* pp = (uint8_t*)(p + 1);
1150
1151   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY;
1152   p->offset = 0;
1153
1154   if (!is_yes) {
1155     /* Negative reply */
1156     UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY);
1157   } else {
1158     /* Confirmation */
1159     UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY);
1160   }
1161
1162   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY);
1163
1164   BDADDR_TO_STREAM(pp, bd_addr);
1165
1166   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1167 }
1168
1169 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) {
1170   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1171   uint8_t* pp = (uint8_t*)(p + 1);
1172
1173   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY;
1174   p->offset = 0;
1175
1176   UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY);
1177   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY);
1178
1179   BDADDR_TO_STREAM(pp, bd_addr);
1180   UINT32_TO_STREAM(pp, value);
1181
1182   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1183 }
1184
1185 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) {
1186   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1187   uint8_t* pp = (uint8_t*)(p + 1);
1188
1189   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY;
1190   p->offset = 0;
1191
1192   UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY);
1193   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY);
1194
1195   BDADDR_TO_STREAM(pp, bd_addr);
1196
1197   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1198 }
1199
1200 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, uint8_t* p_c,
1201                               uint8_t* p_r) {
1202   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1203   uint8_t* pp = (uint8_t*)(p + 1);
1204
1205   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY;
1206   p->offset = 0;
1207
1208   UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY);
1209   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY);
1210
1211   BDADDR_TO_STREAM(pp, bd_addr);
1212   ARRAY16_TO_STREAM(pp, p_c);
1213   ARRAY16_TO_STREAM(pp, p_r);
1214
1215   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1216 }
1217
1218 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) {
1219   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1220   uint8_t* pp = (uint8_t*)(p + 1);
1221
1222   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY;
1223   p->offset = 0;
1224
1225   UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY);
1226   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY);
1227
1228   BDADDR_TO_STREAM(pp, bd_addr);
1229
1230   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1231 }
1232
1233 void btsnd_hcic_read_inq_tx_power(void) {
1234   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1235   uint8_t* pp = (uint8_t*)(p + 1);
1236
1237   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_TX_POWER;
1238   p->offset = 0;
1239
1240   UINT16_TO_STREAM(pp, HCI_READ_INQ_TX_POWER_LEVEL);
1241   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_TX_POWER);
1242
1243   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1244 }
1245
1246 void btsnd_hcic_send_keypress_notif(const RawAddress& bd_addr, uint8_t notif) {
1247   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1248   uint8_t* pp = (uint8_t*)(p + 1);
1249
1250   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF;
1251   p->offset = 0;
1252
1253   UINT16_TO_STREAM(pp, HCI_SEND_KEYPRESS_NOTIF);
1254   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF);
1255
1256   BDADDR_TO_STREAM(pp, bd_addr);
1257   UINT8_TO_STREAM(pp, notif);
1258
1259   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1260 }
1261
1262 /**** end of Simple Pairing Commands ****/
1263
1264 #if (L2CAP_NON_FLUSHABLE_PB_INCLUDED == TRUE)
1265 void btsnd_hcic_enhanced_flush(uint16_t handle, uint8_t packet_type) {
1266   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1267   uint8_t* pp = (uint8_t*)(p + 1);
1268
1269   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENHANCED_FLUSH;
1270   p->offset = 0;
1271   UINT16_TO_STREAM(pp, HCI_ENHANCED_FLUSH);
1272   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENHANCED_FLUSH);
1273
1274   UINT16_TO_STREAM(pp, handle);
1275   UINT8_TO_STREAM(pp, packet_type);
1276
1277   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1278 }
1279 #endif
1280
1281 /*************************
1282  * End of Lisbon Commands
1283  *************************/
1284
1285 void btsnd_hcic_get_link_quality(uint16_t handle) {
1286   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1287   uint8_t* pp = (uint8_t*)(p + 1);
1288
1289   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1290   p->offset = 0;
1291
1292   UINT16_TO_STREAM(pp, HCI_GET_LINK_QUALITY);
1293   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1294
1295   UINT16_TO_STREAM(pp, handle);
1296
1297   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1298 }
1299
1300 void btsnd_hcic_read_rssi(uint16_t handle) {
1301   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1302   uint8_t* pp = (uint8_t*)(p + 1);
1303
1304   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1305   p->offset = 0;
1306
1307   UINT16_TO_STREAM(pp, HCI_READ_RSSI);
1308   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1309
1310   UINT16_TO_STREAM(pp, handle);
1311
1312   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1313 }
1314
1315 static void read_encryption_key_size_complete(
1316     ReadEncKeySizeCb cb, uint8_t* return_parameters,
1317     uint16_t return_parameters_length) {
1318   uint8_t status;
1319   uint16_t handle;
1320   uint8_t key_size;
1321   STREAM_TO_UINT8(status, return_parameters);
1322   STREAM_TO_UINT16(handle, return_parameters);
1323   STREAM_TO_UINT8(key_size, return_parameters);
1324
1325   std::move(cb).Run(status, handle, key_size);
1326 }
1327
1328 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) {
1329   constexpr uint8_t len = 2;
1330   uint8_t param[len];
1331   memset(param, 0, len);
1332
1333   uint8_t* p = param;
1334   UINT16_TO_STREAM(p, handle);
1335
1336   btu_hcif_send_cmd_with_cb(
1337       FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len,
1338       base::Bind(&read_encryption_key_size_complete, base::Passed(&cb)));
1339 }
1340
1341 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) {
1342   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1343   uint8_t* pp = (uint8_t*)(p + 1);
1344
1345   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1346   p->offset = 0;
1347
1348   UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER);
1349   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1350
1351   UINT16_TO_STREAM(pp, handle);
1352
1353   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1354 }
1355
1356 void btsnd_hcic_read_automatic_flush_timeout(uint16_t handle) {
1357   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1358   uint8_t* pp = (uint8_t*)(p + 1);
1359
1360   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1361   p->offset = 0;
1362
1363   UINT16_TO_STREAM(pp, HCI_READ_AUTOMATIC_FLUSH_TIMEOUT);
1364   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1365
1366   UINT16_TO_STREAM(pp, handle);
1367
1368   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1369 }
1370
1371 void btsnd_hcic_enable_test_mode(void) {
1372   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1373   uint8_t* pp = (uint8_t*)(p + 1);
1374
1375   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1376   p->offset = 0;
1377
1378   UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE);
1379   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1380
1381   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1382 }
1383
1384 void btsnd_hcic_write_inqscan_type(uint8_t type) {
1385   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1386   uint8_t* pp = (uint8_t*)(p + 1);
1387
1388   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1389   p->offset = 0;
1390
1391   UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE);
1392   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1393
1394   UINT8_TO_STREAM(pp, type);
1395
1396   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1397 }
1398
1399 void btsnd_hcic_write_inquiry_mode(uint8_t mode) {
1400   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1401   uint8_t* pp = (uint8_t*)(p + 1);
1402
1403   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1404   p->offset = 0;
1405
1406   UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE);
1407   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1408
1409   UINT8_TO_STREAM(pp, mode);
1410
1411   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1412 }
1413
1414 void btsnd_hcic_write_pagescan_type(uint8_t type) {
1415   BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1416   uint8_t* pp = (uint8_t*)(p + 1);
1417
1418   p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1419   p->offset = 0;
1420
1421   UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE);
1422   UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1423
1424   UINT8_TO_STREAM(pp, type);
1425
1426   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1427 }
1428
1429 /* Must have room to store BT_HDR + max VSC length + callback pointer */
1430 #if (HCI_CMD_BUF_SIZE < 268)
1431 #error "HCI_CMD_BUF_SIZE must be larger than 268"
1432 #endif
1433
1434 void btsnd_hcic_vendor_spec_cmd(void* buffer, uint16_t opcode, uint8_t len,
1435                                 uint8_t* p_data, void* p_cmd_cplt_cback) {
1436   BT_HDR* p = (BT_HDR*)buffer;
1437   uint8_t* pp = (uint8_t*)(p + 1);
1438
1439   p->len = HCIC_PREAMBLE_SIZE + len;
1440   p->offset = sizeof(void*);
1441
1442   *((void**)pp) =
1443       p_cmd_cplt_cback; /* Store command complete callback in buffer */
1444   pp += sizeof(void*);  /* Skip over callback pointer */
1445
1446   UINT16_TO_STREAM(pp, HCI_GRP_VENDOR_SPECIFIC | opcode);
1447   UINT8_TO_STREAM(pp, len);
1448   ARRAY_TO_STREAM(pp, p_data, len);
1449
1450   btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1451 }