4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
45 ARMCPU *cpu = ARM_CPU(cs);
46 CPUARMState *env = &cpu->env;
52 env->regs[15] = value & ~1;
53 env->thumb = value & 1;
58 static void arm_cpu_synchronize_from_tb(CPUState *cs,
59 const TranslationBlock *tb)
61 ARMCPU *cpu = ARM_CPU(cs);
62 CPUARMState *env = &cpu->env;
65 * It's OK to look at env for the current mode here, because it's
66 * never possible for an AArch64 TB to chain to an AArch32 TB.
71 env->regs[15] = tb->pc;
74 #endif /* CONFIG_TCG */
76 static bool arm_cpu_has_work(CPUState *cs)
78 ARMCPU *cpu = ARM_CPU(cs);
80 return (cpu->power_state != PSCI_OFF)
81 && cs->interrupt_request &
82 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
83 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
84 | CPU_INTERRUPT_EXITTB);
87 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
90 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
93 entry->opaque = opaque;
95 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
98 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
101 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
104 entry->opaque = opaque;
106 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
109 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
111 /* Reset a single ARMCPRegInfo register */
112 ARMCPRegInfo *ri = value;
113 ARMCPU *cpu = opaque;
115 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
120 ri->resetfn(&cpu->env, ri);
124 /* A zero offset is never possible as it would be regs[0]
125 * so we use it to indicate that reset is being handled elsewhere.
126 * This is basically only used for fields in non-core coprocessors
127 * (like the pxa2xx ones).
129 if (!ri->fieldoffset) {
133 if (cpreg_field_is_64bit(ri)) {
134 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
136 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
140 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
142 /* Purely an assertion check: we've already done reset once,
143 * so now check that running the reset for the cpreg doesn't
144 * change its value. This traps bugs where two different cpregs
145 * both try to reset the same state field but to different values.
147 ARMCPRegInfo *ri = value;
148 ARMCPU *cpu = opaque;
149 uint64_t oldvalue, newvalue;
151 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
155 oldvalue = read_raw_cp_reg(&cpu->env, ri);
156 cp_reg_reset(key, value, opaque);
157 newvalue = read_raw_cp_reg(&cpu->env, ri);
158 assert(oldvalue == newvalue);
161 static void arm_cpu_reset(DeviceState *dev)
163 CPUState *s = CPU(dev);
164 ARMCPU *cpu = ARM_CPU(s);
165 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
166 CPUARMState *env = &cpu->env;
168 acc->parent_reset(dev);
170 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
172 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
173 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
175 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
176 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
177 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
178 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
180 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON;
182 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
183 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
186 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
187 /* 64 bit CPUs always start in 64 bit mode */
189 #if defined(CONFIG_USER_ONLY)
190 env->pstate = PSTATE_MODE_EL0t;
191 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
192 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
193 /* Enable all PAC keys. */
194 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
195 SCTLR_EnDA | SCTLR_EnDB);
196 /* and to the FP/Neon instructions */
197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
198 /* and to the SVE instructions */
199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
200 /* with reasonable vector length */
201 if (cpu_isar_feature(aa64_sve, cpu)) {
202 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
205 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
206 * turning on both here will produce smaller code and otherwise
207 * make no difference to the user-level emulation.
209 * In sve_probe_page, we assume that this is set.
210 * Do not modify this without other changes.
212 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
214 /* Reset into the highest available EL */
215 if (arm_feature(env, ARM_FEATURE_EL3)) {
216 env->pstate = PSTATE_MODE_EL3h;
217 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
218 env->pstate = PSTATE_MODE_EL2h;
220 env->pstate = PSTATE_MODE_EL1h;
222 env->pc = cpu->rvbar;
225 #if defined(CONFIG_USER_ONLY)
226 /* Userspace expects access to cp10 and cp11 for FP/Neon */
227 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
231 #if defined(CONFIG_USER_ONLY)
232 env->uncached_cpsr = ARM_CPU_MODE_USR;
233 /* For user mode we must enable access to coprocessors */
234 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
235 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
236 env->cp15.c15_cpar = 3;
237 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
238 env->cp15.c15_cpar = 1;
243 * If the highest available EL is EL2, AArch32 will start in Hyp
244 * mode; otherwise it starts in SVC. Note that if we start in
245 * AArch64 then these values in the uncached_cpsr will be ignored.
247 if (arm_feature(env, ARM_FEATURE_EL2) &&
248 !arm_feature(env, ARM_FEATURE_EL3)) {
249 env->uncached_cpsr = ARM_CPU_MODE_HYP;
251 env->uncached_cpsr = ARM_CPU_MODE_SVC;
253 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
255 if (arm_feature(env, ARM_FEATURE_M)) {
256 uint32_t initial_msp; /* Loaded from 0x0 */
257 uint32_t initial_pc; /* Loaded from 0x4 */
261 if (cpu_isar_feature(aa32_lob, cpu)) {
263 * LTPSIZE is constant 4 if MVE not implemented, and resets
264 * to an UNKNOWN value if MVE is implemented. We choose to
267 env->v7m.ltpsize = 4;
268 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
269 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
270 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
273 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
274 env->v7m.secure = true;
276 /* This bit resets to 0 if security is supported, but 1 if
277 * it is not. The bit is not present in v7M, but we set it
278 * here so we can avoid having to make checks on it conditional
279 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
281 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
283 * Set NSACR to indicate "NS access permitted to everything";
284 * this avoids having to have all the tests of it being
285 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
286 * v8.1M the guest-visible value of NSACR in a CPU without the
287 * Security Extension is 0xcff.
289 env->v7m.nsacr = 0xcff;
292 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
293 * that it resets to 1, so QEMU always does that rather than making
294 * it dependent on CPU model. In v8M it is RES1.
296 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
297 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
298 if (arm_feature(env, ARM_FEATURE_V8)) {
299 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
300 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
301 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
303 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
304 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
305 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
308 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
309 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
310 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
311 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
313 /* Unlike A/R profile, M profile defines the reset LR value */
314 env->regs[14] = 0xffffffff;
316 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
318 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
319 vecbase = env->v7m.vecbase[env->v7m.secure];
320 rom = rom_ptr(vecbase, 8);
322 /* Address zero is covered by ROM which hasn't yet been
323 * copied into physical memory.
325 initial_msp = ldl_p(rom);
326 initial_pc = ldl_p(rom + 4);
328 /* Address zero not covered by a ROM blob, or the ROM blob
329 * is in non-modifiable memory and this is a second reset after
330 * it got copied into memory. In the latter case, rom_ptr
331 * will return a NULL pointer and we should use ldl_phys instead.
333 initial_msp = ldl_phys(s->as, vecbase);
334 initial_pc = ldl_phys(s->as, vecbase + 4);
337 env->regs[13] = initial_msp & 0xFFFFFFFC;
338 env->regs[15] = initial_pc & ~1;
339 env->thumb = initial_pc & 1;
342 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
343 * executing as AArch32 then check if highvecs are enabled and
344 * adjust the PC accordingly.
346 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
347 env->regs[15] = 0xFFFF0000;
350 /* M profile requires that reset clears the exclusive monitor;
351 * A profile does not, but clearing it makes more sense than having it
352 * set with an exclusive access on address zero.
354 arm_clear_exclusive(env);
356 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
359 if (arm_feature(env, ARM_FEATURE_PMSA)) {
360 if (cpu->pmsav7_dregion > 0) {
361 if (arm_feature(env, ARM_FEATURE_V8)) {
362 memset(env->pmsav8.rbar[M_REG_NS], 0,
363 sizeof(*env->pmsav8.rbar[M_REG_NS])
364 * cpu->pmsav7_dregion);
365 memset(env->pmsav8.rlar[M_REG_NS], 0,
366 sizeof(*env->pmsav8.rlar[M_REG_NS])
367 * cpu->pmsav7_dregion);
368 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
369 memset(env->pmsav8.rbar[M_REG_S], 0,
370 sizeof(*env->pmsav8.rbar[M_REG_S])
371 * cpu->pmsav7_dregion);
372 memset(env->pmsav8.rlar[M_REG_S], 0,
373 sizeof(*env->pmsav8.rlar[M_REG_S])
374 * cpu->pmsav7_dregion);
376 } else if (arm_feature(env, ARM_FEATURE_V7)) {
377 memset(env->pmsav7.drbar, 0,
378 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
379 memset(env->pmsav7.drsr, 0,
380 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
381 memset(env->pmsav7.dracr, 0,
382 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
385 env->pmsav7.rnr[M_REG_NS] = 0;
386 env->pmsav7.rnr[M_REG_S] = 0;
387 env->pmsav8.mair0[M_REG_NS] = 0;
388 env->pmsav8.mair0[M_REG_S] = 0;
389 env->pmsav8.mair1[M_REG_NS] = 0;
390 env->pmsav8.mair1[M_REG_S] = 0;
393 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
394 if (cpu->sau_sregion > 0) {
395 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
396 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
399 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
400 * the Cortex-M33 does.
405 set_flush_to_zero(1, &env->vfp.standard_fp_status);
406 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
407 set_default_nan_mode(1, &env->vfp.standard_fp_status);
408 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
409 set_float_detect_tininess(float_tininess_before_rounding,
410 &env->vfp.fp_status);
411 set_float_detect_tininess(float_tininess_before_rounding,
412 &env->vfp.standard_fp_status);
413 set_float_detect_tininess(float_tininess_before_rounding,
414 &env->vfp.fp_status_f16);
415 set_float_detect_tininess(float_tininess_before_rounding,
416 &env->vfp.standard_fp_status_f16);
417 #ifndef CONFIG_USER_ONLY
419 kvm_arm_reset_vcpu(cpu);
423 hw_breakpoint_update_all(cpu);
424 hw_watchpoint_update_all(cpu);
425 arm_rebuild_hflags(env);
428 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
429 unsigned int target_el,
430 unsigned int cur_el, bool secure,
433 CPUARMState *env = cs->env_ptr;
434 bool pstate_unmasked;
435 bool unmasked = false;
438 * Don't take exceptions if they target a lower EL.
439 * This check should catch any exceptions that would not be taken
442 if (cur_el > target_el) {
448 pstate_unmasked = !(env->daif & PSTATE_F);
452 pstate_unmasked = !(env->daif & PSTATE_I);
456 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
457 /* VFIQs are only taken when hypervized. */
460 return !(env->daif & PSTATE_F);
462 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
463 /* VIRQs are only taken when hypervized. */
466 return !(env->daif & PSTATE_I);
468 g_assert_not_reached();
472 * Use the target EL, current execution state and SCR/HCR settings to
473 * determine whether the corresponding CPSR bit is used to mask the
476 if ((target_el > cur_el) && (target_el != 1)) {
477 /* Exceptions targeting a higher EL may not be maskable */
478 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
480 * 64-bit masking rules are simple: exceptions to EL3
481 * can't be masked, and exceptions to EL2 can only be
482 * masked from Secure state. The HCR and SCR settings
483 * don't affect the masking logic, only the interrupt routing.
485 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
490 * The old 32-bit-only environment has a more complicated
491 * masking setup. HCR and SCR bits not only affect interrupt
492 * routing but also change the behaviour of masking.
499 * If FIQs are routed to EL3 or EL2 then there are cases where
500 * we override the CPSR.F in determining if the exception is
501 * masked or not. If neither of these are set then we fall back
502 * to the CPSR.F setting otherwise we further assess the state
505 hcr = hcr_el2 & HCR_FMO;
506 scr = (env->cp15.scr_el3 & SCR_FIQ);
509 * When EL3 is 32-bit, the SCR.FW bit controls whether the
510 * CPSR.F bit masks FIQ interrupts when taken in non-secure
511 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
512 * when non-secure but only when FIQs are only routed to EL3.
514 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
518 * When EL3 execution state is 32-bit, if HCR.IMO is set then
519 * we may override the CPSR.I masking when in non-secure state.
520 * The SCR.IRQ setting has already been taken into consideration
521 * when setting the target EL, so it does not have a further
524 hcr = hcr_el2 & HCR_IMO;
528 g_assert_not_reached();
531 if ((scr || hcr) && !secure) {
538 * The PSTATE bits only mask the interrupt if we have not overriden the
541 return unmasked || pstate_unmasked;
544 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
546 CPUClass *cc = CPU_GET_CLASS(cs);
547 CPUARMState *env = cs->env_ptr;
548 uint32_t cur_el = arm_current_el(env);
549 bool secure = arm_is_secure(env);
550 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
554 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
556 if (interrupt_request & CPU_INTERRUPT_FIQ) {
558 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
559 if (arm_excp_unmasked(cs, excp_idx, target_el,
560 cur_el, secure, hcr_el2)) {
564 if (interrupt_request & CPU_INTERRUPT_HARD) {
566 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
567 if (arm_excp_unmasked(cs, excp_idx, target_el,
568 cur_el, secure, hcr_el2)) {
572 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
573 excp_idx = EXCP_VIRQ;
575 if (arm_excp_unmasked(cs, excp_idx, target_el,
576 cur_el, secure, hcr_el2)) {
580 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
581 excp_idx = EXCP_VFIQ;
583 if (arm_excp_unmasked(cs, excp_idx, target_el,
584 cur_el, secure, hcr_el2)) {
591 cs->exception_index = excp_idx;
592 env->exception.target_el = target_el;
593 cc->do_interrupt(cs);
597 void arm_cpu_update_virq(ARMCPU *cpu)
600 * Update the interrupt level for VIRQ, which is the logical OR of
601 * the HCR_EL2.VI bit and the input line level from the GIC.
603 CPUARMState *env = &cpu->env;
604 CPUState *cs = CPU(cpu);
606 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
607 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
609 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
611 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
613 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
618 void arm_cpu_update_vfiq(ARMCPU *cpu)
621 * Update the interrupt level for VFIQ, which is the logical OR of
622 * the HCR_EL2.VF bit and the input line level from the GIC.
624 CPUARMState *env = &cpu->env;
625 CPUState *cs = CPU(cpu);
627 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
628 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
630 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
632 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
634 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
639 #ifndef CONFIG_USER_ONLY
640 static void arm_cpu_set_irq(void *opaque, int irq, int level)
642 ARMCPU *cpu = opaque;
643 CPUARMState *env = &cpu->env;
644 CPUState *cs = CPU(cpu);
645 static const int mask[] = {
646 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
647 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
648 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
649 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
653 env->irq_line_state |= mask[irq];
655 env->irq_line_state &= ~mask[irq];
660 assert(arm_feature(env, ARM_FEATURE_EL2));
661 arm_cpu_update_virq(cpu);
664 assert(arm_feature(env, ARM_FEATURE_EL2));
665 arm_cpu_update_vfiq(cpu);
670 cpu_interrupt(cs, mask[irq]);
672 cpu_reset_interrupt(cs, mask[irq]);
676 g_assert_not_reached();
680 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
683 ARMCPU *cpu = opaque;
684 CPUARMState *env = &cpu->env;
685 CPUState *cs = CPU(cpu);
686 uint32_t linestate_bit;
691 irq_id = KVM_ARM_IRQ_CPU_IRQ;
692 linestate_bit = CPU_INTERRUPT_HARD;
695 irq_id = KVM_ARM_IRQ_CPU_FIQ;
696 linestate_bit = CPU_INTERRUPT_FIQ;
699 g_assert_not_reached();
703 env->irq_line_state |= linestate_bit;
705 env->irq_line_state &= ~linestate_bit;
707 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
711 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
713 ARMCPU *cpu = ARM_CPU(cs);
714 CPUARMState *env = &cpu->env;
716 cpu_synchronize_state(cs);
717 return arm_cpu_data_is_big_endian(env);
723 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
725 return print_insn_arm(pc | 1, info);
728 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
730 ARMCPU *ac = ARM_CPU(cpu);
731 CPUARMState *env = &ac->env;
735 /* We might not be compiled with the A64 disassembler
736 * because it needs a C++ compiler. Leave print_insn
737 * unset in this case to use the caller default behaviour.
739 #if defined(CONFIG_ARM_A64_DIS)
740 info->print_insn = print_insn_arm_a64;
742 info->cap_arch = CS_ARCH_ARM64;
743 info->cap_insn_unit = 4;
744 info->cap_insn_split = 4;
748 info->print_insn = print_insn_thumb1;
749 info->cap_insn_unit = 2;
750 info->cap_insn_split = 4;
751 cap_mode = CS_MODE_THUMB;
753 info->print_insn = print_insn_arm;
754 info->cap_insn_unit = 4;
755 info->cap_insn_split = 4;
756 cap_mode = CS_MODE_ARM;
758 if (arm_feature(env, ARM_FEATURE_V8)) {
759 cap_mode |= CS_MODE_V8;
761 if (arm_feature(env, ARM_FEATURE_M)) {
762 cap_mode |= CS_MODE_MCLASS;
764 info->cap_arch = CS_ARCH_ARM;
765 info->cap_mode = cap_mode;
768 sctlr_b = arm_sctlr_b(env);
769 if (bswap_code(sctlr_b)) {
770 #ifdef TARGET_WORDS_BIGENDIAN
771 info->endian = BFD_ENDIAN_LITTLE;
773 info->endian = BFD_ENDIAN_BIG;
776 info->flags &= ~INSN_ARM_BE32;
777 #ifndef CONFIG_USER_ONLY
779 info->flags |= INSN_ARM_BE32;
784 #ifdef TARGET_AARCH64
786 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
788 ARMCPU *cpu = ARM_CPU(cs);
789 CPUARMState *env = &cpu->env;
790 uint32_t psr = pstate_read(env);
792 int el = arm_current_el(env);
793 const char *ns_status;
795 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
796 for (i = 0; i < 32; i++) {
798 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
800 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
801 (i + 2) % 3 ? " " : "\n");
805 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
806 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
810 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
812 psr & PSTATE_N ? 'N' : '-',
813 psr & PSTATE_Z ? 'Z' : '-',
814 psr & PSTATE_C ? 'C' : '-',
815 psr & PSTATE_V ? 'V' : '-',
818 psr & PSTATE_SP ? 'h' : 't');
820 if (cpu_isar_feature(aa64_bti, cpu)) {
821 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
823 if (!(flags & CPU_DUMP_FPU)) {
824 qemu_fprintf(f, "\n");
827 if (fp_exception_el(env, el) != 0) {
828 qemu_fprintf(f, " FPU disabled\n");
831 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
832 vfp_get_fpcr(env), vfp_get_fpsr(env));
834 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
835 int j, zcr_len = sve_zcr_len_for_el(env, el);
837 for (i = 0; i <= FFR_PRED_NUM; i++) {
839 if (i == FFR_PRED_NUM) {
840 qemu_fprintf(f, "FFR=");
841 /* It's last, so end the line. */
844 qemu_fprintf(f, "P%02d=", i);
857 /* More than one quadword per predicate. */
862 for (j = zcr_len / 4; j >= 0; j--) {
864 if (j * 4 + 4 <= zcr_len + 1) {
867 digits = (zcr_len % 4 + 1) * 4;
869 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
870 env->vfp.pregs[i].p[j],
871 j ? ":" : eol ? "\n" : " ");
875 for (i = 0; i < 32; i++) {
877 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
878 i, env->vfp.zregs[i].d[1],
879 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
880 } else if (zcr_len == 1) {
881 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
882 ":%016" PRIx64 ":%016" PRIx64 "\n",
883 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
884 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
886 for (j = zcr_len; j >= 0; j--) {
887 bool odd = (zcr_len - j) % 2 != 0;
889 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
892 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
894 qemu_fprintf(f, " [%x]=", j);
897 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
898 env->vfp.zregs[i].d[j * 2 + 1],
899 env->vfp.zregs[i].d[j * 2],
900 odd || j == 0 ? "\n" : ":");
905 for (i = 0; i < 32; i++) {
906 uint64_t *q = aa64_vfp_qreg(env, i);
907 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
908 i, q[1], q[0], (i & 1 ? "\n" : " "));
915 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
917 g_assert_not_reached();
922 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
924 ARMCPU *cpu = ARM_CPU(cs);
925 CPUARMState *env = &cpu->env;
929 aarch64_cpu_dump_state(cs, f, flags);
933 for (i = 0; i < 16; i++) {
934 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
936 qemu_fprintf(f, "\n");
938 qemu_fprintf(f, " ");
942 if (arm_feature(env, ARM_FEATURE_M)) {
943 uint32_t xpsr = xpsr_read(env);
945 const char *ns_status = "";
947 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
948 ns_status = env->v7m.secure ? "S " : "NS ";
951 if (xpsr & XPSR_EXCP) {
954 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
955 mode = "unpriv-thread";
957 mode = "priv-thread";
961 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
963 xpsr & XPSR_N ? 'N' : '-',
964 xpsr & XPSR_Z ? 'Z' : '-',
965 xpsr & XPSR_C ? 'C' : '-',
966 xpsr & XPSR_V ? 'V' : '-',
967 xpsr & XPSR_T ? 'T' : 'A',
971 uint32_t psr = cpsr_read(env);
972 const char *ns_status = "";
974 if (arm_feature(env, ARM_FEATURE_EL3) &&
975 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
976 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
979 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
981 psr & CPSR_N ? 'N' : '-',
982 psr & CPSR_Z ? 'Z' : '-',
983 psr & CPSR_C ? 'C' : '-',
984 psr & CPSR_V ? 'V' : '-',
985 psr & CPSR_T ? 'T' : 'A',
987 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
990 if (flags & CPU_DUMP_FPU) {
992 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
994 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
997 for (i = 0; i < numvfpregs; i++) {
998 uint64_t v = *aa32_vfp_dreg(env, i);
999 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1001 i * 2 + 1, (uint32_t)(v >> 32),
1004 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1008 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1010 uint32_t Aff1 = idx / clustersz;
1011 uint32_t Aff0 = idx % clustersz;
1012 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1015 static void cpreg_hashtable_data_destroy(gpointer data)
1018 * Destroy function for cpu->cp_regs hashtable data entries.
1019 * We must free the name string because it was g_strdup()ed in
1020 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1021 * from r->name because we know we definitely allocated it.
1023 ARMCPRegInfo *r = data;
1025 g_free((void *)r->name);
1029 static void arm_cpu_initfn(Object *obj)
1031 ARMCPU *cpu = ARM_CPU(obj);
1033 cpu_set_cpustate_pointers(cpu);
1034 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
1035 g_free, cpreg_hashtable_data_destroy);
1037 QLIST_INIT(&cpu->pre_el_change_hooks);
1038 QLIST_INIT(&cpu->el_change_hooks);
1040 #ifndef CONFIG_USER_ONLY
1041 /* Our inbound IRQ and FIQ lines */
1042 if (kvm_enabled()) {
1043 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1044 * the same interface as non-KVM CPUs.
1046 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
1048 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
1051 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1052 ARRAY_SIZE(cpu->gt_timer_outputs));
1054 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1055 "gicv3-maintenance-interrupt", 1);
1056 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1057 "pmu-interrupt", 1);
1060 /* DTB consumers generally don't in fact care what the 'compatible'
1061 * string is, so always provide some string and trust that a hypothetical
1062 * picky DTB consumer will also provide a helpful error message.
1064 cpu->dtb_compatible = "qemu,unknown";
1065 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
1066 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1068 if (tcg_enabled()) {
1069 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
1073 static Property arm_cpu_gt_cntfrq_property =
1074 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1075 NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1077 static Property arm_cpu_reset_cbar_property =
1078 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1080 static Property arm_cpu_reset_hivecs_property =
1081 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1083 static Property arm_cpu_rvbar_property =
1084 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
1086 #ifndef CONFIG_USER_ONLY
1087 static Property arm_cpu_has_el2_property =
1088 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1090 static Property arm_cpu_has_el3_property =
1091 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1094 static Property arm_cpu_cfgend_property =
1095 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1097 static Property arm_cpu_has_vfp_property =
1098 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1100 static Property arm_cpu_has_neon_property =
1101 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1103 static Property arm_cpu_has_dsp_property =
1104 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1106 static Property arm_cpu_has_mpu_property =
1107 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1109 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1110 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1111 * the right value for that particular CPU type, and we don't want
1112 * to override that with an incorrect constant value.
1114 static Property arm_cpu_pmsav7_dregion_property =
1115 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1117 qdev_prop_uint32, uint32_t);
1119 static bool arm_get_pmu(Object *obj, Error **errp)
1121 ARMCPU *cpu = ARM_CPU(obj);
1123 return cpu->has_pmu;
1126 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1128 ARMCPU *cpu = ARM_CPU(obj);
1131 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1132 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1135 set_feature(&cpu->env, ARM_FEATURE_PMU);
1137 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1139 cpu->has_pmu = value;
1142 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1145 * The exact approach to calculating guest ticks is:
1147 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1148 * NANOSECONDS_PER_SECOND);
1150 * We don't do that. Rather we intentionally use integer division
1151 * truncation below and in the caller for the conversion of host monotonic
1152 * time to guest ticks to provide the exact inverse for the semantics of
1153 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1154 * it loses precision when representing frequencies where
1155 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1156 * provide an exact inverse leads to scheduling timers with negative
1157 * periods, which in turn leads to sticky behaviour in the guest.
1159 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1160 * cannot become zero.
1162 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1163 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1166 void arm_cpu_post_init(Object *obj)
1168 ARMCPU *cpu = ARM_CPU(obj);
1170 /* M profile implies PMSA. We have to do this here rather than
1171 * in realize with the other feature-implication checks because
1172 * we look at the PMSA bit to see if we should add some properties.
1174 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1175 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1178 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1179 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1180 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1183 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1184 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1187 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1188 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
1191 #ifndef CONFIG_USER_ONLY
1192 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1193 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1194 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1196 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1198 object_property_add_link(obj, "secure-memory",
1200 (Object **)&cpu->secure_memory,
1201 qdev_prop_allow_set_link_before_realize,
1202 OBJ_PROP_LINK_STRONG);
1205 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1206 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1210 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1211 cpu->has_pmu = true;
1212 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1216 * Allow user to turn off VFP and Neon support, but only for TCG --
1217 * KVM does not currently allow us to lie to the guest about its
1218 * ID/feature registers, so the guest always sees what the host has.
1220 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
1221 ? cpu_isar_feature(aa64_fp_simd, cpu)
1222 : cpu_isar_feature(aa32_vfp, cpu)) {
1223 cpu->has_vfp = true;
1224 if (!kvm_enabled()) {
1225 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1229 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1230 cpu->has_neon = true;
1231 if (!kvm_enabled()) {
1232 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1236 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1237 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1238 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1241 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1242 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1243 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1244 qdev_property_add_static(DEVICE(obj),
1245 &arm_cpu_pmsav7_dregion_property);
1249 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1250 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1251 qdev_prop_allow_set_link_before_realize,
1252 OBJ_PROP_LINK_STRONG);
1254 * M profile: initial value of the Secure VTOR. We can't just use
1255 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1256 * the property to be set after realize.
1258 object_property_add_uint32_ptr(obj, "init-svtor",
1260 OBJ_PROP_FLAG_READWRITE);
1263 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1265 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1266 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1269 if (kvm_enabled()) {
1270 kvm_arm_add_vcpu_properties(obj);
1273 #ifndef CONFIG_USER_ONLY
1274 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1275 cpu_isar_feature(aa64_mte, cpu)) {
1276 object_property_add_link(obj, "tag-memory",
1278 (Object **)&cpu->tag_memory,
1279 qdev_prop_allow_set_link_before_realize,
1280 OBJ_PROP_LINK_STRONG);
1282 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1283 object_property_add_link(obj, "secure-tag-memory",
1285 (Object **)&cpu->secure_tag_memory,
1286 qdev_prop_allow_set_link_before_realize,
1287 OBJ_PROP_LINK_STRONG);
1293 static void arm_cpu_finalizefn(Object *obj)
1295 ARMCPU *cpu = ARM_CPU(obj);
1296 ARMELChangeHook *hook, *next;
1298 g_hash_table_destroy(cpu->cp_regs);
1300 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1301 QLIST_REMOVE(hook, node);
1304 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1305 QLIST_REMOVE(hook, node);
1308 #ifndef CONFIG_USER_ONLY
1309 if (cpu->pmu_timer) {
1310 timer_free(cpu->pmu_timer);
1315 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1317 Error *local_err = NULL;
1319 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1320 arm_cpu_sve_finalize(cpu, &local_err);
1321 if (local_err != NULL) {
1322 error_propagate(errp, local_err);
1327 * KVM does not support modifications to this feature.
1328 * We have not registered the cpu properties when KVM
1329 * is in use, so the user will not be able to set them.
1331 if (!kvm_enabled()) {
1332 arm_cpu_pauth_finalize(cpu, &local_err);
1333 if (local_err != NULL) {
1334 error_propagate(errp, local_err);
1340 if (kvm_enabled()) {
1341 kvm_arm_steal_time_finalize(cpu, &local_err);
1342 if (local_err != NULL) {
1343 error_propagate(errp, local_err);
1349 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1351 CPUState *cs = CPU(dev);
1352 ARMCPU *cpu = ARM_CPU(dev);
1353 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1354 CPUARMState *env = &cpu->env;
1356 Error *local_err = NULL;
1357 bool no_aa32 = false;
1359 /* If we needed to query the host kernel for the CPU features
1360 * then it's possible that might have failed in the initfn, but
1361 * this is the first point where we can report it.
1363 if (cpu->host_cpu_probe_failed) {
1364 if (!kvm_enabled()) {
1365 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1367 error_setg(errp, "Failed to retrieve host CPU features");
1372 #ifndef CONFIG_USER_ONLY
1373 /* The NVIC and M-profile CPU are two halves of a single piece of
1374 * hardware; trying to use one without the other is a command line
1375 * error and will result in segfaults if not caught here.
1377 if (arm_feature(env, ARM_FEATURE_M)) {
1379 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1384 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1392 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1393 if (!cpu->gt_cntfrq_hz) {
1394 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1398 scale = gt_cntfrq_period_ns(cpu);
1400 scale = GTIMER_SCALE;
1403 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1404 arm_gt_ptimer_cb, cpu);
1405 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1406 arm_gt_vtimer_cb, cpu);
1407 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1408 arm_gt_htimer_cb, cpu);
1409 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1410 arm_gt_stimer_cb, cpu);
1411 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1412 arm_gt_hvtimer_cb, cpu);
1416 cpu_exec_realizefn(cs, &local_err);
1417 if (local_err != NULL) {
1418 error_propagate(errp, local_err);
1422 arm_cpu_finalize_features(cpu, &local_err);
1423 if (local_err != NULL) {
1424 error_propagate(errp, local_err);
1428 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1429 cpu->has_vfp != cpu->has_neon) {
1431 * This is an architectural requirement for AArch64; AArch32 is
1432 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1435 "AArch64 CPUs must have both VFP and Neon or neither");
1439 if (!cpu->has_vfp) {
1443 t = cpu->isar.id_aa64isar1;
1444 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1445 cpu->isar.id_aa64isar1 = t;
1447 t = cpu->isar.id_aa64pfr0;
1448 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1449 cpu->isar.id_aa64pfr0 = t;
1451 u = cpu->isar.id_isar6;
1452 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1453 cpu->isar.id_isar6 = u;
1455 u = cpu->isar.mvfr0;
1456 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1457 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1458 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1459 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1460 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1461 if (!arm_feature(env, ARM_FEATURE_M)) {
1462 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1463 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1465 cpu->isar.mvfr0 = u;
1467 u = cpu->isar.mvfr1;
1468 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1469 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1470 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1471 if (arm_feature(env, ARM_FEATURE_M)) {
1472 u = FIELD_DP32(u, MVFR1, FP16, 0);
1474 cpu->isar.mvfr1 = u;
1476 u = cpu->isar.mvfr2;
1477 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1478 cpu->isar.mvfr2 = u;
1481 if (!cpu->has_neon) {
1485 unset_feature(env, ARM_FEATURE_NEON);
1487 t = cpu->isar.id_aa64isar0;
1488 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1489 cpu->isar.id_aa64isar0 = t;
1491 t = cpu->isar.id_aa64isar1;
1492 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1493 cpu->isar.id_aa64isar1 = t;
1495 t = cpu->isar.id_aa64pfr0;
1496 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1497 cpu->isar.id_aa64pfr0 = t;
1499 u = cpu->isar.id_isar5;
1500 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1501 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1502 cpu->isar.id_isar5 = u;
1504 u = cpu->isar.id_isar6;
1505 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1506 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1507 cpu->isar.id_isar6 = u;
1509 if (!arm_feature(env, ARM_FEATURE_M)) {
1510 u = cpu->isar.mvfr1;
1511 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1512 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1513 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1514 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1515 cpu->isar.mvfr1 = u;
1517 u = cpu->isar.mvfr2;
1518 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1519 cpu->isar.mvfr2 = u;
1523 if (!cpu->has_neon && !cpu->has_vfp) {
1527 t = cpu->isar.id_aa64isar0;
1528 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1529 cpu->isar.id_aa64isar0 = t;
1531 t = cpu->isar.id_aa64isar1;
1532 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1533 cpu->isar.id_aa64isar1 = t;
1535 u = cpu->isar.mvfr0;
1536 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1537 cpu->isar.mvfr0 = u;
1539 /* Despite the name, this field covers both VFP and Neon */
1540 u = cpu->isar.mvfr1;
1541 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1542 cpu->isar.mvfr1 = u;
1545 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1548 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1550 u = cpu->isar.id_isar1;
1551 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1552 cpu->isar.id_isar1 = u;
1554 u = cpu->isar.id_isar2;
1555 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1556 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1557 cpu->isar.id_isar2 = u;
1559 u = cpu->isar.id_isar3;
1560 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1561 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1562 cpu->isar.id_isar3 = u;
1565 /* Some features automatically imply others: */
1566 if (arm_feature(env, ARM_FEATURE_V8)) {
1567 if (arm_feature(env, ARM_FEATURE_M)) {
1568 set_feature(env, ARM_FEATURE_V7);
1570 set_feature(env, ARM_FEATURE_V7VE);
1575 * There exist AArch64 cpus without AArch32 support. When KVM
1576 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1577 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1578 * As a general principle, we also do not make ID register
1579 * consistency checks anywhere unless using TCG, because only
1580 * for TCG would a consistency-check failure be a QEMU bug.
1582 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1583 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1586 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1587 /* v7 Virtualization Extensions. In real hardware this implies
1588 * EL2 and also the presence of the Security Extensions.
1589 * For QEMU, for backwards-compatibility we implement some
1590 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1591 * include the various other features that V7VE implies.
1592 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1593 * Security Extensions is ARM_FEATURE_EL3.
1595 assert(!tcg_enabled() || no_aa32 ||
1596 cpu_isar_feature(aa32_arm_div, cpu));
1597 set_feature(env, ARM_FEATURE_LPAE);
1598 set_feature(env, ARM_FEATURE_V7);
1600 if (arm_feature(env, ARM_FEATURE_V7)) {
1601 set_feature(env, ARM_FEATURE_VAPA);
1602 set_feature(env, ARM_FEATURE_THUMB2);
1603 set_feature(env, ARM_FEATURE_MPIDR);
1604 if (!arm_feature(env, ARM_FEATURE_M)) {
1605 set_feature(env, ARM_FEATURE_V6K);
1607 set_feature(env, ARM_FEATURE_V6);
1610 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1611 * non-EL3 configs. This is needed by some legacy boards.
1613 set_feature(env, ARM_FEATURE_VBAR);
1615 if (arm_feature(env, ARM_FEATURE_V6K)) {
1616 set_feature(env, ARM_FEATURE_V6);
1617 set_feature(env, ARM_FEATURE_MVFR);
1619 if (arm_feature(env, ARM_FEATURE_V6)) {
1620 set_feature(env, ARM_FEATURE_V5);
1621 if (!arm_feature(env, ARM_FEATURE_M)) {
1622 assert(!tcg_enabled() || no_aa32 ||
1623 cpu_isar_feature(aa32_jazelle, cpu));
1624 set_feature(env, ARM_FEATURE_AUXCR);
1627 if (arm_feature(env, ARM_FEATURE_V5)) {
1628 set_feature(env, ARM_FEATURE_V4T);
1630 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1631 set_feature(env, ARM_FEATURE_V7MP);
1633 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1634 set_feature(env, ARM_FEATURE_CBAR);
1636 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1637 !arm_feature(env, ARM_FEATURE_M)) {
1638 set_feature(env, ARM_FEATURE_THUMB_DSP);
1642 * We rely on no XScale CPU having VFP so we can use the same bits in the
1643 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1645 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
1646 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
1647 !arm_feature(env, ARM_FEATURE_XSCALE));
1649 if (arm_feature(env, ARM_FEATURE_V7) &&
1650 !arm_feature(env, ARM_FEATURE_M) &&
1651 !arm_feature(env, ARM_FEATURE_PMSA)) {
1652 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1657 /* For CPUs which might have tiny 1K pages, or which have an
1658 * MPU and might have small region sizes, stick with 1K pages.
1662 if (!set_preferred_target_page_bits(pagebits)) {
1663 /* This can only ever happen for hotplugging a CPU, or if
1664 * the board code incorrectly creates a CPU which it has
1665 * promised via minimum_page_size that it will not.
1667 error_setg(errp, "This CPU requires a smaller page size than the "
1672 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1673 * We don't support setting cluster ID ([16..23]) (known as Aff2
1674 * in later ARM ARM versions), or any of the higher affinity level fields,
1675 * so these bits always RAZ.
1677 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1678 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1679 ARM_DEFAULT_CPUS_PER_CLUSTER);
1682 if (cpu->reset_hivecs) {
1683 cpu->reset_sctlr |= (1 << 13);
1687 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1688 cpu->reset_sctlr |= SCTLR_EE;
1690 cpu->reset_sctlr |= SCTLR_B;
1694 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
1695 /* If the has_el3 CPU property is disabled then we need to disable the
1698 unset_feature(env, ARM_FEATURE_EL3);
1700 /* Disable the security extension feature bits in the processor feature
1701 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1703 cpu->isar.id_pfr1 &= ~0xf0;
1704 cpu->isar.id_aa64pfr0 &= ~0xf000;
1707 if (!cpu->has_el2) {
1708 unset_feature(env, ARM_FEATURE_EL2);
1711 if (!cpu->has_pmu) {
1712 unset_feature(env, ARM_FEATURE_PMU);
1714 if (arm_feature(env, ARM_FEATURE_PMU)) {
1717 if (!kvm_enabled()) {
1718 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1719 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1722 #ifndef CONFIG_USER_ONLY
1723 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1727 cpu->isar.id_aa64dfr0 =
1728 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
1729 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
1734 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1735 /* Disable the hypervisor feature bits in the processor feature
1736 * registers if we don't have EL2. These are id_pfr1[15:12] and
1737 * id_aa64pfr0_el1[11:8].
1739 cpu->isar.id_aa64pfr0 &= ~0xf00;
1740 cpu->isar.id_pfr1 &= ~0xf000;
1743 #ifndef CONFIG_USER_ONLY
1744 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
1746 * Disable the MTE feature bits if we do not have tag-memory
1747 * provided by the machine.
1749 cpu->isar.id_aa64pfr1 =
1750 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
1754 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1755 * to false or by setting pmsav7-dregion to 0.
1757 if (!cpu->has_mpu) {
1758 cpu->pmsav7_dregion = 0;
1760 if (cpu->pmsav7_dregion == 0) {
1761 cpu->has_mpu = false;
1764 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1765 arm_feature(env, ARM_FEATURE_V7)) {
1766 uint32_t nr = cpu->pmsav7_dregion;
1769 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1774 if (arm_feature(env, ARM_FEATURE_V8)) {
1776 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1777 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1778 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1779 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1780 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1783 env->pmsav7.drbar = g_new0(uint32_t, nr);
1784 env->pmsav7.drsr = g_new0(uint32_t, nr);
1785 env->pmsav7.dracr = g_new0(uint32_t, nr);
1790 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1791 uint32_t nr = cpu->sau_sregion;
1794 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1799 env->sau.rbar = g_new0(uint32_t, nr);
1800 env->sau.rlar = g_new0(uint32_t, nr);
1804 if (arm_feature(env, ARM_FEATURE_EL3)) {
1805 set_feature(env, ARM_FEATURE_VBAR);
1808 register_cp_regs_for_features(cpu);
1809 arm_cpu_register_gdb_regs_for_features(cpu);
1811 init_cpreg_list(cpu);
1813 #ifndef CONFIG_USER_ONLY
1814 MachineState *ms = MACHINE(qdev_get_machine());
1815 unsigned int smp_cpus = ms->smp.cpus;
1816 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
1819 * We must set cs->num_ases to the final value before
1820 * the first call to cpu_address_space_init.
1822 if (cpu->tag_memory != NULL) {
1823 cs->num_ases = 3 + has_secure;
1825 cs->num_ases = 1 + has_secure;
1829 if (!cpu->secure_memory) {
1830 cpu->secure_memory = cs->memory;
1832 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1833 cpu->secure_memory);
1836 if (cpu->tag_memory != NULL) {
1837 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
1840 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
1841 cpu->secure_tag_memory);
1845 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1847 /* No core_count specified, default to smp_cpus. */
1848 if (cpu->core_count == -1) {
1849 cpu->core_count = smp_cpus;
1853 if (tcg_enabled()) {
1854 int dcz_blocklen = 4 << cpu->dcz_blocksize;
1857 * We only support DCZ blocklen that fits on one page.
1859 * Architectually this is always true. However TARGET_PAGE_SIZE
1860 * is variable and, for compatibility with -machine virt-2.7,
1861 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1862 * But even then, while the largest architectural DCZ blocklen
1863 * is 2KiB, no cpu actually uses such a large blocklen.
1865 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
1868 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1869 * both nibbles of each byte storing tag data may be written at once.
1870 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1872 if (cpu_isar_feature(aa64_mte, cpu)) {
1873 assert(dcz_blocklen >= 2 * TAG_GRANULE);
1880 acc->parent_realize(dev, errp);
1883 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1888 const char *cpunamestr;
1890 cpuname = g_strsplit(cpu_model, ",", 1);
1891 cpunamestr = cpuname[0];
1892 #ifdef CONFIG_USER_ONLY
1893 /* For backwards compatibility usermode emulation allows "-cpu any",
1894 * which has the same semantics as "-cpu max".
1896 if (!strcmp(cpunamestr, "any")) {
1900 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1901 oc = object_class_by_name(typename);
1902 g_strfreev(cpuname);
1904 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1905 object_class_is_abstract(oc)) {
1911 /* CPU models. These are not needed for the AArch64 linux-user build. */
1912 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1914 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1915 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1916 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1917 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1918 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1922 static void cortex_a8_initfn(Object *obj)
1924 ARMCPU *cpu = ARM_CPU(obj);
1926 cpu->dtb_compatible = "arm,cortex-a8";
1927 set_feature(&cpu->env, ARM_FEATURE_V7);
1928 set_feature(&cpu->env, ARM_FEATURE_NEON);
1929 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1930 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1931 set_feature(&cpu->env, ARM_FEATURE_EL3);
1932 cpu->midr = 0x410fc080;
1933 cpu->reset_fpsid = 0x410330c0;
1934 cpu->isar.mvfr0 = 0x11110222;
1935 cpu->isar.mvfr1 = 0x00011111;
1936 cpu->ctr = 0x82048004;
1937 cpu->reset_sctlr = 0x00c50078;
1938 cpu->isar.id_pfr0 = 0x1031;
1939 cpu->isar.id_pfr1 = 0x11;
1940 cpu->isar.id_dfr0 = 0x400;
1942 cpu->isar.id_mmfr0 = 0x31100003;
1943 cpu->isar.id_mmfr1 = 0x20000000;
1944 cpu->isar.id_mmfr2 = 0x01202000;
1945 cpu->isar.id_mmfr3 = 0x11;
1946 cpu->isar.id_isar0 = 0x00101111;
1947 cpu->isar.id_isar1 = 0x12112111;
1948 cpu->isar.id_isar2 = 0x21232031;
1949 cpu->isar.id_isar3 = 0x11112131;
1950 cpu->isar.id_isar4 = 0x00111142;
1951 cpu->isar.dbgdidr = 0x15141000;
1952 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1953 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1954 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1955 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1956 cpu->reset_auxcr = 2;
1957 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1960 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1961 /* power_control should be set to maximum latency. Again,
1962 * default to 0 and set by private hook
1964 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1965 .access = PL1_RW, .resetvalue = 0,
1966 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1967 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1968 .access = PL1_RW, .resetvalue = 0,
1969 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1970 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1971 .access = PL1_RW, .resetvalue = 0,
1972 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1973 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1974 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1975 /* TLB lockdown control */
1976 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1977 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1978 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1979 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1980 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1981 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1982 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1983 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1984 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1985 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1989 static void cortex_a9_initfn(Object *obj)
1991 ARMCPU *cpu = ARM_CPU(obj);
1993 cpu->dtb_compatible = "arm,cortex-a9";
1994 set_feature(&cpu->env, ARM_FEATURE_V7);
1995 set_feature(&cpu->env, ARM_FEATURE_NEON);
1996 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1997 set_feature(&cpu->env, ARM_FEATURE_EL3);
1998 /* Note that A9 supports the MP extensions even for
1999 * A9UP and single-core A9MP (which are both different
2000 * and valid configurations; we don't model A9UP).
2002 set_feature(&cpu->env, ARM_FEATURE_V7MP);
2003 set_feature(&cpu->env, ARM_FEATURE_CBAR);
2004 cpu->midr = 0x410fc090;
2005 cpu->reset_fpsid = 0x41033090;
2006 cpu->isar.mvfr0 = 0x11110222;
2007 cpu->isar.mvfr1 = 0x01111111;
2008 cpu->ctr = 0x80038003;
2009 cpu->reset_sctlr = 0x00c50078;
2010 cpu->isar.id_pfr0 = 0x1031;
2011 cpu->isar.id_pfr1 = 0x11;
2012 cpu->isar.id_dfr0 = 0x000;
2014 cpu->isar.id_mmfr0 = 0x00100103;
2015 cpu->isar.id_mmfr1 = 0x20000000;
2016 cpu->isar.id_mmfr2 = 0x01230000;
2017 cpu->isar.id_mmfr3 = 0x00002111;
2018 cpu->isar.id_isar0 = 0x00101111;
2019 cpu->isar.id_isar1 = 0x13112111;
2020 cpu->isar.id_isar2 = 0x21232041;
2021 cpu->isar.id_isar3 = 0x11112131;
2022 cpu->isar.id_isar4 = 0x00111142;
2023 cpu->isar.dbgdidr = 0x35141000;
2024 cpu->clidr = (1 << 27) | (1 << 24) | 3;
2025 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2026 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2027 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2030 #ifndef CONFIG_USER_ONLY
2031 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2033 MachineState *ms = MACHINE(qdev_get_machine());
2035 /* Linux wants the number of processors from here.
2036 * Might as well set the interrupt-controller bit too.
2038 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
2042 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2043 #ifndef CONFIG_USER_ONLY
2044 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2045 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2046 .writefn = arm_cp_write_ignore, },
2048 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2049 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2053 static void cortex_a7_initfn(Object *obj)
2055 ARMCPU *cpu = ARM_CPU(obj);
2057 cpu->dtb_compatible = "arm,cortex-a7";
2058 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2059 set_feature(&cpu->env, ARM_FEATURE_NEON);
2060 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2061 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2062 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2063 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2064 set_feature(&cpu->env, ARM_FEATURE_EL2);
2065 set_feature(&cpu->env, ARM_FEATURE_EL3);
2066 set_feature(&cpu->env, ARM_FEATURE_PMU);
2067 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2068 cpu->midr = 0x410fc075;
2069 cpu->reset_fpsid = 0x41023075;
2070 cpu->isar.mvfr0 = 0x10110222;
2071 cpu->isar.mvfr1 = 0x11111111;
2072 cpu->ctr = 0x84448003;
2073 cpu->reset_sctlr = 0x00c50078;
2074 cpu->isar.id_pfr0 = 0x00001131;
2075 cpu->isar.id_pfr1 = 0x00011011;
2076 cpu->isar.id_dfr0 = 0x02010555;
2077 cpu->id_afr0 = 0x00000000;
2078 cpu->isar.id_mmfr0 = 0x10101105;
2079 cpu->isar.id_mmfr1 = 0x40000000;
2080 cpu->isar.id_mmfr2 = 0x01240000;
2081 cpu->isar.id_mmfr3 = 0x02102211;
2082 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2083 * table 4-41 gives 0x02101110, which includes the arm div insns.
2085 cpu->isar.id_isar0 = 0x02101110;
2086 cpu->isar.id_isar1 = 0x13112111;
2087 cpu->isar.id_isar2 = 0x21232041;
2088 cpu->isar.id_isar3 = 0x11112131;
2089 cpu->isar.id_isar4 = 0x10011142;
2090 cpu->isar.dbgdidr = 0x3515f005;
2091 cpu->clidr = 0x0a200023;
2092 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2093 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2094 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2095 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2098 static void cortex_a15_initfn(Object *obj)
2100 ARMCPU *cpu = ARM_CPU(obj);
2102 cpu->dtb_compatible = "arm,cortex-a15";
2103 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2104 set_feature(&cpu->env, ARM_FEATURE_NEON);
2105 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2106 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2107 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2108 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2109 set_feature(&cpu->env, ARM_FEATURE_EL2);
2110 set_feature(&cpu->env, ARM_FEATURE_EL3);
2111 set_feature(&cpu->env, ARM_FEATURE_PMU);
2112 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
2113 cpu->midr = 0x412fc0f1;
2114 cpu->reset_fpsid = 0x410430f0;
2115 cpu->isar.mvfr0 = 0x10110222;
2116 cpu->isar.mvfr1 = 0x11111111;
2117 cpu->ctr = 0x8444c004;
2118 cpu->reset_sctlr = 0x00c50078;
2119 cpu->isar.id_pfr0 = 0x00001131;
2120 cpu->isar.id_pfr1 = 0x00011011;
2121 cpu->isar.id_dfr0 = 0x02010555;
2122 cpu->id_afr0 = 0x00000000;
2123 cpu->isar.id_mmfr0 = 0x10201105;
2124 cpu->isar.id_mmfr1 = 0x20000000;
2125 cpu->isar.id_mmfr2 = 0x01240000;
2126 cpu->isar.id_mmfr3 = 0x02102211;
2127 cpu->isar.id_isar0 = 0x02101110;
2128 cpu->isar.id_isar1 = 0x13112111;
2129 cpu->isar.id_isar2 = 0x21232041;
2130 cpu->isar.id_isar3 = 0x11112131;
2131 cpu->isar.id_isar4 = 0x10011142;
2132 cpu->isar.dbgdidr = 0x3515f021;
2133 cpu->clidr = 0x0a200023;
2134 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2135 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2136 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2137 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2140 #ifndef TARGET_AARCH64
2142 * -cpu max: a CPU with as many features enabled as our emulation supports.
2143 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2144 * this only needs to handle 32 bits, and need not care about KVM.
2146 static void arm_max_initfn(Object *obj)
2148 ARMCPU *cpu = ARM_CPU(obj);
2150 cortex_a15_initfn(obj);
2152 /* old-style VFP short-vector support */
2153 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2155 #ifdef CONFIG_USER_ONLY
2157 * We don't set these in system emulation mode for the moment,
2158 * since we don't correctly set (all of) the ID registers to
2161 set_feature(&cpu->env, ARM_FEATURE_V8);
2165 t = cpu->isar.id_isar5;
2166 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2167 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2168 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2169 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2170 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2171 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2172 cpu->isar.id_isar5 = t;
2174 t = cpu->isar.id_isar6;
2175 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2176 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2177 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2178 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2179 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2180 cpu->isar.id_isar6 = t;
2182 t = cpu->isar.mvfr1;
2183 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
2184 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
2185 cpu->isar.mvfr1 = t;
2187 t = cpu->isar.mvfr2;
2188 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2189 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2190 cpu->isar.mvfr2 = t;
2192 t = cpu->isar.id_mmfr3;
2193 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
2194 cpu->isar.id_mmfr3 = t;
2196 t = cpu->isar.id_mmfr4;
2197 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2198 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
2199 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
2200 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
2201 cpu->isar.id_mmfr4 = t;
2207 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2209 static const ARMCPUInfo arm_cpus[] = {
2210 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2211 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
2212 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2213 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2214 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2215 #ifndef TARGET_AARCH64
2216 { .name = "max", .initfn = arm_max_initfn },
2218 #ifdef CONFIG_USER_ONLY
2219 { .name = "any", .initfn = arm_max_initfn },
2224 static Property arm_cpu_properties[] = {
2225 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2226 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2227 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2228 mp_affinity, ARM64_AFFINITY_INVALID),
2229 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2230 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2231 DEFINE_PROP_END_OF_LIST()
2234 static gchar *arm_gdb_arch_name(CPUState *cs)
2236 ARMCPU *cpu = ARM_CPU(cs);
2237 CPUARMState *env = &cpu->env;
2239 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2240 return g_strdup("iwmmxt");
2242 return g_strdup("arm");
2245 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2247 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2248 CPUClass *cc = CPU_CLASS(acc);
2249 DeviceClass *dc = DEVICE_CLASS(oc);
2251 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2252 &acc->parent_realize);
2254 device_class_set_props(dc, arm_cpu_properties);
2255 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
2257 cc->class_by_name = arm_cpu_class_by_name;
2258 cc->has_work = arm_cpu_has_work;
2259 cc->dump_state = arm_cpu_dump_state;
2260 cc->set_pc = arm_cpu_set_pc;
2261 cc->gdb_read_register = arm_cpu_gdb_read_register;
2262 cc->gdb_write_register = arm_cpu_gdb_write_register;
2263 #ifndef CONFIG_USER_ONLY
2264 cc->do_interrupt = arm_cpu_do_interrupt;
2265 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2266 cc->asidx_from_attrs = arm_asidx_from_attrs;
2267 cc->vmsd = &vmstate_arm_cpu;
2268 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2269 cc->write_elf64_note = arm_cpu_write_elf64_note;
2270 cc->write_elf32_note = arm_cpu_write_elf32_note;
2272 cc->gdb_num_core_regs = 26;
2273 cc->gdb_core_xml_file = "arm-core.xml";
2274 cc->gdb_arch_name = arm_gdb_arch_name;
2275 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2276 cc->gdb_stop_before_watchpoint = true;
2277 cc->disas_set_info = arm_disas_set_info;
2279 cc->tcg_ops.initialize = arm_translate_init;
2280 cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
2281 cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
2282 cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
2283 cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
2284 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2285 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2286 #if !defined(CONFIG_USER_ONLY)
2287 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2288 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2289 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2294 static void arm_host_initfn(Object *obj)
2296 ARMCPU *cpu = ARM_CPU(obj);
2298 kvm_arm_set_cpu_features_from_host(cpu);
2299 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2300 aarch64_add_sve_properties(obj);
2302 arm_cpu_post_init(obj);
2305 static const TypeInfo host_arm_cpu_type_info = {
2306 .name = TYPE_ARM_HOST_CPU,
2307 .parent = TYPE_AARCH64_CPU,
2308 .instance_init = arm_host_initfn,
2313 static void arm_cpu_instance_init(Object *obj)
2315 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2317 acc->info->initfn(obj);
2318 arm_cpu_post_init(obj);
2321 static void cpu_register_class_init(ObjectClass *oc, void *data)
2323 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2328 void arm_cpu_register(const ARMCPUInfo *info)
2330 TypeInfo type_info = {
2331 .parent = TYPE_ARM_CPU,
2332 .instance_size = sizeof(ARMCPU),
2333 .instance_align = __alignof__(ARMCPU),
2334 .instance_init = arm_cpu_instance_init,
2335 .class_size = sizeof(ARMCPUClass),
2336 .class_init = info->class_init ?: cpu_register_class_init,
2337 .class_data = (void *)info,
2340 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2341 type_register(&type_info);
2342 g_free((void *)type_info.name);
2345 static const TypeInfo arm_cpu_type_info = {
2346 .name = TYPE_ARM_CPU,
2348 .instance_size = sizeof(ARMCPU),
2349 .instance_align = __alignof__(ARMCPU),
2350 .instance_init = arm_cpu_initfn,
2351 .instance_finalize = arm_cpu_finalizefn,
2353 .class_size = sizeof(ARMCPUClass),
2354 .class_init = arm_cpu_class_init,
2357 static const TypeInfo idau_interface_type_info = {
2358 .name = TYPE_IDAU_INTERFACE,
2359 .parent = TYPE_INTERFACE,
2360 .class_size = sizeof(IDAUInterfaceClass),
2363 static void arm_cpu_register_types(void)
2365 const size_t cpu_count = ARRAY_SIZE(arm_cpus);
2367 type_register_static(&arm_cpu_type_info);
2370 type_register_static(&host_arm_cpu_type_info);
2376 type_register_static(&idau_interface_type_info);
2377 for (i = 0; i < cpu_count; ++i) {
2378 arm_cpu_register(&arm_cpus[i]);
2383 type_init(arm_cpu_register_types)