2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
29 #include "tcg/tcg-gvec-desc.h"
31 #include "cpu-features.h"
33 /* register banks for CPU modes */
43 static inline bool excp_is_internal(int excp)
45 /* Return true if this exception number represents a QEMU-internal
46 * exception that will not be passed to the guest.
48 return excp == EXCP_INTERRUPT
51 || excp == EXCP_HALTED
52 || excp == EXCP_EXCEPTION_EXIT
53 || excp == EXCP_KERNEL_TRAP
54 || excp == EXCP_SEMIHOST;
57 /* Scale factor for generic timers, ie number of ns per tick.
58 * This gives a 62.5MHz timer.
60 #define GTIMER_SCALE 16
62 /* Bit definitions for the v7M CONTROL register */
63 FIELD(V7M_CONTROL, NPRIV, 0, 1)
64 FIELD(V7M_CONTROL, SPSEL, 1, 1)
65 FIELD(V7M_CONTROL, FPCA, 2, 1)
66 FIELD(V7M_CONTROL, SFPA, 3, 1)
68 /* Bit definitions for v7M exception return payload */
69 FIELD(V7M_EXCRET, ES, 0, 1)
70 FIELD(V7M_EXCRET, RES0, 1, 1)
71 FIELD(V7M_EXCRET, SPSEL, 2, 1)
72 FIELD(V7M_EXCRET, MODE, 3, 1)
73 FIELD(V7M_EXCRET, FTYPE, 4, 1)
74 FIELD(V7M_EXCRET, DCRS, 5, 1)
75 FIELD(V7M_EXCRET, S, 6, 1)
76 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
78 /* Minimum value which is a magic number for exception return */
79 #define EXC_RETURN_MIN_MAGIC 0xff000000
80 /* Minimum number which is a magic number for function or exception return
81 * when using v8M security extension
83 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
85 /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
86 FIELD(DBGWCR, E, 0, 1)
87 FIELD(DBGWCR, PAC, 1, 2)
88 FIELD(DBGWCR, LSC, 3, 2)
89 FIELD(DBGWCR, BAS, 5, 8)
90 FIELD(DBGWCR, HMC, 13, 1)
91 FIELD(DBGWCR, SSC, 14, 2)
92 FIELD(DBGWCR, LBN, 16, 4)
93 FIELD(DBGWCR, WT, 20, 1)
94 FIELD(DBGWCR, MASK, 24, 5)
95 FIELD(DBGWCR, SSCE, 29, 1)
97 /* We use a few fake FSR values for internal purposes in M profile.
98 * M profile cores don't have A/R format FSRs, but currently our
99 * get_phys_addr() code assumes A/R profile and reports failures via
100 * an A/R format FSR value. We then translate that into the proper
101 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
102 * Mostly the FSR values we use for this are those defined for v7PMSA,
103 * since we share some of that codepath. A few kinds of fault are
104 * only for M profile and have no A/R equivalent, though, so we have
105 * to pick a value from the reserved range (which we never otherwise
106 * generate) to use for these.
107 * These values will never be visible to the guest.
109 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
110 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
113 * raise_exception: Raise the specified exception.
114 * Raise a guest exception with the specified value, syndrome register
115 * and target exception level. This should be called from helper functions,
116 * and never returns because we will longjump back up to the CPU main loop.
118 G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp,
119 uint32_t syndrome, uint32_t target_el);
122 * Similarly, but also use unwinding to restore cpu state.
124 G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp,
125 uint32_t syndrome, uint32_t target_el,
129 * For AArch64, map a given EL to an index in the banked_spsr array.
130 * Note that this mapping and the AArch32 mapping defined in bank_number()
131 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
132 * mandated mapping between each other.
134 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
136 static const unsigned int map[4] = {
137 [1] = BANK_SVC, /* EL1. */
138 [2] = BANK_HYP, /* EL2. */
139 [3] = BANK_MON, /* EL3. */
141 assert(el >= 1 && el <= 3);
145 /* Map CPU modes onto saved register banks. */
146 static inline int bank_number(int mode)
149 case ARM_CPU_MODE_USR:
150 case ARM_CPU_MODE_SYS:
152 case ARM_CPU_MODE_SVC:
154 case ARM_CPU_MODE_ABT:
156 case ARM_CPU_MODE_UND:
158 case ARM_CPU_MODE_IRQ:
160 case ARM_CPU_MODE_FIQ:
162 case ARM_CPU_MODE_HYP:
164 case ARM_CPU_MODE_MON:
167 g_assert_not_reached();
171 * r14_bank_number: Map CPU mode onto register bank for r14
173 * Given an AArch32 CPU mode, return the index into the saved register
174 * banks to use for the R14 (LR) in that mode. This is the same as
175 * bank_number(), except for the special case of Hyp mode, where
176 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
177 * This should be used as the index into env->banked_r14[], and
178 * bank_number() used for the index into env->banked_r13[] and
179 * env->banked_spsr[].
181 static inline int r14_bank_number(int mode)
183 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
186 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
187 void arm_translate_init(void);
189 void arm_restore_state_to_opc(CPUState *cs,
190 const TranslationBlock *tb,
191 const uint64_t *data);
194 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
195 #endif /* CONFIG_TCG */
197 typedef enum ARMFPRounding {
206 extern const FloatRoundMode arm_rmode_to_sf_map[6];
208 static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
210 assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
211 return arm_rmode_to_sf_map[rmode];
214 static inline void aarch64_save_sp(CPUARMState *env, int el)
216 if (env->pstate & PSTATE_SP) {
217 env->sp_el[el] = env->xregs[31];
219 env->sp_el[0] = env->xregs[31];
223 static inline void aarch64_restore_sp(CPUARMState *env, int el)
225 if (env->pstate & PSTATE_SP) {
226 env->xregs[31] = env->sp_el[el];
228 env->xregs[31] = env->sp_el[0];
232 static inline void update_spsel(CPUARMState *env, uint32_t imm)
234 unsigned int cur_el = arm_current_el(env);
235 /* Update PSTATE SPSel bit; this requires us to update the
236 * working stack pointer in xregs[31].
238 if (!((imm ^ env->pstate) & PSTATE_SP)) {
241 aarch64_save_sp(env, cur_el);
242 env->pstate = deposit32(env->pstate, 0, 1, imm);
244 /* We rely on illegal updates to SPsel from EL0 to get trapped
245 * at translation time.
247 assert(cur_el >= 1 && cur_el <= 3);
248 aarch64_restore_sp(env, cur_el);
255 * Returns the implementation defined bit-width of physical addresses.
256 * The ARMv8 reference manuals refer to this as PAMax().
258 unsigned int arm_pamax(ARMCPU *cpu);
260 /* Return true if extended addresses are enabled.
261 * This is always the case if our translation regime is 64 bit,
262 * but depends on TTBCR.EAE for 32 bit.
264 static inline bool extended_addresses_enabled(CPUARMState *env)
266 uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
267 if (arm_feature(env, ARM_FEATURE_PMSA) &&
268 arm_feature(env, ARM_FEATURE_V8)) {
271 return arm_el_is_aa64(env, 1) ||
272 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
275 /* Update a QEMU watchpoint based on the information the guest has set in the
276 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
278 void hw_watchpoint_update(ARMCPU *cpu, int n);
279 /* Update the QEMU watchpoints for every guest watchpoint. This does a
280 * complete delete-and-reinstate of the QEMU watchpoint list and so is
281 * suitable for use after migration or on reset.
283 void hw_watchpoint_update_all(ARMCPU *cpu);
284 /* Update a QEMU breakpoint based on the information the guest has set in the
285 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
287 void hw_breakpoint_update(ARMCPU *cpu, int n);
288 /* Update the QEMU breakpoints for every guest breakpoint. This does a
289 * complete delete-and-reinstate of the QEMU breakpoint list and so is
290 * suitable for use after migration or on reset.
292 void hw_breakpoint_update_all(ARMCPU *cpu);
294 /* Callback function for checking if a breakpoint should trigger. */
295 bool arm_debug_check_breakpoint(CPUState *cs);
297 /* Callback function for checking if a watchpoint should trigger. */
298 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
300 /* Adjust addresses (in BE32 mode) before testing against watchpoint
303 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
305 /* Callback function for when a watchpoint or breakpoint triggers. */
306 void arm_debug_excp_handler(CPUState *cs);
308 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
309 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
313 static inline void arm_handle_psci_call(ARMCPU *cpu)
315 g_assert_not_reached();
318 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
319 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
320 /* Actually handle a PSCI call */
321 void arm_handle_psci_call(ARMCPU *cpu);
325 * arm_clear_exclusive: clear the exclusive monitor
327 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
329 static inline void arm_clear_exclusive(CPUARMState *env)
331 env->exclusive_addr = -1;
335 * ARMFaultType: type of an ARM MMU fault
336 * This corresponds to the v8A pseudocode's Fault enumeration,
337 * with extensions for QEMU internal conditions.
339 typedef enum ARMFaultType {
346 ARMFault_Translation,
347 ARMFault_AddressSize,
348 ARMFault_SyncExternal,
349 ARMFault_SyncExternalOnWalk,
351 ARMFault_SyncParityOnWalk,
352 ARMFault_AsyncParity,
353 ARMFault_AsyncExternal,
355 ARMFault_TLBConflict,
356 ARMFault_UnsuppAtomicUpdate,
359 ARMFault_ICacheMaint,
360 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */
361 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
363 ARMFault_GPCFOnOutput,
366 typedef enum ARMGPCF {
375 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
376 * @type: Type of fault
377 * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}.
378 * @level: Table walk level (for translation, access flag and permission faults)
379 * @domain: Domain of the fault address (for non-LPAE CPUs only)
380 * @s2addr: Address that caused a fault at stage 2
381 * @paddr: physical address that caused a fault for gpc
382 * @paddr_space: physical address space that caused a fault for gpc
383 * @stage2: True if we faulted at stage 2
384 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
385 * @s1ns: True if we faulted on a non-secure IPA while in secure state
386 * @ea: True if we should set the EA (external abort type) bit in syndrome
388 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
389 struct ARMMMUFaultInfo {
394 ARMSecuritySpace paddr_space;
404 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
405 * Compare pseudocode EncodeSDFSC(), though unlike that function
406 * we set up a whole FSR-format code including domain field and
407 * putting the high bit of the FSC into bit 10.
409 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi)
416 case ARMFault_AccessFlag:
417 fsc = fi->level == 1 ? 0x3 : 0x6;
419 case ARMFault_Alignment:
422 case ARMFault_Permission:
423 fsc = fi->level == 1 ? 0xd : 0xf;
425 case ARMFault_Domain:
426 fsc = fi->level == 1 ? 0x9 : 0xb;
428 case ARMFault_Translation:
429 fsc = fi->level == 1 ? 0x5 : 0x7;
431 case ARMFault_SyncExternal:
432 fsc = 0x8 | (fi->ea << 12);
434 case ARMFault_SyncExternalOnWalk:
435 fsc = fi->level == 1 ? 0xc : 0xe;
436 fsc |= (fi->ea << 12);
438 case ARMFault_SyncParity:
441 case ARMFault_SyncParityOnWalk:
442 fsc = fi->level == 1 ? 0x40c : 0x40e;
444 case ARMFault_AsyncParity:
447 case ARMFault_AsyncExternal:
448 fsc = 0x406 | (fi->ea << 12);
453 case ARMFault_TLBConflict:
456 case ARMFault_Lockdown:
459 case ARMFault_Exclusive:
462 case ARMFault_ICacheMaint:
465 case ARMFault_Background:
468 case ARMFault_QEMU_NSCExec:
469 fsc = M_FAKE_FSR_NSC_EXEC;
471 case ARMFault_QEMU_SFault:
472 fsc = M_FAKE_FSR_SFAULT;
475 /* Other faults can't occur in a context that requires a
476 * short-format status code.
478 g_assert_not_reached();
481 fsc |= (fi->domain << 4);
486 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
487 * Compare pseudocode EncodeLDFSC(), though unlike that function
488 * we fill in also the LPAE bit 9 of a DFSR format.
490 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
497 case ARMFault_AddressSize:
498 assert(fi->level >= -1 && fi->level <= 3);
505 case ARMFault_AccessFlag:
506 assert(fi->level >= 0 && fi->level <= 3);
507 fsc = 0b001000 | fi->level;
509 case ARMFault_Permission:
510 assert(fi->level >= 0 && fi->level <= 3);
511 fsc = 0b001100 | fi->level;
513 case ARMFault_Translation:
514 assert(fi->level >= -1 && fi->level <= 3);
518 fsc = 0b000100 | fi->level;
521 case ARMFault_SyncExternal:
522 fsc = 0x10 | (fi->ea << 12);
524 case ARMFault_SyncExternalOnWalk:
525 assert(fi->level >= -1 && fi->level <= 3);
529 fsc = 0b010100 | fi->level;
533 case ARMFault_SyncParity:
536 case ARMFault_SyncParityOnWalk:
537 assert(fi->level >= -1 && fi->level <= 3);
541 fsc = 0b011100 | fi->level;
544 case ARMFault_AsyncParity:
547 case ARMFault_AsyncExternal:
548 fsc = 0x11 | (fi->ea << 12);
550 case ARMFault_Alignment:
556 case ARMFault_TLBConflict:
559 case ARMFault_UnsuppAtomicUpdate:
562 case ARMFault_Lockdown:
565 case ARMFault_Exclusive:
568 case ARMFault_GPCFOnWalk:
569 assert(fi->level >= -1 && fi->level <= 3);
573 fsc = 0b100100 | fi->level;
576 case ARMFault_GPCFOnOutput:
580 /* Other faults can't occur in a context that requires a
581 * long-format status code.
583 g_assert_not_reached();
590 static inline bool arm_extabort_type(MemTxResult result)
592 /* The EA bit in syndromes and fault status registers is an
593 * IMPDEF classification of external aborts. ARM implementations
594 * usually use this to indicate AXI bus Decode error (0) or
595 * Slave error (1); in QEMU we follow that.
597 return result != MEMTX_DECODE_ERROR;
600 #ifdef CONFIG_USER_ONLY
601 void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
602 MMUAccessType access_type,
603 bool maperr, uintptr_t ra);
604 void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
605 MMUAccessType access_type, uintptr_t ra);
607 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
608 MMUAccessType access_type, int mmu_idx,
609 bool probe, uintptr_t retaddr);
612 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
614 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
617 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
619 if (arm_feature(env, ARM_FEATURE_M)) {
620 return mmu_idx | ARM_MMU_IDX_M;
622 return mmu_idx | ARM_MMU_IDX_A;
626 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
628 /* AArch64 is always a-profile. */
629 return mmu_idx | ARM_MMU_IDX_A;
632 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
634 /* Return the MMU index for a v7M CPU in the specified security state */
635 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
638 * Return true if the stage 1 translation regime is using LPAE
641 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
643 /* Raise a data fault alignment exception for the specified virtual address */
644 G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
645 MMUAccessType access_type,
646 int mmu_idx, uintptr_t retaddr);
648 #ifndef CONFIG_USER_ONLY
649 /* arm_cpu_do_transaction_failed: handle a memory system error response
650 * (eg "no device/memory present at address") by raising an external abort
653 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
654 vaddr addr, unsigned size,
655 MMUAccessType access_type,
656 int mmu_idx, MemTxAttrs attrs,
657 MemTxResult response, uintptr_t retaddr);
660 /* Call any registered EL change hooks */
661 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
663 ARMELChangeHook *hook, *next;
664 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
665 hook->hook(cpu, hook->opaque);
668 static inline void arm_call_el_change_hook(ARMCPU *cpu)
670 ARMELChangeHook *hook, *next;
671 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
672 hook->hook(cpu, hook->opaque);
676 /* Return true if this address translation regime has two ranges. */
677 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
680 case ARMMMUIdx_Stage1_E0:
681 case ARMMMUIdx_Stage1_E1:
682 case ARMMMUIdx_Stage1_E1_PAN:
683 case ARMMMUIdx_E10_0:
684 case ARMMMUIdx_E10_1:
685 case ARMMMUIdx_E10_1_PAN:
686 case ARMMMUIdx_E20_0:
687 case ARMMMUIdx_E20_2:
688 case ARMMMUIdx_E20_2_PAN:
695 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
698 case ARMMMUIdx_Stage1_E1_PAN:
699 case ARMMMUIdx_E10_1_PAN:
700 case ARMMMUIdx_E20_2_PAN:
707 static inline bool regime_is_stage2(ARMMMUIdx mmu_idx)
709 return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S;
712 /* Return the exception level which controls this address translation regime */
713 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
716 case ARMMMUIdx_E20_0:
717 case ARMMMUIdx_E20_2:
718 case ARMMMUIdx_E20_2_PAN:
719 case ARMMMUIdx_Stage2:
720 case ARMMMUIdx_Stage2_S:
725 case ARMMMUIdx_E10_0:
726 case ARMMMUIdx_Stage1_E0:
727 return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
728 case ARMMMUIdx_Stage1_E1:
729 case ARMMMUIdx_Stage1_E1_PAN:
730 case ARMMMUIdx_E10_1:
731 case ARMMMUIdx_E10_1_PAN:
732 case ARMMMUIdx_MPrivNegPri:
733 case ARMMMUIdx_MUserNegPri:
734 case ARMMMUIdx_MPriv:
735 case ARMMMUIdx_MUser:
736 case ARMMMUIdx_MSPrivNegPri:
737 case ARMMMUIdx_MSUserNegPri:
738 case ARMMMUIdx_MSPriv:
739 case ARMMMUIdx_MSUser:
742 g_assert_not_reached();
746 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
749 case ARMMMUIdx_E20_0:
750 case ARMMMUIdx_Stage1_E0:
751 case ARMMMUIdx_MUser:
752 case ARMMMUIdx_MSUser:
753 case ARMMMUIdx_MUserNegPri:
754 case ARMMMUIdx_MSUserNegPri:
758 case ARMMMUIdx_E10_0:
759 case ARMMMUIdx_E10_1:
760 case ARMMMUIdx_E10_1_PAN:
761 g_assert_not_reached();
765 /* Return the SCTLR value which controls this address translation regime */
766 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
768 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
772 * These are the fields in VTCR_EL2 which affect both the Secure stage 2
773 * and the Non-Secure stage 2 translation regimes (and hence which are
774 * not present in VSTCR_EL2).
776 #define VTCR_SHARED_FIELD_MASK \
777 (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \
778 R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \
781 /* Return the value of the TCR controlling this translation regime */
782 static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
784 if (mmu_idx == ARMMMUIdx_Stage2) {
785 return env->cp15.vtcr_el2;
787 if (mmu_idx == ARMMMUIdx_Stage2_S) {
789 * Secure stage 2 shares fields from VTCR_EL2. We merge those
790 * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format
791 * value so the callers don't need to special case this.
793 * If a future architecture change defines bits in VSTCR_EL2 that
794 * overlap with these VTCR_EL2 fields we may need to revisit this.
796 uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK;
797 v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK;
800 return env->cp15.tcr_el[regime_el(env, mmu_idx)];
803 /* Return true if the translation regime is using LPAE format page tables */
804 static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
806 int el = regime_el(env, mmu_idx);
807 if (el == 2 || arm_el_is_aa64(env, el)) {
810 if (arm_feature(env, ARM_FEATURE_PMSA) &&
811 arm_feature(env, ARM_FEATURE_V8)) {
814 if (arm_feature(env, ARM_FEATURE_LPAE)
815 && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
822 * arm_num_brps: Return number of implemented breakpoints.
823 * Note that the ID register BRPS field is "number of bps - 1",
824 * and we return the actual number of breakpoints.
826 static inline int arm_num_brps(ARMCPU *cpu)
828 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
829 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
831 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
836 * arm_num_wrps: Return number of implemented watchpoints.
837 * Note that the ID register WRPS field is "number of wps - 1",
838 * and we return the actual number of watchpoints.
840 static inline int arm_num_wrps(ARMCPU *cpu)
842 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
843 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
845 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
850 * arm_num_ctx_cmps: Return number of implemented context comparators.
851 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
852 * and we return the actual number of comparators.
854 static inline int arm_num_ctx_cmps(ARMCPU *cpu)
856 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
857 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
859 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
864 * v7m_using_psp: Return true if using process stack pointer
865 * Return true if the CPU is currently using the process stack
866 * pointer, or false if it is using the main stack pointer.
868 static inline bool v7m_using_psp(CPUARMState *env)
870 /* Handler mode always uses the main stack; for thread mode
871 * the CONTROL.SPSEL bit determines the answer.
872 * Note that in v7M it is not possible to be in Handler mode with
873 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
875 return !arm_v7m_is_handler_mode(env) &&
876 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
880 * v7m_sp_limit: Return SP limit for current CPU state
881 * Return the SP limit value for the current CPU security state
884 static inline uint32_t v7m_sp_limit(CPUARMState *env)
886 if (v7m_using_psp(env)) {
887 return env->v7m.psplim[env->v7m.secure];
889 return env->v7m.msplim[env->v7m.secure];
895 * Return true if the v7M CPACR permits access to the FPU for the specified
896 * security state and privilege level.
898 static inline bool v7m_cpacr_pass(CPUARMState *env,
899 bool is_secure, bool is_priv)
901 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
903 case 2: /* UNPREDICTABLE: we treat like 0 */
910 g_assert_not_reached();
915 * aarch32_mode_name(): Return name of the AArch32 CPU mode
916 * @psr: Program Status Register indicating CPU mode
918 * Returns, for debug logging purposes, a printable representation
919 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
920 * the low bits of the specified PSR.
922 static inline const char *aarch32_mode_name(uint32_t psr)
924 static const char cpu_mode_names[16][4] = {
925 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
926 "???", "???", "hyp", "und", "???", "???", "???", "sys"
929 return cpu_mode_names[psr & 0xf];
933 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
935 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
936 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
937 * Must be called with the iothread lock held.
939 void arm_cpu_update_virq(ARMCPU *cpu);
942 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
944 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
945 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
946 * Must be called with the iothread lock held.
948 void arm_cpu_update_vfiq(ARMCPU *cpu);
951 * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
953 * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
954 * following a change to the HCR_EL2.VSE bit.
956 void arm_cpu_update_vserr(ARMCPU *cpu);
960 * @env: The cpu environment
961 * @el: The EL to use.
963 * Return the full ARMMMUIdx for the translation regime for EL.
965 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
969 * @env: The cpu environment
971 * Return the full ARMMMUIdx for the current translation regime.
973 ARMMMUIdx arm_mmu_idx(CPUARMState *env);
976 * arm_stage1_mmu_idx:
977 * @env: The cpu environment
979 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
981 #ifdef CONFIG_USER_ONLY
982 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
984 return ARMMMUIdx_Stage1_E0;
986 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
988 return ARMMMUIdx_Stage1_E0;
991 ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx);
992 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
996 * arm_mmu_idx_is_stage1_of_2:
997 * @mmu_idx: The ARMMMUIdx to test
999 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
1000 * first stage of a two stage regime.
1002 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
1005 case ARMMMUIdx_Stage1_E0:
1006 case ARMMMUIdx_Stage1_E1:
1007 case ARMMMUIdx_Stage1_E1_PAN:
1014 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
1015 const ARMISARegisters *id)
1017 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
1019 if ((features >> ARM_FEATURE_V4T) & 1) {
1022 if ((features >> ARM_FEATURE_V5) & 1) {
1023 valid |= CPSR_Q; /* V5TE in reality*/
1025 if ((features >> ARM_FEATURE_V6) & 1) {
1026 valid |= CPSR_E | CPSR_GE;
1028 if ((features >> ARM_FEATURE_THUMB2) & 1) {
1031 if (isar_feature_aa32_jazelle(id)) {
1034 if (isar_feature_aa32_pan(id)) {
1037 if (isar_feature_aa32_dit(id)) {
1040 if (isar_feature_aa32_ssbs(id)) {
1047 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
1051 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
1052 if (isar_feature_aa64_bti(id)) {
1053 valid |= PSTATE_BTYPE;
1055 if (isar_feature_aa64_pan(id)) {
1056 valid |= PSTATE_PAN;
1058 if (isar_feature_aa64_uao(id)) {
1059 valid |= PSTATE_UAO;
1061 if (isar_feature_aa64_dit(id)) {
1062 valid |= PSTATE_DIT;
1064 if (isar_feature_aa64_ssbs(id)) {
1065 valid |= PSTATE_SSBS;
1067 if (isar_feature_aa64_mte(id)) {
1068 valid |= PSTATE_TCO;
1074 /* Granule size (i.e. page size) */
1075 typedef enum ARMGranuleSize {
1076 /* Same order as TG0 encoding */
1084 * arm_granule_bits: Return address size of the granule in bits
1086 * Return the address size of the granule in bits. This corresponds
1087 * to the pseudocode TGxGranuleBits().
1089 static inline int arm_granule_bits(ARMGranuleSize gran)
1099 g_assert_not_reached();
1104 * Parameters of a given virtual address, as extracted from the
1105 * translation control register (TCR) for a given regime.
1107 typedef struct ARMVAParameters {
1111 unsigned select : 1;
1115 bool tsz_oob : 1; /* tsz has been clamped to legal range */
1119 ARMGranuleSize gran : 2;
1123 * aa64_va_parameters: Return parameters for an AArch64 virtual address
1125 * @va: virtual address to look up
1126 * @mmu_idx: determines translation regime to use
1127 * @data: true if this is a data access
1128 * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32
1129 * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob)
1131 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1132 ARMMMUIdx mmu_idx, bool data,
1135 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
1136 int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
1137 int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
1139 /* Determine if allocation tags are available. */
1140 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
1144 && arm_feature(env, ARM_FEATURE_EL3)
1145 && !(env->cp15.scr_el3 & SCR_ATA)) {
1148 if (el < 2 && arm_is_el2_enabled(env)) {
1149 uint64_t hcr = arm_hcr_el2_eff(env);
1150 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
1154 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
1158 #ifndef CONFIG_USER_ONLY
1160 /* Security attributes for an address, as returned by v8m_security_lookup. */
1161 typedef struct V8M_SAttributes {
1162 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
1171 void v8m_security_lookup(CPUARMState *env, uint32_t address,
1172 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1173 bool secure, V8M_SAttributes *sattrs);
1175 /* Cacheability and shareability attributes for a memory access */
1176 typedef struct ARMCacheAttrs {
1178 * If is_s2_format is true, attrs is the S2 descriptor bits [5:2]
1179 * Otherwise, attrs is the same as the MAIR_EL1 8-bit format
1181 unsigned int attrs:8;
1182 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
1183 bool is_s2_format:1;
1184 bool guarded:1; /* guarded bit of the v8-64 PTE */
1187 /* Fields that are valid upon success. */
1188 typedef struct GetPhysAddrResult {
1190 ARMCacheAttrs cacheattrs;
1191 } GetPhysAddrResult;
1194 * get_phys_addr: get the physical address for a virtual address
1196 * @address: virtual address to get physical address for
1197 * @access_type: 0 for read, 1 for write, 2 for execute
1198 * @mmu_idx: MMU index indicating required translation regime
1199 * @result: set on translation success.
1200 * @fi: set to fault info if the translation fails
1202 * Find the physical address corresponding to the given virtual address,
1203 * by doing a translation table walk on MMU based systems or using the
1204 * MPU state on MPU based systems.
1206 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
1207 * prot and page_size may not be filled in, and the populated fsr value provides
1208 * information on why the translation aborted, in the format of a
1209 * DFSR/IFSR fault register, with the following caveats:
1210 * * we honour the short vs long DFSR format differences.
1211 * * the WnR bit is never set (the caller must do this).
1212 * * for PSMAv5 based systems we don't bother to return a full FSR format
1215 bool get_phys_addr(CPUARMState *env, target_ulong address,
1216 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1217 GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
1218 __attribute__((nonnull));
1221 * get_phys_addr_with_space_nogpc: get the physical address for a virtual
1224 * @address: virtual address to get physical address for
1225 * @access_type: 0 for read, 1 for write, 2 for execute
1226 * @mmu_idx: MMU index indicating required translation regime
1227 * @space: security space for the access
1228 * @result: set on translation success.
1229 * @fi: set to fault info if the translation fails
1231 * Similar to get_phys_addr, but use the given security space and don't perform
1232 * a Granule Protection Check on the resulting address.
1234 bool get_phys_addr_with_space_nogpc(CPUARMState *env, target_ulong address,
1235 MMUAccessType access_type,
1236 ARMMMUIdx mmu_idx, ARMSecuritySpace space,
1237 GetPhysAddrResult *result,
1238 ARMMMUFaultInfo *fi)
1239 __attribute__((nonnull));
1241 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
1242 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1243 bool is_secure, GetPhysAddrResult *result,
1244 ARMMMUFaultInfo *fi, uint32_t *mregion);
1246 void arm_log_exception(CPUState *cs);
1248 #endif /* !CONFIG_USER_ONLY */
1251 * SVE predicates are 1/8 the size of SVE vectors, and cannot use
1252 * the same simd_desc() encoding due to restrictions on size.
1253 * Use these instead.
1255 FIELD(PREDDESC, OPRSZ, 0, 6)
1256 FIELD(PREDDESC, ESZ, 6, 2)
1257 FIELD(PREDDESC, DATA, 8, 24)
1260 * The SVE simd_data field, for memory ops, contains either
1261 * rd (5 bits) or a shift count (2 bits).
1263 #define SVE_MTEDESC_SHIFT 5
1265 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1266 FIELD(MTEDESC, MIDX, 0, 4)
1267 FIELD(MTEDESC, TBI, 4, 2)
1268 FIELD(MTEDESC, TCMA, 6, 2)
1269 FIELD(MTEDESC, WRITE, 8, 1)
1270 FIELD(MTEDESC, ALIGN, 9, 3)
1271 FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */
1273 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
1274 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
1277 * mte_mops_probe: Check where the next MTE failure is for a FEAT_MOPS operation
1279 * @ptr: start address of memory region (dirty pointer)
1280 * @size: length of region (guaranteed not to cross a page boundary)
1281 * @desc: MTEDESC descriptor word (0 means no MTE checks)
1282 * Returns: the size of the region that can be copied without hitting
1283 * an MTE tag failure
1285 * Note that we assume that the caller has already checked the TBI
1286 * and TCMA bits with mte_checks_needed() and an MTE check is definitely
1289 uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size,
1293 * mte_mops_probe_rev: Check where the next MTE failure is for a FEAT_MOPS
1294 * operation going in the reverse direction
1296 * @ptr: *end* address of memory region (dirty pointer)
1297 * @size: length of region (guaranteed not to cross a page boundary)
1298 * @desc: MTEDESC descriptor word (0 means no MTE checks)
1299 * Returns: the size of the region that can be copied without hitting
1300 * an MTE tag failure
1302 * Note that we assume that the caller has already checked the TBI
1303 * and TCMA bits with mte_checks_needed() and an MTE check is definitely
1306 uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size,
1310 * mte_check_fail: Record an MTE tag check failure
1312 * @desc: MTEDESC descriptor word
1313 * @dirty_ptr: Failing dirty address
1316 * This may never return (if the MTE tag checks are configured to fault).
1318 void mte_check_fail(CPUARMState *env, uint32_t desc,
1319 uint64_t dirty_ptr, uintptr_t ra);
1322 * mte_mops_set_tags: Set MTE tags for a portion of a FEAT_MOPS operation
1324 * @dirty_ptr: Start address of memory region (dirty pointer)
1325 * @size: length of region (guaranteed not to cross page boundary)
1326 * @desc: MTEDESC descriptor word
1328 void mte_mops_set_tags(CPUARMState *env, uint64_t dirty_ptr, uint64_t size,
1331 static inline int allocation_tag_from_addr(uint64_t ptr)
1333 return extract64(ptr, 56, 4);
1336 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
1338 return deposit64(ptr, 56, 4, rtag);
1341 /* Return true if tbi bits mean that the access is checked. */
1342 static inline bool tbi_check(uint32_t desc, int bit55)
1344 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
1347 /* Return true if tcma bits mean that the access is unchecked. */
1348 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag)
1351 * We had extracted bit55 and ptr_tag for other reasons, so fold
1352 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1354 bool match = ((ptr_tag + bit55) & 0xf) == 0;
1355 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1;
1356 return tcma && match;
1360 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1361 * for the tag to be present in the FAR_ELx register. But for user-only
1362 * mode, we do not have a TLB with which to implement this, so we must
1363 * remove the top byte.
1365 static inline uint64_t useronly_clean_ptr(uint64_t ptr)
1367 #ifdef CONFIG_USER_ONLY
1368 /* TBI0 is known to be enabled, while TBI1 is disabled. */
1369 ptr &= sextract64(ptr, 0, 56);
1374 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
1376 #ifdef CONFIG_USER_ONLY
1377 int64_t clean_ptr = sextract64(ptr, 0, 56);
1378 if (tbi_check(desc, clean_ptr < 0)) {
1385 /* Values for M-profile PSR.ECI for MVE insns */
1387 ECI_NONE = 0, /* No completed beats */
1388 ECI_A0 = 1, /* Completed: A0 */
1389 ECI_A0A1 = 2, /* Completed: A0, A1 */
1391 ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */
1392 ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */
1393 /* All other values reserved */
1396 /* Definitions for the PMU registers */
1397 #define PMCRN_MASK 0xf800
1398 #define PMCRN_SHIFT 11
1408 * Mask of PMCR bits writable by guest (not including WO bits like C, P,
1409 * which can be written as 1 to trigger behaviour but which stay RAZ).
1411 #define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1413 #define PMXEVTYPER_P 0x80000000
1414 #define PMXEVTYPER_U 0x40000000
1415 #define PMXEVTYPER_NSK 0x20000000
1416 #define PMXEVTYPER_NSU 0x10000000
1417 #define PMXEVTYPER_NSH 0x08000000
1418 #define PMXEVTYPER_M 0x04000000
1419 #define PMXEVTYPER_MT 0x02000000
1420 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1421 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1422 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1423 PMXEVTYPER_M | PMXEVTYPER_MT | \
1424 PMXEVTYPER_EVTCOUNT)
1426 #define PMCCFILTR 0xf8000000
1427 #define PMCCFILTR_M PMXEVTYPER_M
1428 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1430 static inline uint32_t pmu_num_counters(CPUARMState *env)
1432 ARMCPU *cpu = env_archcpu(env);
1434 return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
1437 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1438 static inline uint64_t pmu_counter_mask(CPUARMState *env)
1440 return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);
1443 #ifdef TARGET_AARCH64
1444 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1445 int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
1446 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
1447 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
1448 int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
1449 int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
1450 int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
1451 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
1452 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
1453 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
1454 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
1455 void aarch64_max_tcg_initfn(Object *obj);
1456 void aarch64_add_pauth_properties(Object *obj);
1457 void aarch64_add_sve_properties(Object *obj);
1458 void aarch64_add_sme_properties(Object *obj);
1461 /* Read the CONTROL register as the MRS instruction would. */
1462 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
1465 * Return a pointer to the location where we currently store the
1466 * stack pointer for the requested security state and thread mode.
1467 * This pointer will become invalid if the CPU state is updated
1468 * such that the stack pointers are switched around (eg changing
1469 * the SPSEL control bit).
1471 uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
1472 bool threadmode, bool spsel);
1474 bool el_is_in_host(CPUARMState *env, int el);
1476 void aa32_max_features(ARMCPU *cpu);
1477 int exception_target_el(CPUARMState *env);
1478 bool arm_singlestep_active(CPUARMState *env);
1479 bool arm_generate_debug_exceptions(CPUARMState *env);
1483 * @param: parameters defining the MMU setup
1485 * Return a mask of the address bits that contain the authentication code,
1486 * given the MMU config defined by @param.
1488 static inline uint64_t pauth_ptr_mask(ARMVAParameters param)
1490 int bot_pac_bit = 64 - param.tsz;
1491 int top_pac_bit = 64 - 8 * param.tbi;
1493 return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
1496 /* Add the cpreg definitions for debug related system registers */
1497 void define_debug_regs(ARMCPU *cpu);
1499 /* Effective value of MDCR_EL2 */
1500 static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
1502 return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;
1505 /* Powers of 2 for sve_vq_map et al. */
1506 #define SVE_VQ_POW2_MAP \
1507 ((1 << (1 - 1)) | (1 << (2 - 1)) | \
1508 (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
1511 * Return true if it is possible to take a fine-grained-trap to EL2.
1513 static inline bool arm_fgt_active(CPUARMState *env, int el)
1516 * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
1517 * that can affect EL0, but it is harmless to do the test also for
1518 * traps on registers that are only accessible at EL1 because if the test
1519 * returns true then we can't be executing at EL1 anyway.
1520 * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
1521 * traps from AArch32 only happen for the EL0 is AArch32 case.
1523 return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
1524 el < 2 && arm_is_el2_enabled(env) &&
1525 arm_el_is_aa64(env, 1) &&
1526 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
1527 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
1530 void assert_hflags_rebuild_correctly(CPUARMState *env);
1533 * Although the ARM implementation of hardware assisted debugging
1534 * allows for different breakpoints per-core, the current GDB
1535 * interface treats them as a global pool of registers (which seems to
1536 * be the case for x86, ppc and s390). As a result we store one copy
1537 * of registers which is used for all active cores.
1539 * Write access is serialised by virtue of the GDB protocol which
1540 * updates things. Read access (i.e. when the values are copied to the
1541 * vCPU) is also gated by GDB's run control.
1543 * This is not unreasonable as most of the time debugging kernels you
1544 * never know which core will eventually execute your function.
1553 * The watchpoint registers can cover more area than the requested
1554 * watchpoint so we need to store the additional information
1555 * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
1556 * when the watchpoint is hit.
1561 CPUWatchpoint details;
1564 /* Maximum and current break/watch point counts */
1565 extern int max_hw_bps, max_hw_wps;
1566 extern GArray *hw_breakpoints, *hw_watchpoints;
1568 #define cur_hw_wps (hw_watchpoints->len)
1569 #define cur_hw_bps (hw_breakpoints->len)
1570 #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
1571 #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
1573 bool find_hw_breakpoint(CPUState *cpu, target_ulong pc);
1574 int insert_hw_breakpoint(target_ulong pc);
1575 int delete_hw_breakpoint(target_ulong pc);
1577 bool check_watchpoint_in_range(int i, target_ulong addr);
1578 CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr);
1579 int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type);
1580 int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);