2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
29 #include "tcg/tcg-gvec-desc.h"
32 /* register banks for CPU modes */
42 static inline bool excp_is_internal(int excp)
44 /* Return true if this exception number represents a QEMU-internal
45 * exception that will not be passed to the guest.
47 return excp == EXCP_INTERRUPT
50 || excp == EXCP_HALTED
51 || excp == EXCP_EXCEPTION_EXIT
52 || excp == EXCP_KERNEL_TRAP
53 || excp == EXCP_SEMIHOST;
56 /* Scale factor for generic timers, ie number of ns per tick.
57 * This gives a 62.5MHz timer.
59 #define GTIMER_SCALE 16
61 /* Bit definitions for the v7M CONTROL register */
62 FIELD(V7M_CONTROL, NPRIV, 0, 1)
63 FIELD(V7M_CONTROL, SPSEL, 1, 1)
64 FIELD(V7M_CONTROL, FPCA, 2, 1)
65 FIELD(V7M_CONTROL, SFPA, 3, 1)
67 /* Bit definitions for v7M exception return payload */
68 FIELD(V7M_EXCRET, ES, 0, 1)
69 FIELD(V7M_EXCRET, RES0, 1, 1)
70 FIELD(V7M_EXCRET, SPSEL, 2, 1)
71 FIELD(V7M_EXCRET, MODE, 3, 1)
72 FIELD(V7M_EXCRET, FTYPE, 4, 1)
73 FIELD(V7M_EXCRET, DCRS, 5, 1)
74 FIELD(V7M_EXCRET, S, 6, 1)
75 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
77 /* Minimum value which is a magic number for exception return */
78 #define EXC_RETURN_MIN_MAGIC 0xff000000
79 /* Minimum number which is a magic number for function or exception return
80 * when using v8M security extension
82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
84 /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
85 FIELD(DBGWCR, E, 0, 1)
86 FIELD(DBGWCR, PAC, 1, 2)
87 FIELD(DBGWCR, LSC, 3, 2)
88 FIELD(DBGWCR, BAS, 5, 8)
89 FIELD(DBGWCR, HMC, 13, 1)
90 FIELD(DBGWCR, SSC, 14, 2)
91 FIELD(DBGWCR, LBN, 16, 4)
92 FIELD(DBGWCR, WT, 20, 1)
93 FIELD(DBGWCR, MASK, 24, 5)
94 FIELD(DBGWCR, SSCE, 29, 1)
96 /* We use a few fake FSR values for internal purposes in M profile.
97 * M profile cores don't have A/R format FSRs, but currently our
98 * get_phys_addr() code assumes A/R profile and reports failures via
99 * an A/R format FSR value. We then translate that into the proper
100 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
101 * Mostly the FSR values we use for this are those defined for v7PMSA,
102 * since we share some of that codepath. A few kinds of fault are
103 * only for M profile and have no A/R equivalent, though, so we have
104 * to pick a value from the reserved range (which we never otherwise
105 * generate) to use for these.
106 * These values will never be visible to the guest.
108 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
109 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
112 * raise_exception: Raise the specified exception.
113 * Raise a guest exception with the specified value, syndrome register
114 * and target exception level. This should be called from helper functions,
115 * and never returns because we will longjump back up to the CPU main loop.
117 G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp,
118 uint32_t syndrome, uint32_t target_el);
121 * Similarly, but also use unwinding to restore cpu state.
123 G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp,
124 uint32_t syndrome, uint32_t target_el,
128 * For AArch64, map a given EL to an index in the banked_spsr array.
129 * Note that this mapping and the AArch32 mapping defined in bank_number()
130 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
131 * mandated mapping between each other.
133 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
135 static const unsigned int map[4] = {
136 [1] = BANK_SVC, /* EL1. */
137 [2] = BANK_HYP, /* EL2. */
138 [3] = BANK_MON, /* EL3. */
140 assert(el >= 1 && el <= 3);
144 /* Map CPU modes onto saved register banks. */
145 static inline int bank_number(int mode)
148 case ARM_CPU_MODE_USR:
149 case ARM_CPU_MODE_SYS:
151 case ARM_CPU_MODE_SVC:
153 case ARM_CPU_MODE_ABT:
155 case ARM_CPU_MODE_UND:
157 case ARM_CPU_MODE_IRQ:
159 case ARM_CPU_MODE_FIQ:
161 case ARM_CPU_MODE_HYP:
163 case ARM_CPU_MODE_MON:
166 g_assert_not_reached();
170 * r14_bank_number: Map CPU mode onto register bank for r14
172 * Given an AArch32 CPU mode, return the index into the saved register
173 * banks to use for the R14 (LR) in that mode. This is the same as
174 * bank_number(), except for the special case of Hyp mode, where
175 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
176 * This should be used as the index into env->banked_r14[], and
177 * bank_number() used for the index into env->banked_r13[] and
178 * env->banked_spsr[].
180 static inline int r14_bank_number(int mode)
182 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
185 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
186 void arm_translate_init(void);
188 void arm_restore_state_to_opc(CPUState *cs,
189 const TranslationBlock *tb,
190 const uint64_t *data);
193 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
194 #endif /* CONFIG_TCG */
196 typedef enum ARMFPRounding {
205 extern const FloatRoundMode arm_rmode_to_sf_map[6];
207 static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
209 assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
210 return arm_rmode_to_sf_map[rmode];
213 static inline void aarch64_save_sp(CPUARMState *env, int el)
215 if (env->pstate & PSTATE_SP) {
216 env->sp_el[el] = env->xregs[31];
218 env->sp_el[0] = env->xregs[31];
222 static inline void aarch64_restore_sp(CPUARMState *env, int el)
224 if (env->pstate & PSTATE_SP) {
225 env->xregs[31] = env->sp_el[el];
227 env->xregs[31] = env->sp_el[0];
231 static inline void update_spsel(CPUARMState *env, uint32_t imm)
233 unsigned int cur_el = arm_current_el(env);
234 /* Update PSTATE SPSel bit; this requires us to update the
235 * working stack pointer in xregs[31].
237 if (!((imm ^ env->pstate) & PSTATE_SP)) {
240 aarch64_save_sp(env, cur_el);
241 env->pstate = deposit32(env->pstate, 0, 1, imm);
243 /* We rely on illegal updates to SPsel from EL0 to get trapped
244 * at translation time.
246 assert(cur_el >= 1 && cur_el <= 3);
247 aarch64_restore_sp(env, cur_el);
254 * Returns the implementation defined bit-width of physical addresses.
255 * The ARMv8 reference manuals refer to this as PAMax().
257 unsigned int arm_pamax(ARMCPU *cpu);
259 /* Return true if extended addresses are enabled.
260 * This is always the case if our translation regime is 64 bit,
261 * but depends on TTBCR.EAE for 32 bit.
263 static inline bool extended_addresses_enabled(CPUARMState *env)
265 uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
266 if (arm_feature(env, ARM_FEATURE_PMSA) &&
267 arm_feature(env, ARM_FEATURE_V8)) {
270 return arm_el_is_aa64(env, 1) ||
271 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
274 /* Update a QEMU watchpoint based on the information the guest has set in the
275 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
277 void hw_watchpoint_update(ARMCPU *cpu, int n);
278 /* Update the QEMU watchpoints for every guest watchpoint. This does a
279 * complete delete-and-reinstate of the QEMU watchpoint list and so is
280 * suitable for use after migration or on reset.
282 void hw_watchpoint_update_all(ARMCPU *cpu);
283 /* Update a QEMU breakpoint based on the information the guest has set in the
284 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
286 void hw_breakpoint_update(ARMCPU *cpu, int n);
287 /* Update the QEMU breakpoints for every guest breakpoint. This does a
288 * complete delete-and-reinstate of the QEMU breakpoint list and so is
289 * suitable for use after migration or on reset.
291 void hw_breakpoint_update_all(ARMCPU *cpu);
293 /* Callback function for checking if a breakpoint should trigger. */
294 bool arm_debug_check_breakpoint(CPUState *cs);
296 /* Callback function for checking if a watchpoint should trigger. */
297 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
299 /* Adjust addresses (in BE32 mode) before testing against watchpoint
302 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
304 /* Callback function for when a watchpoint or breakpoint triggers. */
305 void arm_debug_excp_handler(CPUState *cs);
307 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
308 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
312 static inline void arm_handle_psci_call(ARMCPU *cpu)
314 g_assert_not_reached();
317 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
318 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
319 /* Actually handle a PSCI call */
320 void arm_handle_psci_call(ARMCPU *cpu);
324 * arm_clear_exclusive: clear the exclusive monitor
326 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
328 static inline void arm_clear_exclusive(CPUARMState *env)
330 env->exclusive_addr = -1;
334 * ARMFaultType: type of an ARM MMU fault
335 * This corresponds to the v8A pseudocode's Fault enumeration,
336 * with extensions for QEMU internal conditions.
338 typedef enum ARMFaultType {
345 ARMFault_Translation,
346 ARMFault_AddressSize,
347 ARMFault_SyncExternal,
348 ARMFault_SyncExternalOnWalk,
350 ARMFault_SyncParityOnWalk,
351 ARMFault_AsyncParity,
352 ARMFault_AsyncExternal,
354 ARMFault_TLBConflict,
355 ARMFault_UnsuppAtomicUpdate,
358 ARMFault_ICacheMaint,
359 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */
360 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
364 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
365 * @type: Type of fault
366 * @level: Table walk level (for translation, access flag and permission faults)
367 * @domain: Domain of the fault address (for non-LPAE CPUs only)
368 * @s2addr: Address that caused a fault at stage 2
369 * @stage2: True if we faulted at stage 2
370 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
371 * @s1ns: True if we faulted on a non-secure IPA while in secure state
372 * @ea: True if we should set the EA (external abort type) bit in syndrome
374 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
375 struct ARMMMUFaultInfo {
387 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
388 * Compare pseudocode EncodeSDFSC(), though unlike that function
389 * we set up a whole FSR-format code including domain field and
390 * putting the high bit of the FSC into bit 10.
392 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi)
399 case ARMFault_AccessFlag:
400 fsc = fi->level == 1 ? 0x3 : 0x6;
402 case ARMFault_Alignment:
405 case ARMFault_Permission:
406 fsc = fi->level == 1 ? 0xd : 0xf;
408 case ARMFault_Domain:
409 fsc = fi->level == 1 ? 0x9 : 0xb;
411 case ARMFault_Translation:
412 fsc = fi->level == 1 ? 0x5 : 0x7;
414 case ARMFault_SyncExternal:
415 fsc = 0x8 | (fi->ea << 12);
417 case ARMFault_SyncExternalOnWalk:
418 fsc = fi->level == 1 ? 0xc : 0xe;
419 fsc |= (fi->ea << 12);
421 case ARMFault_SyncParity:
424 case ARMFault_SyncParityOnWalk:
425 fsc = fi->level == 1 ? 0x40c : 0x40e;
427 case ARMFault_AsyncParity:
430 case ARMFault_AsyncExternal:
431 fsc = 0x406 | (fi->ea << 12);
436 case ARMFault_TLBConflict:
439 case ARMFault_Lockdown:
442 case ARMFault_Exclusive:
445 case ARMFault_ICacheMaint:
448 case ARMFault_Background:
451 case ARMFault_QEMU_NSCExec:
452 fsc = M_FAKE_FSR_NSC_EXEC;
454 case ARMFault_QEMU_SFault:
455 fsc = M_FAKE_FSR_SFAULT;
458 /* Other faults can't occur in a context that requires a
459 * short-format status code.
461 g_assert_not_reached();
464 fsc |= (fi->domain << 4);
469 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
470 * Compare pseudocode EncodeLDFSC(), though unlike that function
471 * we fill in also the LPAE bit 9 of a DFSR format.
473 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
480 case ARMFault_AddressSize:
481 assert(fi->level >= -1 && fi->level <= 3);
488 case ARMFault_AccessFlag:
489 assert(fi->level >= 0 && fi->level <= 3);
490 fsc = 0b001000 | fi->level;
492 case ARMFault_Permission:
493 assert(fi->level >= 0 && fi->level <= 3);
494 fsc = 0b001100 | fi->level;
496 case ARMFault_Translation:
497 assert(fi->level >= -1 && fi->level <= 3);
501 fsc = 0b000100 | fi->level;
504 case ARMFault_SyncExternal:
505 fsc = 0x10 | (fi->ea << 12);
507 case ARMFault_SyncExternalOnWalk:
508 assert(fi->level >= -1 && fi->level <= 3);
512 fsc = 0b010100 | fi->level;
516 case ARMFault_SyncParity:
519 case ARMFault_SyncParityOnWalk:
520 assert(fi->level >= -1 && fi->level <= 3);
524 fsc = 0b011100 | fi->level;
527 case ARMFault_AsyncParity:
530 case ARMFault_AsyncExternal:
531 fsc = 0x11 | (fi->ea << 12);
533 case ARMFault_Alignment:
539 case ARMFault_TLBConflict:
542 case ARMFault_UnsuppAtomicUpdate:
545 case ARMFault_Lockdown:
548 case ARMFault_Exclusive:
552 /* Other faults can't occur in a context that requires a
553 * long-format status code.
555 g_assert_not_reached();
562 static inline bool arm_extabort_type(MemTxResult result)
564 /* The EA bit in syndromes and fault status registers is an
565 * IMPDEF classification of external aborts. ARM implementations
566 * usually use this to indicate AXI bus Decode error (0) or
567 * Slave error (1); in QEMU we follow that.
569 return result != MEMTX_DECODE_ERROR;
572 #ifdef CONFIG_USER_ONLY
573 void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
574 MMUAccessType access_type,
575 bool maperr, uintptr_t ra);
576 void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
577 MMUAccessType access_type, uintptr_t ra);
579 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
580 MMUAccessType access_type, int mmu_idx,
581 bool probe, uintptr_t retaddr);
584 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
586 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
589 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
591 if (arm_feature(env, ARM_FEATURE_M)) {
592 return mmu_idx | ARM_MMU_IDX_M;
594 return mmu_idx | ARM_MMU_IDX_A;
598 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
600 /* AArch64 is always a-profile. */
601 return mmu_idx | ARM_MMU_IDX_A;
604 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
606 /* Return the MMU index for a v7M CPU in the specified security state */
607 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
610 * Return true if the stage 1 translation regime is using LPAE
613 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
615 /* Raise a data fault alignment exception for the specified virtual address */
616 G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
617 MMUAccessType access_type,
618 int mmu_idx, uintptr_t retaddr);
620 #ifndef CONFIG_USER_ONLY
621 /* arm_cpu_do_transaction_failed: handle a memory system error response
622 * (eg "no device/memory present at address") by raising an external abort
625 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
626 vaddr addr, unsigned size,
627 MMUAccessType access_type,
628 int mmu_idx, MemTxAttrs attrs,
629 MemTxResult response, uintptr_t retaddr);
632 /* Call any registered EL change hooks */
633 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
635 ARMELChangeHook *hook, *next;
636 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
637 hook->hook(cpu, hook->opaque);
640 static inline void arm_call_el_change_hook(ARMCPU *cpu)
642 ARMELChangeHook *hook, *next;
643 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
644 hook->hook(cpu, hook->opaque);
648 /* Return true if this address translation regime has two ranges. */
649 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
652 case ARMMMUIdx_Stage1_E0:
653 case ARMMMUIdx_Stage1_E1:
654 case ARMMMUIdx_Stage1_E1_PAN:
655 case ARMMMUIdx_E10_0:
656 case ARMMMUIdx_E10_1:
657 case ARMMMUIdx_E10_1_PAN:
658 case ARMMMUIdx_E20_0:
659 case ARMMMUIdx_E20_2:
660 case ARMMMUIdx_E20_2_PAN:
667 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
670 case ARMMMUIdx_Stage1_E1_PAN:
671 case ARMMMUIdx_E10_1_PAN:
672 case ARMMMUIdx_E20_2_PAN:
679 static inline bool regime_is_stage2(ARMMMUIdx mmu_idx)
681 return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S;
684 /* Return the exception level which controls this address translation regime */
685 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
688 case ARMMMUIdx_E20_0:
689 case ARMMMUIdx_E20_2:
690 case ARMMMUIdx_E20_2_PAN:
691 case ARMMMUIdx_Stage2:
692 case ARMMMUIdx_Stage2_S:
697 case ARMMMUIdx_E10_0:
698 case ARMMMUIdx_Stage1_E0:
699 return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
700 case ARMMMUIdx_Stage1_E1:
701 case ARMMMUIdx_Stage1_E1_PAN:
702 case ARMMMUIdx_E10_1:
703 case ARMMMUIdx_E10_1_PAN:
704 case ARMMMUIdx_MPrivNegPri:
705 case ARMMMUIdx_MUserNegPri:
706 case ARMMMUIdx_MPriv:
707 case ARMMMUIdx_MUser:
708 case ARMMMUIdx_MSPrivNegPri:
709 case ARMMMUIdx_MSUserNegPri:
710 case ARMMMUIdx_MSPriv:
711 case ARMMMUIdx_MSUser:
714 g_assert_not_reached();
718 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
721 case ARMMMUIdx_E20_0:
722 case ARMMMUIdx_Stage1_E0:
723 case ARMMMUIdx_MUser:
724 case ARMMMUIdx_MSUser:
725 case ARMMMUIdx_MUserNegPri:
726 case ARMMMUIdx_MSUserNegPri:
730 case ARMMMUIdx_E10_0:
731 case ARMMMUIdx_E10_1:
732 case ARMMMUIdx_E10_1_PAN:
733 g_assert_not_reached();
737 /* Return the SCTLR value which controls this address translation regime */
738 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
740 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
744 * These are the fields in VTCR_EL2 which affect both the Secure stage 2
745 * and the Non-Secure stage 2 translation regimes (and hence which are
746 * not present in VSTCR_EL2).
748 #define VTCR_SHARED_FIELD_MASK \
749 (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \
750 R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \
753 /* Return the value of the TCR controlling this translation regime */
754 static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
756 if (mmu_idx == ARMMMUIdx_Stage2) {
757 return env->cp15.vtcr_el2;
759 if (mmu_idx == ARMMMUIdx_Stage2_S) {
761 * Secure stage 2 shares fields from VTCR_EL2. We merge those
762 * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format
763 * value so the callers don't need to special case this.
765 * If a future architecture change defines bits in VSTCR_EL2 that
766 * overlap with these VTCR_EL2 fields we may need to revisit this.
768 uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK;
769 v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK;
772 return env->cp15.tcr_el[regime_el(env, mmu_idx)];
775 /* Return true if the translation regime is using LPAE format page tables */
776 static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
778 int el = regime_el(env, mmu_idx);
779 if (el == 2 || arm_el_is_aa64(env, el)) {
782 if (arm_feature(env, ARM_FEATURE_PMSA) &&
783 arm_feature(env, ARM_FEATURE_V8)) {
786 if (arm_feature(env, ARM_FEATURE_LPAE)
787 && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
794 * arm_num_brps: Return number of implemented breakpoints.
795 * Note that the ID register BRPS field is "number of bps - 1",
796 * and we return the actual number of breakpoints.
798 static inline int arm_num_brps(ARMCPU *cpu)
800 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
801 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
803 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
808 * arm_num_wrps: Return number of implemented watchpoints.
809 * Note that the ID register WRPS field is "number of wps - 1",
810 * and we return the actual number of watchpoints.
812 static inline int arm_num_wrps(ARMCPU *cpu)
814 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
815 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
817 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
822 * arm_num_ctx_cmps: Return number of implemented context comparators.
823 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
824 * and we return the actual number of comparators.
826 static inline int arm_num_ctx_cmps(ARMCPU *cpu)
828 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
829 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
831 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
836 * v7m_using_psp: Return true if using process stack pointer
837 * Return true if the CPU is currently using the process stack
838 * pointer, or false if it is using the main stack pointer.
840 static inline bool v7m_using_psp(CPUARMState *env)
842 /* Handler mode always uses the main stack; for thread mode
843 * the CONTROL.SPSEL bit determines the answer.
844 * Note that in v7M it is not possible to be in Handler mode with
845 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
847 return !arm_v7m_is_handler_mode(env) &&
848 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
852 * v7m_sp_limit: Return SP limit for current CPU state
853 * Return the SP limit value for the current CPU security state
856 static inline uint32_t v7m_sp_limit(CPUARMState *env)
858 if (v7m_using_psp(env)) {
859 return env->v7m.psplim[env->v7m.secure];
861 return env->v7m.msplim[env->v7m.secure];
867 * Return true if the v7M CPACR permits access to the FPU for the specified
868 * security state and privilege level.
870 static inline bool v7m_cpacr_pass(CPUARMState *env,
871 bool is_secure, bool is_priv)
873 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
875 case 2: /* UNPREDICTABLE: we treat like 0 */
882 g_assert_not_reached();
887 * aarch32_mode_name(): Return name of the AArch32 CPU mode
888 * @psr: Program Status Register indicating CPU mode
890 * Returns, for debug logging purposes, a printable representation
891 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
892 * the low bits of the specified PSR.
894 static inline const char *aarch32_mode_name(uint32_t psr)
896 static const char cpu_mode_names[16][4] = {
897 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
898 "???", "???", "hyp", "und", "???", "???", "???", "sys"
901 return cpu_mode_names[psr & 0xf];
905 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
907 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
908 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
909 * Must be called with the iothread lock held.
911 void arm_cpu_update_virq(ARMCPU *cpu);
914 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
916 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
917 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
918 * Must be called with the iothread lock held.
920 void arm_cpu_update_vfiq(ARMCPU *cpu);
923 * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
925 * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
926 * following a change to the HCR_EL2.VSE bit.
928 void arm_cpu_update_vserr(ARMCPU *cpu);
932 * @env: The cpu environment
933 * @el: The EL to use.
935 * Return the full ARMMMUIdx for the translation regime for EL.
937 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
941 * @env: The cpu environment
943 * Return the full ARMMMUIdx for the current translation regime.
945 ARMMMUIdx arm_mmu_idx(CPUARMState *env);
948 * arm_stage1_mmu_idx:
949 * @env: The cpu environment
951 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
953 #ifdef CONFIG_USER_ONLY
954 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
956 return ARMMMUIdx_Stage1_E0;
958 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
960 return ARMMMUIdx_Stage1_E0;
963 ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx);
964 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
968 * arm_mmu_idx_is_stage1_of_2:
969 * @mmu_idx: The ARMMMUIdx to test
971 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
972 * first stage of a two stage regime.
974 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
977 case ARMMMUIdx_Stage1_E0:
978 case ARMMMUIdx_Stage1_E1:
979 case ARMMMUIdx_Stage1_E1_PAN:
986 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
987 const ARMISARegisters *id)
989 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
991 if ((features >> ARM_FEATURE_V4T) & 1) {
994 if ((features >> ARM_FEATURE_V5) & 1) {
995 valid |= CPSR_Q; /* V5TE in reality*/
997 if ((features >> ARM_FEATURE_V6) & 1) {
998 valid |= CPSR_E | CPSR_GE;
1000 if ((features >> ARM_FEATURE_THUMB2) & 1) {
1003 if (isar_feature_aa32_jazelle(id)) {
1006 if (isar_feature_aa32_pan(id)) {
1009 if (isar_feature_aa32_dit(id)) {
1012 if (isar_feature_aa32_ssbs(id)) {
1019 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
1023 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
1024 if (isar_feature_aa64_bti(id)) {
1025 valid |= PSTATE_BTYPE;
1027 if (isar_feature_aa64_pan(id)) {
1028 valid |= PSTATE_PAN;
1030 if (isar_feature_aa64_uao(id)) {
1031 valid |= PSTATE_UAO;
1033 if (isar_feature_aa64_dit(id)) {
1034 valid |= PSTATE_DIT;
1036 if (isar_feature_aa64_ssbs(id)) {
1037 valid |= PSTATE_SSBS;
1039 if (isar_feature_aa64_mte(id)) {
1040 valid |= PSTATE_TCO;
1046 /* Granule size (i.e. page size) */
1047 typedef enum ARMGranuleSize {
1048 /* Same order as TG0 encoding */
1056 * arm_granule_bits: Return address size of the granule in bits
1058 * Return the address size of the granule in bits. This corresponds
1059 * to the pseudocode TGxGranuleBits().
1061 static inline int arm_granule_bits(ARMGranuleSize gran)
1071 g_assert_not_reached();
1076 * Parameters of a given virtual address, as extracted from the
1077 * translation control register (TCR) for a given regime.
1079 typedef struct ARMVAParameters {
1083 unsigned select : 1;
1087 bool tsz_oob : 1; /* tsz has been clamped to legal range */
1091 ARMGranuleSize gran : 2;
1094 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1095 ARMMMUIdx mmu_idx, bool data);
1097 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
1098 int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
1099 int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
1101 /* Determine if allocation tags are available. */
1102 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
1106 && arm_feature(env, ARM_FEATURE_EL3)
1107 && !(env->cp15.scr_el3 & SCR_ATA)) {
1110 if (el < 2 && arm_is_el2_enabled(env)) {
1111 uint64_t hcr = arm_hcr_el2_eff(env);
1112 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
1116 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
1120 #ifndef CONFIG_USER_ONLY
1122 /* Security attributes for an address, as returned by v8m_security_lookup. */
1123 typedef struct V8M_SAttributes {
1124 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
1133 void v8m_security_lookup(CPUARMState *env, uint32_t address,
1134 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1135 bool secure, V8M_SAttributes *sattrs);
1137 /* Cacheability and shareability attributes for a memory access */
1138 typedef struct ARMCacheAttrs {
1140 * If is_s2_format is true, attrs is the S2 descriptor bits [5:2]
1141 * Otherwise, attrs is the same as the MAIR_EL1 8-bit format
1143 unsigned int attrs:8;
1144 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
1145 bool is_s2_format:1;
1146 bool guarded:1; /* guarded bit of the v8-64 PTE */
1149 /* Fields that are valid upon success. */
1150 typedef struct GetPhysAddrResult {
1152 ARMCacheAttrs cacheattrs;
1153 } GetPhysAddrResult;
1156 * get_phys_addr_with_secure: get the physical address for a virtual address
1158 * @address: virtual address to get physical address for
1159 * @access_type: 0 for read, 1 for write, 2 for execute
1160 * @mmu_idx: MMU index indicating required translation regime
1161 * @is_secure: security state for the access
1162 * @result: set on translation success.
1163 * @fi: set to fault info if the translation fails
1165 * Find the physical address corresponding to the given virtual address,
1166 * by doing a translation table walk on MMU based systems or using the
1167 * MPU state on MPU based systems.
1169 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
1170 * prot and page_size may not be filled in, and the populated fsr value provides
1171 * information on why the translation aborted, in the format of a
1172 * DFSR/IFSR fault register, with the following caveats:
1173 * * we honour the short vs long DFSR format differences.
1174 * * the WnR bit is never set (the caller must do this).
1175 * * for PSMAv5 based systems we don't bother to return a full FSR format
1178 bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
1179 MMUAccessType access_type,
1180 ARMMMUIdx mmu_idx, bool is_secure,
1181 GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
1182 __attribute__((nonnull));
1185 * get_phys_addr: get the physical address for a virtual address
1187 * @address: virtual address to get physical address for
1188 * @access_type: 0 for read, 1 for write, 2 for execute
1189 * @mmu_idx: MMU index indicating required translation regime
1190 * @result: set on translation success.
1191 * @fi: set to fault info if the translation fails
1193 * Similarly, but use the security regime of @mmu_idx.
1195 bool get_phys_addr(CPUARMState *env, target_ulong address,
1196 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1197 GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
1198 __attribute__((nonnull));
1200 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
1201 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1202 bool is_secure, GetPhysAddrResult *result,
1203 ARMMMUFaultInfo *fi, uint32_t *mregion);
1205 void arm_log_exception(CPUState *cs);
1207 #endif /* !CONFIG_USER_ONLY */
1210 * The log2 of the words in the tag block, for GMID_EL1.BS.
1211 * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
1213 #define GMID_EL1_BS 6
1216 * SVE predicates are 1/8 the size of SVE vectors, and cannot use
1217 * the same simd_desc() encoding due to restrictions on size.
1218 * Use these instead.
1220 FIELD(PREDDESC, OPRSZ, 0, 6)
1221 FIELD(PREDDESC, ESZ, 6, 2)
1222 FIELD(PREDDESC, DATA, 8, 24)
1225 * The SVE simd_data field, for memory ops, contains either
1226 * rd (5 bits) or a shift count (2 bits).
1228 #define SVE_MTEDESC_SHIFT 5
1230 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1231 FIELD(MTEDESC, MIDX, 0, 4)
1232 FIELD(MTEDESC, TBI, 4, 2)
1233 FIELD(MTEDESC, TCMA, 6, 2)
1234 FIELD(MTEDESC, WRITE, 8, 1)
1235 FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */
1237 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
1238 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
1240 static inline int allocation_tag_from_addr(uint64_t ptr)
1242 return extract64(ptr, 56, 4);
1245 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
1247 return deposit64(ptr, 56, 4, rtag);
1250 /* Return true if tbi bits mean that the access is checked. */
1251 static inline bool tbi_check(uint32_t desc, int bit55)
1253 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
1256 /* Return true if tcma bits mean that the access is unchecked. */
1257 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag)
1260 * We had extracted bit55 and ptr_tag for other reasons, so fold
1261 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1263 bool match = ((ptr_tag + bit55) & 0xf) == 0;
1264 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1;
1265 return tcma && match;
1269 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1270 * for the tag to be present in the FAR_ELx register. But for user-only
1271 * mode, we do not have a TLB with which to implement this, so we must
1272 * remove the top byte.
1274 static inline uint64_t useronly_clean_ptr(uint64_t ptr)
1276 #ifdef CONFIG_USER_ONLY
1277 /* TBI0 is known to be enabled, while TBI1 is disabled. */
1278 ptr &= sextract64(ptr, 0, 56);
1283 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
1285 #ifdef CONFIG_USER_ONLY
1286 int64_t clean_ptr = sextract64(ptr, 0, 56);
1287 if (tbi_check(desc, clean_ptr < 0)) {
1294 /* Values for M-profile PSR.ECI for MVE insns */
1296 ECI_NONE = 0, /* No completed beats */
1297 ECI_A0 = 1, /* Completed: A0 */
1298 ECI_A0A1 = 2, /* Completed: A0, A1 */
1300 ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */
1301 ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */
1302 /* All other values reserved */
1305 /* Definitions for the PMU registers */
1306 #define PMCRN_MASK 0xf800
1307 #define PMCRN_SHIFT 11
1317 * Mask of PMCR bits writable by guest (not including WO bits like C, P,
1318 * which can be written as 1 to trigger behaviour but which stay RAZ).
1320 #define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1322 #define PMXEVTYPER_P 0x80000000
1323 #define PMXEVTYPER_U 0x40000000
1324 #define PMXEVTYPER_NSK 0x20000000
1325 #define PMXEVTYPER_NSU 0x10000000
1326 #define PMXEVTYPER_NSH 0x08000000
1327 #define PMXEVTYPER_M 0x04000000
1328 #define PMXEVTYPER_MT 0x02000000
1329 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1330 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1331 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1332 PMXEVTYPER_M | PMXEVTYPER_MT | \
1333 PMXEVTYPER_EVTCOUNT)
1335 #define PMCCFILTR 0xf8000000
1336 #define PMCCFILTR_M PMXEVTYPER_M
1337 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1339 static inline uint32_t pmu_num_counters(CPUARMState *env)
1341 ARMCPU *cpu = env_archcpu(env);
1343 return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
1346 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1347 static inline uint64_t pmu_counter_mask(CPUARMState *env)
1349 return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);
1352 #ifdef TARGET_AARCH64
1353 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1354 int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
1355 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
1356 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
1357 int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
1358 int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
1359 int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
1360 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
1361 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
1362 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
1363 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
1366 /* Read the CONTROL register as the MRS instruction would. */
1367 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
1370 * Return a pointer to the location where we currently store the
1371 * stack pointer for the requested security state and thread mode.
1372 * This pointer will become invalid if the CPU state is updated
1373 * such that the stack pointers are switched around (eg changing
1374 * the SPSEL control bit).
1376 uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
1377 bool threadmode, bool spsel);
1379 #ifdef CONFIG_USER_ONLY
1380 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
1382 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
1385 bool el_is_in_host(CPUARMState *env, int el);
1387 void aa32_max_features(ARMCPU *cpu);
1388 int exception_target_el(CPUARMState *env);
1389 bool arm_singlestep_active(CPUARMState *env);
1390 bool arm_generate_debug_exceptions(CPUARMState *env);
1395 * @ptr: selects between TTBR0 and TTBR1
1396 * @data: selects between TBI and TBID
1398 * Return a mask of the bits of @ptr that contain the authentication code.
1400 uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
1402 /* Add the cpreg definitions for debug related system registers */
1403 void define_debug_regs(ARMCPU *cpu);
1405 /* Effective value of MDCR_EL2 */
1406 static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
1408 return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;
1411 /* Powers of 2 for sve_vq_map et al. */
1412 #define SVE_VQ_POW2_MAP \
1413 ((1 << (1 - 1)) | (1 << (2 - 1)) | \
1414 (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
1417 * Return true if it is possible to take a fine-grained-trap to EL2.
1419 static inline bool arm_fgt_active(CPUARMState *env, int el)
1422 * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
1423 * that can affect EL0, but it is harmless to do the test also for
1424 * traps on registers that are only accessible at EL1 because if the test
1425 * returns true then we can't be executing at EL1 anyway.
1426 * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
1427 * traps from AArch32 only happen for the EL0 is AArch32 case.
1429 return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
1430 el < 2 && arm_is_el2_enabled(env) &&
1431 arm_el_is_aa64(env, 1) &&
1432 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
1433 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
1436 void assert_hflags_rebuild_correctly(CPUARMState *env);