2 * CRIS virtual CPU header
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 #include "exec/cpu-defs.h"
29 #define EXCP_BUSFAULT 3
33 /* CRIS-specific interrupt pending bits. */
34 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
36 /* CRUS CPU device objects interrupt lines. */
37 /* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
38 #define CRIS_CPU_IRQ 0
39 #define CRIS_CPU_NMI 1
41 /* Register aliases. R0 - R15 */
46 /* Support regs, P0 - P15 */
54 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
67 #define Q_FLAG 0x80000000
68 #define M_FLAG_V32 0x40000000
69 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
70 #define F_FLAG_V10 0x400
71 #define P_FLAG_V10 0x200
75 #define M_FLAG_V10 0x80
83 #define ALU_FLAGS 0x1F
85 /* Condition codes. */
108 typedef struct CPUCRISState {
110 /* P0 - P15 are referred to as special registers in the docs. */
113 /* Pseudo register for the PC. Not directly accessible on CRIS. */
116 /* Pseudo register for the kernel stack. */
124 /* Condition flag tracking. */
130 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
132 /* X flag at the time of cc snapshot. */
135 /* CRIS has certain insns that lockout interrupts. */
137 int interrupt_vector;
141 /* FIXME: add a check in the translator to avoid writing to support
142 register sets beyond the 4th. The ISA allows up to 256! but in
143 practice there is no core that implements more than 4.
145 Support function registers are used to control units close to the
146 core. Accesses do not pass down the normal hierarchy.
148 uint32_t sregs[4][16];
150 /* Linear feedback shift reg in the mmu. Used to provide pseudo
151 randomness for the 'hint' the mmu gives to sw for choosing valid
152 sets on TLB refills. */
153 uint32_t mmu_rand_lfsr;
156 * We just store the stores to the tlbset here for later evaluation
157 * when the hw needs access to them.
159 * One for I and another for D.
161 TLBSet tlbsets[2][4][16];
163 /* Fields up to this point are cleared by a CPU reset */
164 struct {} end_reset_fields;
166 /* Members from load_info on are preserved across resets. */
172 * @env: #CPUCRISState
181 CPUNegativeOffsetState neg;
186 #ifndef CONFIG_USER_ONLY
187 extern const VMStateDescription vmstate_cris_cpu;
190 void cris_cpu_do_interrupt(CPUState *cpu);
191 void crisv10_cpu_do_interrupt(CPUState *cpu);
192 bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
194 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
196 hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
198 int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
199 int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
200 int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
202 /* you can call this signal handler from your SIGBUS and SIGSEGV
203 signal handlers to inform the virtual CPU of exceptions. non zero
204 is returned if the signal was handled by the virtual CPU. */
205 int cpu_cris_signal_handler(int host_signum, void *pinfo,
208 void cris_initialize_tcg(void);
209 void cris_initialize_crisv10_tcg(void);
211 /* Instead of computing the condition codes after each CRIS instruction,
212 * QEMU just stores one operand (called CC_SRC), the result
213 * (called CC_DEST) and the type of operation (called CC_OP). When the
214 * condition codes are needed, the condition codes can be calculated
215 * using this information. Condition codes are not generated if they
216 * are only needed for conditional branches.
219 CC_OP_DYNAMIC, /* Use env->cc_op */
246 /* CRIS uses 8k pages. */
247 #define MMAP_SHIFT TARGET_PAGE_BITS
249 #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
250 #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
251 #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
253 #define cpu_signal_handler cpu_cris_signal_handler
255 /* MMU modes definitions */
256 #define MMU_USER_IDX 1
257 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
259 return !!(env->pregs[PR_CCS] & U_FLAG);
262 bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
263 MMUAccessType access_type, int mmu_idx,
264 bool probe, uintptr_t retaddr);
266 /* Support function regs. */
267 #define SFR_RW_GC_CFG 0][0
268 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
269 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
270 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
271 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
272 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
273 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
274 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
276 typedef CPUCRISState CPUArchState;
277 typedef CRISCPU ArchCPU;
279 #include "exec/cpu-all.h"
281 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
282 target_ulong *cs_base, uint32_t *flags)
286 *flags = env->dslot |
287 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
288 | X_FLAG | PFIX_FLAG));
291 #define cpu_list cris_cpu_list
292 void cris_cpu_list(void);