2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #ifndef HEXAGON_TRANSLATE_H
19 #define HEXAGON_TRANSLATE_H
21 #include "qemu/bitmap.h"
24 #include "exec/translator.h"
25 #include "tcg/tcg-op.h"
29 typedef struct DisasContext {
30 DisasContextBase base;
37 uint32_t num_hvx_insns;
38 int reg_log[REG_WRITES_MAX];
40 DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
41 DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
42 DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
43 int preg_log[PRED_WRITES_MAX];
45 DECLARE_BITMAP(pregs_written, NUM_PREGS);
46 DECLARE_BITMAP(pregs_read, NUM_PREGS);
47 uint8_t store_width[STORES_MAX];
48 bool s1_store_processed;
50 int future_vregs_num[VECTOR_TEMPS_MAX];
52 int tmp_vregs_num[VECTOR_TEMPS_MAX];
53 int vreg_log[NUM_VREGS];
55 DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
56 DECLARE_BITMAP(vregs_updated, NUM_VREGS);
57 DECLARE_BITMAP(vregs_select, NUM_VREGS);
58 DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
59 DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
60 DECLARE_BITMAP(vregs_read, NUM_VREGS);
61 int qreg_log[NUM_QREGS];
63 DECLARE_BITMAP(qregs_read, NUM_QREGS);
66 target_ulong branch_dest;
68 bool need_pkt_has_store_s1;
71 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
73 if (!test_bit(pnum, ctx->pregs_written)) {
74 ctx->preg_log[ctx->preg_log_idx] = pnum;
76 set_bit(pnum, ctx->pregs_written);
80 static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
82 set_bit(pnum, ctx->pregs_read);
85 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
88 if (rnum == HEX_REG_P3_0_ALIASED) {
89 for (int i = 0; i < NUM_PREGS; i++) {
90 ctx_log_pred_write(ctx, i);
93 if (!test_bit(rnum, ctx->regs_written)) {
94 ctx->reg_log[ctx->reg_log_idx] = rnum;
96 set_bit(rnum, ctx->regs_written);
99 set_bit(rnum, ctx->predicated_regs);
104 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
107 ctx_log_reg_write(ctx, rnum, is_predicated);
108 ctx_log_reg_write(ctx, rnum + 1, is_predicated);
111 static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
113 set_bit(rnum, ctx->regs_read);
116 static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
118 ctx_log_reg_read(ctx, rnum);
119 ctx_log_reg_read(ctx, rnum + 1);
122 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
123 int num, bool alloc_ok);
124 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
125 int num, bool alloc_ok);
127 static inline void ctx_log_vreg_write(DisasContext *ctx,
128 int rnum, VRegWriteType type,
131 if (type != EXT_TMP) {
132 if (!test_bit(rnum, ctx->vregs_updated)) {
133 ctx->vreg_log[ctx->vreg_log_idx] = rnum;
135 set_bit(rnum, ctx->vregs_updated);
138 set_bit(rnum, ctx->vregs_updated);
140 set_bit(rnum, ctx->predicated_future_vregs);
143 if (type == EXT_NEW) {
144 set_bit(rnum, ctx->vregs_select);
146 if (type == EXT_TMP) {
147 set_bit(rnum, ctx->vregs_updated_tmp);
149 set_bit(rnum, ctx->predicated_tmp_vregs);
154 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
155 int rnum, VRegWriteType type,
158 ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
159 ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
162 static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
164 set_bit(rnum, ctx->vregs_read);
167 static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
169 ctx_log_vreg_read(ctx, rnum ^ 0);
170 ctx_log_vreg_read(ctx, rnum ^ 1);
173 static inline void ctx_log_qreg_write(DisasContext *ctx,
176 ctx->qreg_log[ctx->qreg_log_idx] = rnum;
180 static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
182 set_bit(qnum, ctx->qregs_read);
185 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
186 extern TCGv hex_pred[NUM_PREGS];
187 extern TCGv hex_this_PC;
188 extern TCGv hex_slot_cancelled;
189 extern TCGv hex_branch_taken;
190 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
191 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
192 extern TCGv hex_new_pred_value[NUM_PREGS];
193 extern TCGv hex_pred_written;
194 extern TCGv hex_store_addr[STORES_MAX];
195 extern TCGv hex_store_width[STORES_MAX];
196 extern TCGv hex_store_val32[STORES_MAX];
197 extern TCGv_i64 hex_store_val64[STORES_MAX];
198 extern TCGv hex_dczero_addr;
199 extern TCGv hex_llsc_addr;
200 extern TCGv hex_llsc_val;
201 extern TCGv_i64 hex_llsc_val_i64;
202 extern TCGv hex_vstore_addr[VSTORES_MAX];
203 extern TCGv hex_vstore_size[VSTORES_MAX];
204 extern TCGv hex_vstore_pending[VSTORES_MAX];
206 bool is_gather_store_insn(DisasContext *ctx);
207 void process_store(DisasContext *ctx, int slot_num);
209 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
210 FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
212 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1)
213 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1)
214 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
215 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1)
216 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1)
217 FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2)