2 # HPPA instruction decode definitions.
4 # Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
6 # This library is free software; you can redistribute it and/or
7 # modify it under the terms of the GNU Lesser General Public
8 # License as published by the Free Software Foundation; either
9 # version 2.1 of the License, or (at your option) any later version.
11 # This library is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 # Lesser General Public License for more details.
16 # You should have received a copy of the GNU Lesser General Public
17 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 %assemble_sr3 13:1 14:2
25 %assemble_sr3x 13:1 14:2 !function=expand_sr3x
27 %assemble_11a 0:s1 4:10 !function=expand_shl3
28 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2
29 %assemble_12a 0:s1 3:11 !function=expand_shl2
30 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
31 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
33 %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
38 %sm_imm 16:10 !function=expand_sm_imm
49 %ma_to_m 5:1 13:1 !function=ma_to_m
50 %ma2_to_m 2:2 !function=ma_to_m
51 %pos_to_m 0:1 !function=pos_to_m
52 %neg_to_m 0:1 !function=neg_to_m
53 %a_to_m 2:1 !function=neg_to_m
54 %cmpbid_c 13:2 !function=cmpbid_c
57 # Argument set definitions
60 # All insns that need to form a virtual address should use this set.
61 &ldst t b x disp sp m scale size
65 &rrr_cf_d t r1 r2 cf d
66 &rrr_cf_d_sh t r1 r2 cf d sh
70 &rrb_c_f disp n c f r1 r2
71 &rrb_c_d_f disp n c d f r1 r2
72 &rib_c_f disp n c f r i
73 &rib_c_d_f disp n c d f r i
79 @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
80 @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
81 @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
82 @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
83 @rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
84 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
85 @rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
87 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
88 &rrb_c_f disp=%assemble_12
89 @rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \
90 &rrb_c_d_f disp=%assemble_12
91 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \
92 &rib_c_f disp=%assemble_12 i=%im5_16
93 @rib_cdf ...... r:5 ..... c:3 ........... n:1 . \
94 &rib_c_d_f disp=%assemble_12 i=%im5_16
100 break 000000 ----- ----- --- 00000000 -----
102 mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
103 mtctl 000000 t:5 r:5 --- 11000010 00000
104 mtsarcm 000000 01011 r:5 --- 11000110 00000
105 mtsm 000000 00000 r:5 000 11000011 00000
107 mfia 000000 ----- 00000 --- 10100101 t:5
108 mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
109 mfctl 000000 r:5 00000- e:1 -01000101 t:5
111 sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
113 ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
115 rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
116 ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
118 rfi 000000 ----- ----- --- 01100000 00000
119 rfi_r 000000 ----- ----- --- 01100101 00000
121 # These are artificial instructions used by QEMU firmware.
122 # They are allocated from the unassigned instruction space.
123 halt 1111 1111 1111 1101 1110 1010 1101 0000
124 reset 1111 1111 1111 1101 1110 1010 1101 0001
125 getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010
131 @addrx ...... b:5 x:5 .. ........ m:1 ..... \
132 &ldst disp=0 scale=0 t=0 sp=0 size=0
134 nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
135 nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
136 nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
137 nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
138 nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
139 nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
140 nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
142 probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
144 ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
145 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
146 sp=%assemble_sr3x data=0
148 # pcxl and pcxl2 Fast TLB Insert instructions
149 ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
151 pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
152 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
153 sp=%assemble_sr3x data=0
155 lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
156 &ldst disp=0 scale=0 size=0
158 lci 000001 ----- ----- -- 01001100 0 t:5
164 andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
165 and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
166 or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
167 xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
168 uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
169 ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
170 cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d
171 uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
172 uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
173 dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
174 dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
176 add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
177 add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
178 add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
179 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
180 add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
182 sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
183 sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
184 sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
185 sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
186 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
187 sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
189 ldil 001000 t:5 ..................... i=%assemble_21
190 addil 001010 r:5 ..................... i=%assemble_21
191 ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
193 addi 101101 ..... ..... .... 0 ........... @rri_cf
194 addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
195 addi_tc 101100 ..... ..... .... 0 ........... @rri_cf
196 addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
198 subi 100101 ..... ..... .... 0 ........... @rri_cf
199 subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
201 cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
207 @ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
208 @ldim5 ...... b:5 ..... sp:2 ......... t:5 \
209 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
210 @stim5 ...... b:5 t:5 sp:2 ......... ..... \
211 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
213 ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
214 ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
215 st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
216 ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
217 ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
218 lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
219 lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
220 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
221 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
223 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
224 &ldst t=%rt64 disp=0 size=2
225 @fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
226 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2
228 fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
229 fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
230 fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
231 fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi
233 @fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
235 @fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
236 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3
238 fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
239 fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
240 fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
241 fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
247 @ldstim14 ...... b:5 t:5 sp:2 .............. \
248 &ldst disp=%lowsign_14 x=0 scale=0 m=0
249 @ldstim14m ...... b:5 t:5 sp:2 .............. \
250 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
251 @ldstim12m ...... b:5 t:5 sp:2 .............. \
252 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
254 # LDB, LDH, LDW, LDWM
255 ld 010000 ..... ..... .. .............. @ldstim14 size=0
256 ld 010001 ..... ..... .. .............. @ldstim14 size=1
257 ld 010010 ..... ..... .. .............. @ldstim14 size=2
258 ld 010011 ..... ..... .. .............. @ldstim14m size=2
259 ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
261 # STB, STH, STW, STWM
262 st 011000 ..... ..... .. .............. @ldstim14 size=0
263 st 011001 ..... ..... .. .............. @ldstim14 size=1
264 st 011010 ..... ..... .. .............. @ldstim14 size=2
265 st 011011 ..... ..... .. .............. @ldstim14m size=2
266 st 011111 ..... ..... .. ...........10. @ldstim12m size=2
268 fldw 010110 b:5 ..... sp:2 .............. \
269 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
270 fldw 010111 b:5 ..... sp:2 ...........0.. \
271 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
273 fstw 011110 b:5 ..... sp:2 .............. \
274 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
275 fstw 011111 b:5 ..... sp:2 ...........0.. \
276 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
278 fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
279 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
281 fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
282 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
285 # Floating-point Multiply Add
288 &mpyadd rm1 rm2 ta ra tm
289 @mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
291 fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
292 fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
293 fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
294 fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
297 # Conditional Branches
300 bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
301 bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
303 movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
304 movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
306 cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0
307 cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1
308 cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0
309 cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1
310 cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0
311 cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1
312 cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \
313 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16
315 addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
316 addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
317 addbi 101001 ..... ..... ... ........... . . @rib_cf f=0
318 addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
321 # Shift, Extract, Deposit
324 shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
325 shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
327 extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
328 extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
330 depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5
331 depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5
332 depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16
333 depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16
340 @be ...... b:5 ..... ... ........... n:1 . \
341 &BE disp=%assemble_17 sp=%assemble_sr3
343 be 111000 ..... ..... ... ........... . . @be l=0
344 be 111001 ..... ..... ... ........... . . @be l=31
351 @bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17
354 bl 111010 ..... ..... 000 ........... . . @bl
355 bl 111010 ..... ..... 100 ........... . . @bl
356 # B,L (long displacement)
357 bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
359 b_gate 111010 ..... ..... 001 ........... . . @bl
360 blr 111010 l:5 x:5 010 00000000000 n:1 0
361 bv 111010 b:5 x:5 110 00000000000 n:1 0
362 bve 111010 b:5 00000 110 10000000000 n:1 - l=0
363 bve 111010 b:5 00000 111 10000000000 n:1 - l=2
366 # FP Fused Multiple-Add
369 fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \
370 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64
371 fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
381 @f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01
382 @f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01
383 @f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2
384 @f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3
386 @f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \
387 &fclass01 r=%ra64 t=%rt64
388 @f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01
390 @f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \
391 &fclass01 r=%ra64 t=%rt64
392 @f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64
393 @f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64
394 @f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01
396 @f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \
397 &fclass2 r1=%ra64 r2=%rb64
398 @f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2
400 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
401 &fclass3 r1=%ra64 r2=%rb64 t=%rt64
402 @f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5
404 # Floating point class 0
406 fid_f 001100 00000 00000 000 00 000000 00000
408 fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
409 fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0
410 fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0
411 frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0
412 fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0
413 fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0
415 fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0
416 fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0
417 fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0
418 frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0
419 fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0
420 fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0
422 fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0
423 fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0
424 fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0
425 frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0
426 fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0
427 fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0
429 fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0
430 fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0
431 fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0
432 frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0
433 fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0
434 fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0
436 # Floating point class 1
439 fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1
440 fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1
442 fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1
443 fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1
446 fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1
447 fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1
448 fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1
449 fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1
451 fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1
452 fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1
453 fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1
454 fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1
457 fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1
458 fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1
459 fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1
460 fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1
462 fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1
463 fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1
464 fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1
465 fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1
468 fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1
469 fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1
470 fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1
471 fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1
473 fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1
474 fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1
475 fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1
476 fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1
479 fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1
480 fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1
481 fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1
482 fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1
484 fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1
485 fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1
486 fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1
487 fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1
490 fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1
491 fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1
492 fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1
493 fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1
495 fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1
496 fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1
497 fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1
498 fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1
501 fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1
502 fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1
503 fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1
504 fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1
506 fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1
507 fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1
508 fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1
509 fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1
511 # Floating point class 2
513 ftest 001100 00000 00000 y:3 00 10000 1 c:5
515 fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2
516 fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2
518 fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2
519 fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2
521 # Floating point class 3
523 fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3
524 fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3
525 fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3
526 fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3
528 fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3
529 fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3
530 fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3
531 fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3
533 fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3
534 fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3
535 fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3
536 fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3
538 fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3
539 fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3
540 fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3
541 fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
543 xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64