2 * m68k virtual CPU header
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #define TARGET_LONG_BITS 32
26 #define CPUArchState struct CPUM68KState
28 #include "qemu-common.h"
29 #include "exec/cpu-defs.h"
31 #include "fpu/softfloat.h"
43 #define EXCP_ACCESS 2 /* Access (MMU) error. */
44 #define EXCP_ADDRESS 3 /* Address error. */
45 #define EXCP_ILLEGAL 4 /* Illegal instruction. */
46 #define EXCP_DIV0 5 /* Divide by zero */
47 #define EXCP_PRIVILEGE 8 /* Privilege violation. */
49 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
50 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
51 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
52 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
53 #define EXCP_FORMAT 14 /* RTE format error. */
54 #define EXCP_UNINITIALIZED 15
55 #define EXCP_TRAP0 32 /* User trap #0. */
56 #define EXCP_TRAP15 47 /* User trap #15. */
57 #define EXCP_UNSUPPORTED 61
60 #define EXCP_RTE 0x100
61 #define EXCP_HALT_INSN 0x101
63 #define NB_MMU_MODES 2
64 #define TARGET_INSN_START_EXTRA_WORDS 1
66 typedef struct CPUM68KState {
72 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
76 /* Condition flags. */
78 uint32_t cc_x; /* always 0/1 */
79 uint32_t cc_n; /* in bit 31 (i.e. negative) */
80 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
81 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
82 uint32_t cc_z; /* == 0 or unused */
88 float_status fp_status;
91 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
92 two 8-bit parts. We store a single 64-bit value and
93 rearrange/extend this when changing modes. */
103 /* Control registers. */
112 uint32_t qregs[MAX_QREGS];
114 /* Fields up to this point are cleared by a CPU reset */
115 struct {} end_reset_fields;
119 /* Fields from here on are preserved across CPU reset. */
125 * @env: #CPUM68KState
127 * A Motorola 68k CPU.
137 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
139 return container_of(env, M68kCPU, env);
142 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
144 #define ENV_OFFSET offsetof(M68kCPU, env)
146 void m68k_cpu_do_interrupt(CPUState *cpu);
147 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
148 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
150 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
151 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
152 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
154 void m68k_tcg_init(void);
155 void m68k_cpu_init_gdb(M68kCPU *cpu);
156 M68kCPU *cpu_m68k_init(const char *cpu_model);
157 /* you can call this signal handler from your SIGBUS and SIGSEGV
158 signal handlers to inform the virtual CPU of exceptions. non zero
159 is returned if the signal was handled by the virtual CPU. */
160 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
162 uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
163 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
166 /* Instead of computing the condition codes after each m68k instruction,
167 * QEMU just stores one operand (called CC_SRC), the result
168 * (called CC_DEST) and the type of operation (called CC_OP). When the
169 * condition codes are needed, the condition codes can be calculated
170 * using this information. Condition codes are not generated if they
171 * are only needed for conditional branches.
174 /* Translator only -- use env->cc_op. */
177 /* Each flag bit computed into cc_[xcnvz]. */
180 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
181 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
182 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
184 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
185 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
187 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
208 /* CACR fields are implementation defined, but some bits are common. */
209 #define M68K_CACR_EUSP 0x10
211 #define MACSR_PAV0 0x100
212 #define MACSR_OMC 0x080
213 #define MACSR_SU 0x040
214 #define MACSR_FI 0x020
215 #define MACSR_RT 0x010
216 #define MACSR_N 0x008
217 #define MACSR_Z 0x004
218 #define MACSR_V 0x002
219 #define MACSR_EV 0x001
221 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
222 void m68k_switch_sp(CPUM68KState *env);
224 #define M68K_FPCR_PREC (1 << 6)
226 void do_m68k_semihosting(CPUM68KState *env, int nr);
228 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
229 Each feature covers the subset of instructions common to the
230 ISA revisions mentioned. */
234 M68K_FEATURE_CF_ISA_A,
235 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
236 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
237 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
240 M68K_FEATURE_CF_EMAC,
241 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
242 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
243 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
244 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
245 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
246 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
247 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
248 M68K_FEATURE_BCCL, /* Long conditional branches. */
249 M68K_FEATURE_BITFIELD, /* Bit field insns. */
255 static inline int m68k_feature(CPUM68KState *env, int feature)
257 return (env->features & (1u << feature)) != 0;
260 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
262 void register_m68k_insns (CPUM68KState *env);
264 #ifdef CONFIG_USER_ONLY
265 /* Coldfire Linux uses 8k pages
266 * and m68k linux uses 4k pages
267 * use the smaller one
269 #define TARGET_PAGE_BITS 12
271 /* Smallest TLB entry size is 1k. */
272 #define TARGET_PAGE_BITS 10
275 #define TARGET_PHYS_ADDR_SPACE_BITS 32
276 #define TARGET_VIRT_ADDR_SPACE_BITS 32
278 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
280 #define cpu_signal_handler cpu_m68k_signal_handler
281 #define cpu_list m68k_cpu_list
283 /* MMU modes definitions */
284 #define MMU_MODE0_SUFFIX _kernel
285 #define MMU_MODE1_SUFFIX _user
286 #define MMU_USER_IDX 1
287 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
289 return (env->sr & SR_S) == 0 ? 1 : 0;
292 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
295 #include "exec/cpu-all.h"
297 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
298 target_ulong *cs_base, uint32_t *flags)
302 *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
303 | (env->sr & SR_S) /* Bit 13 */
304 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */