target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "exec/exec-all.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31 }
  32
  33 static bool openrisc_cpu_has_work(CPUState *cs)
  34 {
  35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  36                                     CPU_INTERRUPT_TIMER);
  37 }
  38
  39 /* CPUClass::reset() */
  40 static void openrisc_cpu_reset(CPUState *s)
  41 {
  42     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  43     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  44
  45     occ->parent_reset(s);
  46
  47     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  48
  49     cpu->env.pc = 0x100;
  50     cpu->env.sr = SR_FO | SR_SM;
  51     s->exception_index = -1;
  52
  53     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  54     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  55     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  56     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  57
  58 #ifndef CONFIG_USER_ONLY
  59     cpu->env.picmr = 0x00000000;
  60     cpu->env.picsr = 0x00000000;
  61
  62     cpu->env.ttmr = 0x00000000;
  63     cpu->env.ttcr = 0x00000000;
  64 #endif
  65 }
  66
  67 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  68 {
  69     cpu->feature |= feature;
  70     cpu->env.cpucfgr = cpu->feature;
  71 }
  72
  73 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  74 {
  75     CPUState *cs = CPU(dev);
  76     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  77     Error *local_err = NULL;
  78
  79     cpu_exec_realizefn(cs, &local_err);
  80     if (local_err != NULL) {
  81         error_propagate(errp, local_err);
  82         return;
  83     }
  84
  85     qemu_init_vcpu(cs);
  86     cpu_reset(cs);
  87
  88     occ->parent_realize(dev, errp);
  89 }
  90
  91 static void openrisc_cpu_initfn(Object *obj)
  92 {
  93     CPUState *cs = CPU(obj);
  94     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  95     static int inited;
  96
  97     cs->env_ptr = &cpu->env;
  98
  99 #ifndef CONFIG_USER_ONLY
 100     cpu_openrisc_mmu_init(cpu);
 101 #endif
 102
 103     if (tcg_enabled() && !inited) {
 104         inited = 1;
 105         openrisc_translate_init();
 106     }
 107 }
 108
 109 /* CPU models */
 110
 111 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 112 {
 113     ObjectClass *oc;
 114     char *typename;
 115
 116     if (cpu_model == NULL) {
 117         return NULL;
 118     }
 119
 120     typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
 121     oc = object_class_by_name(typename);
 122     g_free(typename);
 123     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 124                        object_class_is_abstract(oc))) {
 125         return NULL;
 126     }
 127     return oc;
 128 }
 129
 130 static void or1200_initfn(Object *obj)
 131 {
 132     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 133
 134     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 135     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 136 }
 137
 138 static void openrisc_any_initfn(Object *obj)
 139 {
 140     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 141
 142     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 143 }
 144
 145 typedef struct OpenRISCCPUInfo {
 146     const char *name;
 147     void (*initfn)(Object *obj);
 148 } OpenRISCCPUInfo;
 149
 150 static const OpenRISCCPUInfo openrisc_cpus[] = {
 151     { .name = "or1200",      .initfn = or1200_initfn },
 152     { .name = "any",         .initfn = openrisc_any_initfn },
 153 };
 154
 155 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 156 {
 157     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 158     CPUClass *cc = CPU_CLASS(occ);
 159     DeviceClass *dc = DEVICE_CLASS(oc);
 160
 161     occ->parent_realize = dc->realize;
 162     dc->realize = openrisc_cpu_realizefn;
 163
 164     occ->parent_reset = cc->reset;
 165     cc->reset = openrisc_cpu_reset;
 166
 167     cc->class_by_name = openrisc_cpu_class_by_name;
 168     cc->has_work = openrisc_cpu_has_work;
 169     cc->do_interrupt = openrisc_cpu_do_interrupt;
 170     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 171     cc->dump_state = openrisc_cpu_dump_state;
 172     cc->set_pc = openrisc_cpu_set_pc;
 173     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 174     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 175 #ifdef CONFIG_USER_ONLY
 176     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
 177 #else
 178     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 179     dc->vmsd = &vmstate_openrisc_cpu;
 180 #endif
 181     cc->gdb_num_core_regs = 32 + 3;
 182 }
 183
 184 static void cpu_register(const OpenRISCCPUInfo *info)
 185 {
 186     TypeInfo type_info = {
 187         .parent = TYPE_OPENRISC_CPU,
 188         .instance_size = sizeof(OpenRISCCPU),
 189         .instance_init = info->initfn,
 190         .class_size = sizeof(OpenRISCCPUClass),
 191     };
 192
 193     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 194     type_register(&type_info);
 195     g_free((void *)type_info.name);
 196 }
 197
 198 static const TypeInfo openrisc_cpu_type_info = {
 199     .name = TYPE_OPENRISC_CPU,
 200     .parent = TYPE_CPU,
 201     .instance_size = sizeof(OpenRISCCPU),
 202     .instance_init = openrisc_cpu_initfn,
 203     .abstract = true,
 204     .class_size = sizeof(OpenRISCCPUClass),
 205     .class_init = openrisc_cpu_class_init,
 206 };
 207
 208 static void openrisc_cpu_register_types(void)
 209 {
 210     int i;
 211
 212     type_register_static(&openrisc_cpu_type_info);
 213     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 214         cpu_register(&openrisc_cpus[i]);
 215     }
 216 }
 217
 218 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 219 {
 220     return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
 221 }
 222
 223 /* Sort alphabetically by type name, except for "any". */
 224 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 225 {
 226     ObjectClass *class_a = (ObjectClass *)a;
 227     ObjectClass *class_b = (ObjectClass *)b;
 228     const char *name_a, *name_b;
 229
 230     name_a = object_class_get_name(class_a);
 231     name_b = object_class_get_name(class_b);
 232     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 233         return 1;
 234     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 235         return -1;
 236     } else {
 237         return strcmp(name_a, name_b);
 238     }
 239 }
 240
 241 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 242 {
 243     ObjectClass *oc = data;
 244     CPUListState *s = user_data;
 245     const char *typename;
 246     char *name;
 247
 248     typename = object_class_get_name(oc);
 249     name = g_strndup(typename,
 250                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 251     (*s->cpu_fprintf)(s->file, "  %s\n",
 252                       name);
 253     g_free(name);
 254 }
 255
 256 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 257 {
 258     CPUListState s = {
 259         .file = f,
 260         .cpu_fprintf = cpu_fprintf,
 261     };
 262     GSList *list;
 263
 264     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 265     list = g_slist_sort(list, openrisc_cpu_list_compare);
 266     (*cpu_fprintf)(f, "Available CPUs:\n");
 267     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 268     g_slist_free(list);
 269 }
 270
 271 type_init(openrisc_cpu_register_types)